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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#ifndef _DML2_WRAPPER_H_28#define _DML2_WRAPPER_H_29 30#include "os_types.h"31 32#define DML2_MAX_NUM_DPM_LVL 3033 34struct dml2_context;35struct display_mode_lib_st;36struct dc;37struct pipe_ctx;38struct dc_plane_state;39struct dc_sink;40struct dc_stream_state;41struct resource_context;42struct display_stream_compressor;43 44// Configuration of the MALL on the SoC45struct dml2_soc_mall_info {46 // Cache line size of 0 means MALL is not enabled/present47 unsigned int cache_line_size_bytes;48 unsigned int cache_num_ways;49 unsigned int max_cab_allocation_bytes;50 51 unsigned int mblk_width_pixels;52 unsigned int mblk_size_bytes;53 unsigned int mblk_height_4bpe_pixels;54 unsigned int mblk_height_8bpe_pixels;55};56 57// Output of DML2 for clock requirements58struct dml2_dcn_clocks {59 unsigned int dispclk_khz;60 unsigned int dcfclk_khz;61 unsigned int fclk_khz;62 unsigned int uclk_mts;63 unsigned int phyclk_khz;64 unsigned int socclk_khz;65 unsigned int ref_dtbclk_khz;66 bool p_state_supported;67 unsigned int cab_num_ways_required;68 unsigned int dcfclk_khz_ds;69};70 71struct dml2_dc_callbacks {72 struct dc *dc;73 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);74 void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);75 bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);76 bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);77 bool (*update_pipes_for_stream_with_slice_count)(78 struct dc_state *new_ctx,79 const struct dc_state *cur_ctx,80 const struct resource_pool *pool,81 const struct dc_stream_state *stream,82 int new_slice_count);83 bool (*update_pipes_for_plane_with_slice_count)(84 struct dc_state *new_ctx,85 const struct dc_state *cur_ctx,86 const struct resource_pool *pool,87 const struct dc_plane_state *plane,88 int slice_count);89 int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);90 int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);91 int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);92 int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);93 struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);94 struct pipe_ctx *(*get_otg_master_for_stream)(95 struct resource_context *res_ctx,96 const struct dc_stream_state *stream);97 int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,98 struct resource_context *res_ctx,99 struct pipe_ctx *opp_heads[MAX_PIPES]);100 int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane,101 struct resource_context *res_ctx,102 struct pipe_ctx *dpp_pipes[MAX_PIPES]);103 struct dc_stream_status *(*get_stream_status)(104 struct dc_state *state,105 const struct dc_stream_state *stream);106 struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id);107 unsigned int (*get_max_flickerless_instant_vtotal_increase)(108 struct dc_stream_state *stream,109 bool is_gaming);110};111 112struct dml2_dc_svp_callbacks {113 struct dc *dc;114 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);115 struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,116 struct dc_state *state,117 struct dc_stream_state *main_stream);118 struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc,119 struct dc_state *state,120 struct dc_plane_state *main_plane);121 enum dc_status (*add_phantom_stream)(const struct dc *dc,122 struct dc_state *state,123 struct dc_stream_state *phantom_stream,124 struct dc_stream_state *main_stream);125 bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);126 bool (*remove_phantom_plane)(const struct dc *dc,127 struct dc_stream_state *stream,128 struct dc_plane_state *plane_state,129 struct dc_state *context);130 enum dc_status (*remove_phantom_stream)(const struct dc *dc,131 struct dc_state *state,132 struct dc_stream_state *stream);133 void (*release_phantom_plane)(const struct dc *dc,134 struct dc_state *state,135 struct dc_plane_state *plane);136 void (*release_phantom_stream)(const struct dc *dc,137 struct dc_state *state,138 struct dc_stream_state *stream);139 void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);140 enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);141 enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream);142 struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream);143 bool (*remove_phantom_streams_and_planes)(144 const struct dc *dc,145 struct dc_state *state);146 void (*release_phantom_streams_and_planes)(147 const struct dc *dc,148 struct dc_state *state);149 unsigned int (*calculate_mall_ways_from_bytes)(150 const struct dc *dc,151 unsigned int total_size_in_mall_bytes);152};153 154struct dml2_clks_table_entry {155 unsigned int dcfclk_mhz;156 unsigned int fclk_mhz;157 unsigned int memclk_mhz;158 unsigned int socclk_mhz;159 unsigned int dtbclk_mhz;160 unsigned int dispclk_mhz;161 unsigned int dppclk_mhz;162};163 164struct dml2_clks_num_entries {165 unsigned int num_dcfclk_levels;166 unsigned int num_fclk_levels;167 unsigned int num_memclk_levels;168 unsigned int num_socclk_levels;169 unsigned int num_dtbclk_levels;170 unsigned int num_dispclk_levels;171 unsigned int num_dppclk_levels;172};173 174struct dml2_clks_limit_table {175 struct dml2_clks_table_entry clk_entries[DML2_MAX_NUM_DPM_LVL];176 struct dml2_clks_num_entries num_entries_per_clk;177 unsigned int num_states;178};179 180// Various overrides, per ASIC or per SKU specific, or for debugging purpose when/if available181struct dml2_soc_bbox_overrides {182 double xtalclk_mhz;183 double dchub_refclk_mhz;184 double dprefclk_mhz;185 double disp_pll_vco_speed_mhz;186 double urgent_latency_us;187 double sr_exit_latency_us;188 double sr_enter_plus_exit_latency_us;189 double sr_exit_z8_time_us;190 double sr_enter_plus_exit_z8_time_us;191 double dram_clock_change_latency_us;192 double fclk_change_latency_us;193 unsigned int dram_num_chan;194 unsigned int dram_chanel_width_bytes;195 struct dml2_clks_limit_table clks_table;196};197 198enum dml2_force_pstate_methods {199 dml2_force_pstate_method_auto = 0,200 dml2_force_pstate_method_vactive,201 dml2_force_pstate_method_vblank,202 dml2_force_pstate_method_drr,203 dml2_force_pstate_method_subvp,204};205 206struct dml2_configuration_options {207 int dcn_pipe_count;208 bool use_native_pstate_optimization;209 bool enable_windowed_mpo_odm;210 bool use_native_soc_bb_construction;211 bool skip_hw_state_mapping;212 bool optimize_odm_4to1;213 bool minimize_dispclk_using_odm;214 bool override_det_buffer_size_kbytes;215 struct dml2_dc_callbacks callbacks;216 struct {217 bool force_disable_subvp;218 bool force_enable_subvp;219 unsigned int subvp_fw_processing_delay_us;220 unsigned int subvp_pstate_allow_width_us;221 unsigned int subvp_prefetch_end_to_mall_start_us;222 unsigned int subvp_swath_height_margin_lines;223 struct dml2_dc_svp_callbacks callbacks;224 } svp_pstate;225 struct dml2_soc_mall_info mall_cfg;226 struct dml2_soc_bbox_overrides bbox_overrides;227 unsigned int max_segments_per_hubp;228 unsigned int det_segment_size;229 /* Only for debugging purposes when initializing SOCBB params via tool for DML21. */230 struct socbb_ip_params_external *external_socbb_ip_params;231 struct {232 bool force_pstate_method_enable;233 enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];234 } pmo;235 bool map_dc_pipes_with_callbacks;236 237 bool use_clock_dc_limits;238 bool gpuvm_enable;239 bool force_tdlut_enable;240 struct dml2_soc_bb *bb_from_dmub;241};242 243/*244 * dml2_create - Creates dml2_context.245 * @in_dc: dc.246 * @config: dml2 configuration options.247 * @dml2: Created dml2 context.248 *249 * Create and destroy of DML2 is done as part of dc_state creation250 * and dc_state_free. DML2 IP, SOC and STATES are initialized at251 * creation time.252 *253 * Return: True if dml2 is successfully created, false otherwise.254 */255bool dml2_create(const struct dc *in_dc,256 const struct dml2_configuration_options *config,257 struct dml2_context **dml2);258 259void dml2_destroy(struct dml2_context *dml2);260void dml2_copy(struct dml2_context *dst_dml2,261 struct dml2_context *src_dml2);262bool dml2_create_copy(struct dml2_context **dst_dml2,263 struct dml2_context *src_dml2);264void dml2_reinit(const struct dc *in_dc,265 const struct dml2_configuration_options *config,266 struct dml2_context **dml2);267 268/*269 * dml2_validate - Determines if a display configuration is supported or not.270 * @in_dc: dc.271 * @context: dc_state to be validated.272 * @fast_validate: Fast validate will not populate context.res_ctx.273 *274 * DML1.0 compatible interface for validation.275 *276 * Based on fast_validate option internally would call:277 *278 * -dml2_validate_and_build_resource - for non fast_validate option279 * Calculates if dc_state can be supported on the SOC, and attempts to280 * optimize the power management feature supports versus minimum clocks.281 * If supported, also builds out_new_hw_state to represent the hw programming282 * for the new dc state.283 *284 * -dml2_validate_only - for fast_validate option285 * Calculates if dc_state can be supported on the SOC (i.e. at maximum286 * clocks) with all mandatory power features enabled.287 288 * Context: Two threads may not invoke this function concurrently unless they reference289 * separate dc_states for validation.290 * Return: True if mode is supported, false otherwise.291 */292bool dml2_validate(const struct dc *in_dc,293 struct dc_state *context,294 struct dml2_context *dml2,295 bool fast_validate);296 297/*298 * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info.299 * @dml2: input dml2 context pointer.300 * @fclk_change_support: output pointer holding the fclk change support info (vactive, vblank, unsupported).301 * @dram_clk_change_support: output pointer holding the uclk change support info (vactive, vblank, unsupported).302 */303void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,304 unsigned int *fclk_change_support, unsigned int *dram_clk_change_support);305void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);306#endif //_DML2_WRAPPER_H_307