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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "core_types.h"28#include "dcn35/dcn35_dpp.h"29#include "reg_helper.h"30 31#define REG(reg) dpp->tf_regs->reg32 33#define CTX dpp->base.ctx34 35#undef FN36#define FN(reg_name, field_name) \37 ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \38 ((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name39 40void dpp35_dppclk_control(41 struct dpp *dpp_base,42 bool dppclk_div,43 bool enable)44{45 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);46 47 if (enable) {48 if (dpp->tf_mask->DPPCLK_RATE_CONTROL)49 REG_UPDATE_2(DPP_CONTROL,50 DPPCLK_RATE_CONTROL, dppclk_div,51 DPP_CLOCK_ENABLE, 1);52 else53 REG_UPDATE_2(DPP_CONTROL,54 DPP_CLOCK_ENABLE, 1,55 DISPCLK_R_GATE_DISABLE, 1);56 } else57 REG_UPDATE_2(DPP_CONTROL,58 DPP_CLOCK_ENABLE, 0,59 DISPCLK_R_GATE_DISABLE, 0);60}61 62void dpp35_program_bias_and_scale_fcnv(63 struct dpp *dpp_base,64 struct dc_bias_and_scale *params)65{66 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);67 68 if (!params->bias_and_scale_valid) {69 REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0);70 REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0);71 REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0);72 73 REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000);74 REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000);75 REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000);76 } else {77 REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params->bias_red);78 REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params->bias_green);79 REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params->bias_blue);80 81 REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params->scale_red);82 REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, params->scale_green);83 REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, params->scale_blue);84 }85}86 87static struct dpp_funcs dcn35_dpp_funcs = {88 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,89 .dpp_read_state = dpp30_read_state,90 .dpp_reset = dpp_reset,91 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,92 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,93 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,94 .dpp_set_csc_adjustment = NULL,95 .dpp_set_csc_default = NULL,96 .dpp_program_regamma_pwl = NULL,97 .dpp_set_pre_degam = dpp3_set_pre_degam,98 .dpp_program_input_lut = NULL,99 .dpp_full_bypass = dpp1_full_bypass,100 .dpp_setup = dpp3_cnv_setup,101 .dpp_program_degamma_pwl = NULL,102 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,103 .dpp_program_cm_bias = dpp3_program_cm_bias,104 105 .dpp_program_blnd_lut = NULL, // BLNDGAM is removed completely in DCN3.2 DPP106 .dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)107 .dpp_program_3dlut = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)108 109 .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv,110 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,111 .set_cursor_attributes = dpp3_set_cursor_attributes,112 .set_cursor_position = dpp1_set_cursor_position,113 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,114 .dpp_dppclk_control = dpp35_dppclk_control,115 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,116 .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap,117};118 119 120bool dpp35_construct(121 struct dcn3_dpp *dpp, struct dc_context *ctx,122 uint32_t inst, const struct dcn3_dpp_registers *tf_regs,123 const struct dcn35_dpp_shift *tf_shift,124 const struct dcn35_dpp_mask *tf_mask)125{126 bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,127 (const struct dcn3_dpp_shift *)(tf_shift),128 (const struct dcn3_dpp_mask *)(tf_mask));129 130 dpp->base.funcs = &dcn35_dpp_funcs;131 return ret;132}133 134void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)135{136 REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);137}138