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1/* Copyright 2023 Advanced Micro Devices, Inc.2 *3 * Permission is hereby granted, free of charge, to any person obtaining a4 * copy of this software and associated documentation files (the "Software"),5 * to deal in the Software without restriction, including without limitation6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,7 * and/or sell copies of the Software, and to permit persons to whom the8 * Software is furnished to do so, subject to the following conditions:9 *10 * The above copyright notice and this permission notice shall be included in11 * all copies or substantial portions of the Software.12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19 * OTHER DEALINGS IN THE SOFTWARE.20 *21 * Authors: AMD22 *23 */24 25#ifndef __DCN401_DPP_H__26#define __DCN401_DPP_H__27 28#include "dcn20/dcn20_dpp.h"29#include "dcn30/dcn30_dpp.h"30#include "dcn32/dcn32_dpp.h"31 32#define TO_DCN401_DPP(dpp)\33 container_of(dpp, struct dcn401_dpp, base)34 35#define DPP_REG_LIST_SH_MASK_DCN401_COMMON(mask_sh)\36 TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\37 TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\38 TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\39 TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\40 TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\41 TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\42 TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\43 TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\44 TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\45 TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\46 TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\47 TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\48 TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\49 TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\50 TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\51 TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\52 TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\53 TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\54 TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\55 TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\56 TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\57 TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\58 TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\59 TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\60 TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\61 TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\62 TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\63 TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\64 TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\65 TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\66 TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\67 TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\68 TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\69 TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\70 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\71 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\72 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\73 TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\74 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\75 TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\76 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\77 TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\78 TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\79 TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\80 TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\81 TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\82 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\83 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\84 TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\85 TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\86 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\87 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\88 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\89 TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\90 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\91 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\92 TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\93 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\94 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\95 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\96 TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\97 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\98 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\99 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\100 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\101 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\102 TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\103 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\104 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\105 TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\106 TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\107 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\108 TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\109 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\110 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\111 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\112 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\113 TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\114 TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\115 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\116 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\117 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\118 TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\119 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\120 TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\121 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\122 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\123 TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\124 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \125 TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \126 TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \127 TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \128 TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \129 TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \130 TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \131 TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \132 TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \133 TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \134 TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \135 TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \136 TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \137 TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \138 TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \139 TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \140 TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \141 TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \142 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \143 TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \144 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \145 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \146 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \147 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \148 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \149 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \150 TF_SF(CM_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \151 TF_SF(CM_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \152 TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, mask_sh), \153 TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, mask_sh), \154 TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, mask_sh), \155 TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, mask_sh), \156 TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE, mask_sh), \157 TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, mask_sh), \158 TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_COEF_FORMAT, mask_sh), \159 TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C11_A, mask_sh), \160 TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C12_A, mask_sh), \161 TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C13_A, mask_sh), \162 TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C14_A, mask_sh), \163 TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C21_A, mask_sh), \164 TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C22_A, mask_sh), \165 TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C23_A, mask_sh), \166 TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C24_A, mask_sh), \167 TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C31_A, mask_sh), \168 TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C32_A, mask_sh), \169 TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C33_A, mask_sh), \170 TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C34_A, mask_sh), \171 TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \172 TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \173 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \174 TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \175 TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \176 TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \177 TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \178 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \179 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \180 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \181 TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \182 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \183 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \184 TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \185 TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \186 TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \187 TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \188 TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \189 TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \190 TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \191 TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \192 TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \193 TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \194 TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \195 TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \196 TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, LUMA_KEYER_EN, mask_sh), \197 TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \198 TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \199 TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \200 TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \201 TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \202 TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \203 TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \204 TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \205 TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \206 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \207 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \208 TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\209 TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\210 TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\211 TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\212 TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\213 TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\214 TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_EN, mask_sh),\215 TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_RINGEST_FORCE_EN, mask_sh),\216 TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_2TAP_SHARP_FACTOR, mask_sh),\217 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF1_EN, mask_sh),\218 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_MODE, mask_sh),\219 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF3_MODE, mask_sh),\220 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT1_GAIN, mask_sh),\221 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT2_GAIN, mask_sh),\222 TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_ROC_GAIN, mask_sh),\223 TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, mask_sh),\224 TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, mask_sh),\225 TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN1, mask_sh),\226 TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, mask_sh),\227 TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXA, mask_sh),\228 TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXB, mask_sh),\229 TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINA, mask_sh),\230 TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINB, mask_sh),\231 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_IN_SEG0, mask_sh),\232 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_BASE_SEG0, mask_sh),\233 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, mask_sh),\234 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_IN_SEG1, mask_sh),\235 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_BASE_SEG1, mask_sh),\236 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, mask_sh),\237 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_IN_SEG2, mask_sh),\238 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_BASE_SEG2, mask_sh),\239 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, mask_sh),\240 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_IN_SEG3, mask_sh),\241 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_BASE_SEG3, mask_sh),\242 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, mask_sh),\243 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_IN_SEG4, mask_sh),\244 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_BASE_SEG4, mask_sh),\245 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, mask_sh),\246 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_IN_SEG5, mask_sh),\247 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_BASE_SEG5, mask_sh),\248 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, mask_sh),\249 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_IN_SEG6, mask_sh),\250 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_BASE_SEG6, mask_sh),\251 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, mask_sh),\252 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_IN_SEG7, mask_sh),\253 TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_BASE_SEG7, mask_sh),\254 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_IN_SEG0, mask_sh),\255 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_BASE_SEG0, mask_sh),\256 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, mask_sh),\257 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_IN_SEG1, mask_sh),\258 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_BASE_SEG1, mask_sh),\259 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, mask_sh),\260 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_IN_SEG2, mask_sh),\261 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_BASE_SEG2, mask_sh),\262 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, mask_sh),\263 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_IN_SEG3, mask_sh),\264 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_BASE_SEG3, mask_sh),\265 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, mask_sh),\266 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_IN_SEG4, mask_sh),\267 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_BASE_SEG4, mask_sh),\268 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, mask_sh),\269 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_IN_SEG5, mask_sh),\270 TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_BASE_SEG5, mask_sh),\271 TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_EN, mask_sh),\272 TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_RINGEST_FORCE_EN, mask_sh),\273 TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_2TAP_SHARP_FACTOR, mask_sh),\274 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF1_EN, mask_sh),\275 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_MODE, mask_sh),\276 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF3_MODE, mask_sh),\277 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT1_GAIN, mask_sh),\278 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT2_GAIN, mask_sh),\279 TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_ROC_GAIN, mask_sh),\280 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, mask_sh),\281 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, mask_sh),\282 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, mask_sh),\283 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, mask_sh),\284 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, mask_sh),\285 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, mask_sh),\286 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, mask_sh),\287 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, mask_sh),\288 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN1, mask_sh),\289 TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, mask_sh),\290 TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXA, mask_sh),\291 TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXB, mask_sh),\292 TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINA, mask_sh),\293 TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINB, mask_sh),\294 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_IN_SEG0, mask_sh),\295 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_BASE_SEG0, mask_sh),\296 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, mask_sh),\297 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_IN_SEG1, mask_sh),\298 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_BASE_SEG1, mask_sh),\299 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, mask_sh),\300 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_IN_SEG2, mask_sh),\301 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_BASE_SEG2, mask_sh),\302 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, mask_sh),\303 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_IN_SEG3, mask_sh),\304 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_BASE_SEG3, mask_sh),\305 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, mask_sh),\306 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_IN_SEG4, mask_sh),\307 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_BASE_SEG4, mask_sh),\308 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, mask_sh),\309 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_IN_SEG5, mask_sh),\310 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_BASE_SEG5, mask_sh),\311 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, mask_sh),\312 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_IN_SEG6, mask_sh),\313 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_BASE_SEG6, mask_sh),\314 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, mask_sh),\315 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_IN_SEG7, mask_sh),\316 TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_BASE_SEG7, mask_sh),\317 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_IN_SEG0, mask_sh),\318 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_BASE_SEG0, mask_sh),\319 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, mask_sh),\320 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_IN_SEG1, mask_sh),\321 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_BASE_SEG1, mask_sh),\322 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, mask_sh),\323 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_IN_SEG2, mask_sh),\324 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_BASE_SEG2, mask_sh),\325 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, mask_sh),\326 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_IN_SEG3, mask_sh),\327 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_BASE_SEG3, mask_sh),\328 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, mask_sh),\329 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_IN_SEG4, mask_sh),\330 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_BASE_SEG4, mask_sh),\331 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, mask_sh),\332 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_IN_SEG5, mask_sh),\333 TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_BASE_SEG5, mask_sh),\334 TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C0, mask_sh),\335 TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C1, mask_sh),\336 TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\337 TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\338 TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\339 TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\340 TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\341 TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\342 TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_EN, mask_sh),\343 TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_MODE, mask_sh),\344 TF_SF(DSCL0_ISHARP_MODE, ISHARP_LBA_MODE, mask_sh),\345 TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT, mask_sh),\346 TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_MODE, mask_sh),\347 TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_NORM, mask_sh),\348 TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT_CURRENT, mask_sh),\349 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_IN_SEG0, mask_sh),\350 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_BASE_SEG0, mask_sh),\351 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_SLOPE_SEG0, mask_sh), \352 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_IN_SEG1, mask_sh),\353 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_BASE_SEG1, mask_sh),\354 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_SLOPE_SEG1, mask_sh),\355 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_IN_SEG2, mask_sh),\356 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_BASE_SEG2, mask_sh),\357 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_SLOPE_SEG2, mask_sh),\358 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_IN_SEG3, mask_sh),\359 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_BASE_SEG3, mask_sh),\360 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_SLOPE_SEG3, mask_sh),\361 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_IN_SEG4, mask_sh),\362 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_BASE_SEG4, mask_sh),\363 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_SLOPE_SEG4, mask_sh),\364 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_IN_SEG5, mask_sh),\365 TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_BASE_SEG5, mask_sh),\366 TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_UTHRE, mask_sh),\367 TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_DTHRE, mask_sh), \368 TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_START_IN, mask_sh), \369 TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_END_IN, mask_sh), \370 TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_SLOPE, mask_sh), \371 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_P, mask_sh), \372 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_P, mask_sh), \373 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_P, mask_sh), \374 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_N, mask_sh), \375 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_N, mask_sh), \376 TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_N, mask_sh), \377 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\378 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\379 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\380 TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh)381 382#define DPP_REG_FIELD_LIST_DCN401(type) \383 DPP_REG_FIELD_LIST_DCN3(type); \384 type CUR0_FP_BIAS_G_Y; \385 type CUR0_FP_SCALE_G_Y; \386 type CUR0_FP_BIAS_RB_CRCB; \387 type CUR0_FP_SCALE_RB_CRCB; \388 type CUR0_MATRIX_MODE; \389 type CUR0_MATRIX_MODE_CURRENT; \390 type CUR0_MATRIX_COEF_FORMAT; \391 type CUR0_MATRIX_C11_A; \392 type CUR0_MATRIX_C12_A; \393 type CUR0_MATRIX_C13_A; \394 type CUR0_MATRIX_C14_A; \395 type CUR0_MATRIX_C21_A; \396 type CUR0_MATRIX_C22_A; \397 type CUR0_MATRIX_C23_A; \398 type CUR0_MATRIX_C24_A; \399 type CUR0_MATRIX_C31_A; \400 type CUR0_MATRIX_C32_A; \401 type CUR0_MATRIX_C33_A; \402 type CUR0_MATRIX_C34_A; \403 type LUMA_KEYER_EN; \404 type SCL_SC_MATRIX_MODE; \405 type SCL_SC_LTONL_EN; \406 type SCL_EASF_H_EN; \407 type SCL_EASF_H_RINGEST_FORCE_EN; \408 type SCL_EASF_H_2TAP_SHARP_FACTOR; \409 type SCL_EASF_H_BF1_EN; \410 type SCL_EASF_H_BF2_MODE; \411 type SCL_EASF_H_BF3_MODE; \412 type SCL_EASF_H_BF2_FLAT1_GAIN; \413 type SCL_EASF_H_BF2_FLAT2_GAIN; \414 type SCL_EASF_H_BF2_ROC_GAIN; \415 type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1; \416 type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2; \417 type SCL_EASF_H_RINGEST_EVENTAP_GAIN1; \418 type SCL_EASF_H_RINGEST_EVENTAP_GAIN2; \419 type SCL_EASF_H_BF_MAXA; \420 type SCL_EASF_H_BF_MAXB; \421 type SCL_EASF_H_BF_MINA; \422 type SCL_EASF_H_BF_MINB; \423 type SCL_EASF_H_BF1_PWL_IN_SEG0; \424 type SCL_EASF_H_BF1_PWL_BASE_SEG0; \425 type SCL_EASF_H_BF1_PWL_SLOPE_SEG0; \426 type SCL_EASF_H_BF1_PWL_IN_SEG1; \427 type SCL_EASF_H_BF1_PWL_BASE_SEG1; \428 type SCL_EASF_H_BF1_PWL_SLOPE_SEG1; \429 type SCL_EASF_H_BF1_PWL_IN_SEG2; \430 type SCL_EASF_H_BF1_PWL_BASE_SEG2; \431 type SCL_EASF_H_BF1_PWL_SLOPE_SEG2; \432 type SCL_EASF_H_BF1_PWL_IN_SEG3; \433 type SCL_EASF_H_BF1_PWL_BASE_SEG3; \434 type SCL_EASF_H_BF1_PWL_SLOPE_SEG3; \435 type SCL_EASF_H_BF1_PWL_IN_SEG4; \436 type SCL_EASF_H_BF1_PWL_BASE_SEG4; \437 type SCL_EASF_H_BF1_PWL_SLOPE_SEG4; \438 type SCL_EASF_H_BF1_PWL_IN_SEG5; \439 type SCL_EASF_H_BF1_PWL_BASE_SEG5; \440 type SCL_EASF_H_BF1_PWL_SLOPE_SEG5; \441 type SCL_EASF_H_BF1_PWL_IN_SEG6; \442 type SCL_EASF_H_BF1_PWL_BASE_SEG6; \443 type SCL_EASF_H_BF1_PWL_SLOPE_SEG6; \444 type SCL_EASF_H_BF1_PWL_IN_SEG7; \445 type SCL_EASF_H_BF1_PWL_BASE_SEG7; \446 type SCL_EASF_H_BF3_PWL_IN_SEG0; \447 type SCL_EASF_H_BF3_PWL_BASE_SEG0; \448 type SCL_EASF_H_BF3_PWL_SLOPE_SEG0; \449 type SCL_EASF_H_BF3_PWL_IN_SEG1; \450 type SCL_EASF_H_BF3_PWL_BASE_SEG1; \451 type SCL_EASF_H_BF3_PWL_SLOPE_SEG1; \452 type SCL_EASF_H_BF3_PWL_IN_SEG2; \453 type SCL_EASF_H_BF3_PWL_BASE_SEG2; \454 type SCL_EASF_H_BF3_PWL_SLOPE_SEG2; \455 type SCL_EASF_H_BF3_PWL_IN_SEG3; \456 type SCL_EASF_H_BF3_PWL_BASE_SEG3; \457 type SCL_EASF_H_BF3_PWL_SLOPE_SEG3; \458 type SCL_EASF_H_BF3_PWL_IN_SEG4; \459 type SCL_EASF_H_BF3_PWL_BASE_SEG4; \460 type SCL_EASF_H_BF3_PWL_SLOPE_SEG4; \461 type SCL_EASF_H_BF3_PWL_IN_SEG5; \462 type SCL_EASF_H_BF3_PWL_BASE_SEG5; \463 type SCL_EASF_V_EN; \464 type SCL_EASF_V_RINGEST_FORCE_EN; \465 type SCL_EASF_V_2TAP_SHARP_FACTOR; \466 type SCL_EASF_V_BF1_EN; \467 type SCL_EASF_V_BF2_MODE; \468 type SCL_EASF_V_BF3_MODE; \469 type SCL_EASF_V_BF2_FLAT1_GAIN; \470 type SCL_EASF_V_BF2_FLAT2_GAIN; \471 type SCL_EASF_V_BF2_ROC_GAIN; \472 type SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT; \473 type SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL; \474 type SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE; \475 type SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE; \476 type SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE; \477 type SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET; \478 type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1; \479 type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2; \480 type SCL_EASF_V_RINGEST_EVENTAP_GAIN1; \481 type SCL_EASF_V_RINGEST_EVENTAP_GAIN2; \482 type SCL_EASF_V_BF_MAXA; \483 type SCL_EASF_V_BF_MAXB; \484 type SCL_EASF_V_BF_MINA; \485 type SCL_EASF_V_BF_MINB; \486 type SCL_EASF_V_BF1_PWL_IN_SEG0; \487 type SCL_EASF_V_BF1_PWL_BASE_SEG0; \488 type SCL_EASF_V_BF1_PWL_SLOPE_SEG0; \489 type SCL_EASF_V_BF1_PWL_IN_SEG1; \490 type SCL_EASF_V_BF1_PWL_BASE_SEG1; \491 type SCL_EASF_V_BF1_PWL_SLOPE_SEG1; \492 type SCL_EASF_V_BF1_PWL_IN_SEG2; \493 type SCL_EASF_V_BF1_PWL_BASE_SEG2; \494 type SCL_EASF_V_BF1_PWL_SLOPE_SEG2; \495 type SCL_EASF_V_BF1_PWL_IN_SEG3; \496 type SCL_EASF_V_BF1_PWL_BASE_SEG3; \497 type SCL_EASF_V_BF1_PWL_SLOPE_SEG3; \498 type SCL_EASF_V_BF1_PWL_IN_SEG4; \499 type SCL_EASF_V_BF1_PWL_BASE_SEG4; \500 type SCL_EASF_V_BF1_PWL_SLOPE_SEG4; \501 type SCL_EASF_V_BF1_PWL_IN_SEG5; \502 type SCL_EASF_V_BF1_PWL_BASE_SEG5; \503 type SCL_EASF_V_BF1_PWL_SLOPE_SEG5; \504 type SCL_EASF_V_BF1_PWL_IN_SEG6; \505 type SCL_EASF_V_BF1_PWL_BASE_SEG6; \506 type SCL_EASF_V_BF1_PWL_SLOPE_SEG6; \507 type SCL_EASF_V_BF1_PWL_IN_SEG7; \508 type SCL_EASF_V_BF1_PWL_BASE_SEG7; \509 type SCL_EASF_V_BF3_PWL_IN_SEG0; \510 type SCL_EASF_V_BF3_PWL_BASE_SEG0; \511 type SCL_EASF_V_BF3_PWL_SLOPE_SEG0; \512 type SCL_EASF_V_BF3_PWL_IN_SEG1; \513 type SCL_EASF_V_BF3_PWL_BASE_SEG1; \514 type SCL_EASF_V_BF3_PWL_SLOPE_SEG1; \515 type SCL_EASF_V_BF3_PWL_IN_SEG2; \516 type SCL_EASF_V_BF3_PWL_BASE_SEG2; \517 type SCL_EASF_V_BF3_PWL_SLOPE_SEG2; \518 type SCL_EASF_V_BF3_PWL_IN_SEG3; \519 type SCL_EASF_V_BF3_PWL_BASE_SEG3; \520 type SCL_EASF_V_BF3_PWL_SLOPE_SEG3; \521 type SCL_EASF_V_BF3_PWL_IN_SEG4; \522 type SCL_EASF_V_BF3_PWL_BASE_SEG4; \523 type SCL_EASF_V_BF3_PWL_SLOPE_SEG4; \524 type SCL_EASF_V_BF3_PWL_IN_SEG5; \525 type SCL_EASF_V_BF3_PWL_BASE_SEG5; \526 type SCL_SC_MATRIX_C0; \527 type SCL_SC_MATRIX_C1; \528 type SCL_SC_MATRIX_C2; \529 type SCL_SC_MATRIX_C3; \530 type ISHARP_EN; \531 type ISHARP_NOISEDET_EN; \532 type ISHARP_NOISEDET_MODE; \533 type ISHARP_NOISEDET_UTHRE; \534 type ISHARP_NOISEDET_DTHRE; \535 type ISHARP_NOISEDET_PWL_START_IN; \536 type ISHARP_NOISEDET_PWL_END_IN; \537 type ISHARP_NOISEDET_PWL_SLOPE; \538 type ISHARP_LBA_MODE; \539 type ISHARP_LBA_PWL_IN_SEG0; \540 type ISHARP_LBA_PWL_BASE_SEG0; \541 type ISHARP_LBA_PWL_SLOPE_SEG0; \542 type ISHARP_LBA_PWL_IN_SEG1; \543 type ISHARP_LBA_PWL_BASE_SEG1; \544 type ISHARP_LBA_PWL_SLOPE_SEG1; \545 type ISHARP_LBA_PWL_IN_SEG2; \546 type ISHARP_LBA_PWL_BASE_SEG2; \547 type ISHARP_LBA_PWL_SLOPE_SEG2; \548 type ISHARP_LBA_PWL_IN_SEG3; \549 type ISHARP_LBA_PWL_BASE_SEG3; \550 type ISHARP_LBA_PWL_SLOPE_SEG3; \551 type ISHARP_LBA_PWL_IN_SEG4; \552 type ISHARP_LBA_PWL_BASE_SEG4; \553 type ISHARP_LBA_PWL_SLOPE_SEG4; \554 type ISHARP_LBA_PWL_IN_SEG5; \555 type ISHARP_LBA_PWL_BASE_SEG5; \556 type ISHARP_FMT_MODE; \557 type ISHARP_FMT_NORM; \558 type ISHARP_DELTA_LUT_SELECT; \559 type ISHARP_DELTA_LUT_SELECT_CURRENT; \560 type ISHARP_DELTA_LUT_HOST_SELECT; \561 type ISHARP_DELTA_DATA; \562 type ISHARP_DELTA_INDEX; \563 type ISHARP_NLDELTA_SCLIP_EN_P; \564 type ISHARP_NLDELTA_SCLIP_PIVOT_P; \565 type ISHARP_NLDELTA_SCLIP_SLOPE_P; \566 type ISHARP_NLDELTA_SCLIP_EN_N; \567 type ISHARP_NLDELTA_SCLIP_PIVOT_N; \568 type ISHARP_NLDELTA_SCLIP_SLOPE_N569 570struct dcn401_dpp_registers {571 DPP_DCN3_REG_VARIABLE_LIST_COMMON;572 uint32_t CURSOR0_FP_SCALE_BIAS_G_Y;573 uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB;574 uint32_t CUR0_MATRIX_MODE;575 uint32_t CUR0_MATRIX_C11_C12_A;576 uint32_t CUR0_MATRIX_C13_C14_A;577 uint32_t CUR0_MATRIX_C21_C22_A;578 uint32_t CUR0_MATRIX_C23_C24_A;579 uint32_t CUR0_MATRIX_C31_C32_A;580 uint32_t CUR0_MATRIX_C33_C34_A;581 uint32_t CUR0_MATRIX_C11_C12_B;582 uint32_t CUR0_MATRIX_C13_C14_B;583 uint32_t CUR0_MATRIX_C21_C22_B;584 uint32_t CUR0_MATRIX_C23_C24_B;585 uint32_t CUR0_MATRIX_C31_C32_B;586 uint32_t CUR0_MATRIX_C33_C34_B;587 uint32_t DSCL_SC_MODE;588 uint32_t DSCL_EASF_H_MODE;589 uint32_t DSCL_EASF_H_BF_CNTL;590 uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE;591 uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN;592 uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN;593 uint32_t DSCL_EASF_H_BF1_PWL_SEG0;594 uint32_t DSCL_EASF_H_BF1_PWL_SEG1;595 uint32_t DSCL_EASF_H_BF1_PWL_SEG2;596 uint32_t DSCL_EASF_H_BF1_PWL_SEG3;597 uint32_t DSCL_EASF_H_BF1_PWL_SEG4;598 uint32_t DSCL_EASF_H_BF1_PWL_SEG5;599 uint32_t DSCL_EASF_H_BF1_PWL_SEG6;600 uint32_t DSCL_EASF_H_BF1_PWL_SEG7;601 uint32_t DSCL_EASF_H_BF3_PWL_SEG0;602 uint32_t DSCL_EASF_H_BF3_PWL_SEG1;603 uint32_t DSCL_EASF_H_BF3_PWL_SEG2;604 uint32_t DSCL_EASF_H_BF3_PWL_SEG3;605 uint32_t DSCL_EASF_H_BF3_PWL_SEG4;606 uint32_t DSCL_EASF_H_BF3_PWL_SEG5;607 uint32_t DSCL_EASF_V_MODE;608 uint32_t DSCL_EASF_V_BF_CNTL;609 uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1;610 uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2;611 uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3;612 uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE;613 uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN;614 uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN;615 uint32_t DSCL_EASF_V_BF1_PWL_SEG0;616 uint32_t DSCL_EASF_V_BF1_PWL_SEG1;617 uint32_t DSCL_EASF_V_BF1_PWL_SEG2;618 uint32_t DSCL_EASF_V_BF1_PWL_SEG3;619 uint32_t DSCL_EASF_V_BF1_PWL_SEG4;620 uint32_t DSCL_EASF_V_BF1_PWL_SEG5;621 uint32_t DSCL_EASF_V_BF1_PWL_SEG6;622 uint32_t DSCL_EASF_V_BF1_PWL_SEG7;623 uint32_t DSCL_EASF_V_BF3_PWL_SEG0;624 uint32_t DSCL_EASF_V_BF3_PWL_SEG1;625 uint32_t DSCL_EASF_V_BF3_PWL_SEG2;626 uint32_t DSCL_EASF_V_BF3_PWL_SEG3;627 uint32_t DSCL_EASF_V_BF3_PWL_SEG4;628 uint32_t DSCL_EASF_V_BF3_PWL_SEG5;629 uint32_t DSCL_SC_MATRIX_C0C1;630 uint32_t DSCL_SC_MATRIX_C2C3;631 uint32_t ISHARP_MODE;632 uint32_t ISHARP_NOISEDET_THRESHOLD;633 uint32_t ISHARP_NOISE_GAIN_PWL;634 uint32_t ISHARP_LBA_PWL_SEG0;635 uint32_t ISHARP_LBA_PWL_SEG1;636 uint32_t ISHARP_LBA_PWL_SEG2;637 uint32_t ISHARP_LBA_PWL_SEG3;638 uint32_t ISHARP_LBA_PWL_SEG4;639 uint32_t ISHARP_LBA_PWL_SEG5;640 uint32_t ISHARP_DELTA_CTRL;641 uint32_t ISHARP_DELTA_DATA;642 uint32_t ISHARP_DELTA_INDEX;643 uint32_t ISHARP_NLDELTA_SOFT_CLIP;644};645 646struct dcn401_dpp_shift {647 DPP_REG_FIELD_LIST_DCN401(uint8_t);648};649 650struct dcn401_dpp_mask {651 DPP_REG_FIELD_LIST_DCN401(uint32_t);652};653 654struct dcn401_dpp {655 struct dpp base;656 657 const struct dcn401_dpp_registers *tf_regs;658 const struct dcn401_dpp_shift *tf_shift;659 const struct dcn401_dpp_mask *tf_mask;660 661 const uint16_t *filter_v;662 const uint16_t *filter_h;663 const uint16_t *filter_v_c;664 const uint16_t *filter_h_c;665 int lb_pixel_depth_supported;666 int lb_memory_size;667 int lb_bits_per_entry;668 bool is_write_to_ram_a_safe;669 struct scaler_data scl_data;670 struct pwl_params pwl_data;671};672 673bool dpp401_construct(struct dcn401_dpp *dpp401,674 struct dc_context *ctx,675 uint32_t inst,676 const struct dcn401_dpp_registers *tf_regs,677 const struct dcn401_dpp_shift *tf_shift,678 const struct dcn401_dpp_mask *tf_mask);679 680void dpp401_dscl_set_scaler_manual_scale(681 struct dpp *dpp_base,682 const struct scaler_data *scl_data);683 684void dpp401_full_bypass(struct dpp *dpp_base);685 686void dpp401_dpp_setup(687 struct dpp *dpp_base,688 enum surface_pixel_format format,689 enum expansion_mode mode,690 struct dc_csc_transform input_csc_color_matrix,691 enum dc_color_space input_color_space,692 struct cnv_alpha_2bit_lut *alpha_2bit_lut);693 694void dpp401_set_cursor_attributes(695 struct dpp *dpp_base,696 struct dc_cursor_attributes *cursor_attributes);697 698void dpp401_set_cursor_position(699 struct dpp *dpp_base,700 const struct dc_cursor_position *pos,701 const struct dc_cursor_mi_param *param,702 uint32_t width,703 uint32_t height);704 705void dpp401_set_optional_cursor_attributes(706 struct dpp *dpp_base,707 struct dpp_cursor_attributes *attr);708 709void dscl401_calc_lb_num_partitions(710 const struct scaler_data *scl_data,711 enum lb_memory_config lb_config,712 int *num_part_y,713 int *num_part_c);714 715void dscl401_spl_calc_lb_num_partitions(716 bool alpha_en,717 const struct spl_scaler_data *scl_data,718 enum lb_memory_config lb_config,719 int *num_part_y,720 int *num_part_c);721 722void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);723 724void dpp401_set_cursor_matrix(725 struct dpp *dpp_base,726 enum dc_color_space color_space,727 struct dc_csc_transform cursor_csc_color_matrix);728 729#endif /* __DCN401_DPP_H__ */730