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1/*2 * Copyright 2017 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include <drm/display/drm_dsc_helper.h>27 28#include "reg_helper.h"29#include "dcn20_dsc.h"30#include "dsc/dscc_types.h"31#include "dsc/rc_calc.h"32 33static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);34 35static const struct dsc_funcs dcn20_dsc_funcs = {36 .dsc_get_enc_caps = dsc2_get_enc_caps,37 .dsc_read_state = dsc2_read_state,38 .dsc_validate_stream = dsc2_validate_stream,39 .dsc_set_config = dsc2_set_config,40 .dsc_get_packed_pps = dsc2_get_packed_pps,41 .dsc_enable = dsc2_enable,42 .dsc_disable = dsc2_disable,43 .dsc_disconnect = dsc2_disconnect,44 .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,45};46 47/* Macro definitios for REG_SET macros*/48#define CTX \49 dsc20->base.ctx50 51#define REG(reg)\52 dsc20->dsc_regs->reg53 54#undef FN55#define FN(reg_name, field_name) \56 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name57#define DC_LOGGER \58 dsc->ctx->logger59 60enum dsc_bits_per_comp {61 DSC_BPC_8 = 8,62 DSC_BPC_10 = 10,63 DSC_BPC_12 = 12,64 DSC_BPC_UNKNOWN65};66 67/* API functions (external or via structure->function_pointer) */68 69void dsc2_construct(struct dcn20_dsc *dsc,70 struct dc_context *ctx,71 int inst,72 const struct dcn20_dsc_registers *dsc_regs,73 const struct dcn20_dsc_shift *dsc_shift,74 const struct dcn20_dsc_mask *dsc_mask)75{76 dsc->base.ctx = ctx;77 dsc->base.inst = inst;78 dsc->base.funcs = &dcn20_dsc_funcs;79 80 dsc->dsc_regs = dsc_regs;81 dsc->dsc_shift = dsc_shift;82 dsc->dsc_mask = dsc_mask;83 84 dsc->max_image_width = 5184;85}86 87 88#define DCN20_MAX_PIXEL_CLOCK_Mhz 118889#define DCN20_MAX_DISPLAY_CLOCK_Mhz 120090 91/* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput92 * can be doubled, tripled etc. by using additional DSC engines.93 */94void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)95{96 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */97 98 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;99 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;100 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;101 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;102 103 dsc_enc_caps->lb_bit_depth = 13;104 dsc_enc_caps->is_block_pred_supported = true;105 106 dsc_enc_caps->color_formats.bits.RGB = 1;107 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;108 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;109 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;110 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;111 112 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;113 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;114 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;115 116 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.117 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.118 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always119 * be sufficient to process the input pixel rate fed into a single DSC engine.120 */121 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;122 123 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our124 * throughput and number of slices, but also introduces a lower limit of 2 slices125 */126 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {127 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;128 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;129 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;130 }131 132 /* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our133 * throughput and number of slices134 */135 if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) {136 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;137 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;138 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;139 }140 141 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */142 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */143}144 145 146/* this function read dsc related register fields to be logged later in dcn10_log_hw_state147 * into a dcn_dsc_state struct.148 */149void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)150{151 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);152 153 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);154 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);155 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);156 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);157 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);158 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);159 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);160 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);161 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,162 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);163}164 165 166bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)167{168 struct dsc_optc_config dsc_optc_cfg;169 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);170 171 if (dsc_cfg->pic_width > dsc20->max_image_width)172 return false;173 174 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);175}176 177 178void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)179{180 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);181 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);182 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",183 config->dc_dsc_cfg.bits_per_pixel,184 config->dc_dsc_cfg.bits_per_pixel / 16,185 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);186 DC_LOG_DSC("\tcolor_depth %d", config->color_depth);187}188 189void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,190 struct dsc_optc_config *dsc_optc_cfg)191{192 bool is_config_ok;193 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);194 195 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);196 dsc_config_log(dsc, dsc_cfg);197 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);198 ASSERT(is_config_ok);199 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");200 dsc_log_pps(dsc, &dsc20->reg_vals.pps);201 dsc_write_to_registers(dsc, &dsc20->reg_vals);202}203 204 205bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)206{207 bool is_config_ok;208 struct dsc_reg_values dsc_reg_vals;209 struct dsc_optc_config dsc_optc_cfg;210 211 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));212 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));213 214 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");215 dsc_config_log(dsc, dsc_cfg);216 DC_LOG_DSC("DSC Picture Parameter Set (PPS):");217 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);218 ASSERT(is_config_ok);219 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);220 dsc_log_pps(dsc, &dsc_reg_vals.pps);221 222 return is_config_ok;223}224 225 226void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)227{228 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);229 int dsc_clock_en;230 int dsc_fw_config;231 int enabled_opp_pipe;232 233 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);234 235 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);236 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);237 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {238 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);239 ASSERT(0);240 }241 242 REG_UPDATE(DSC_TOP_CONTROL,243 DSC_CLOCK_EN, 1);244 245 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,246 DSCRM_DSC_FORWARD_EN, 1,247 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);248}249 250 251void dsc2_disable(struct display_stream_compressor *dsc)252{253 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);254 int dsc_clock_en;255 256 DC_LOG_DSC("disable DSC %d", dsc->inst);257 258 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);259 if (!dsc_clock_en) {260 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);261 }262 263 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,264 DSCRM_DSC_FORWARD_EN, 0);265 266 REG_UPDATE(DSC_TOP_CONTROL,267 DSC_CLOCK_EN, 0);268}269 270void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)271{272 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);273 274 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);275}276 277void dsc2_disconnect(struct display_stream_compressor *dsc)278{279 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);280 281 DC_LOG_DSC("disconnect DSC %d", dsc->inst);282 283 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,284 DSCRM_DSC_FORWARD_EN, 0);285}286 287/* This module's internal functions */288void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)289{290 int i;291 int bits_per_pixel = pps->bits_per_pixel;292 293 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);294 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);295 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);296 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);297 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);298 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);299 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);300 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);301 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);302 DC_LOG_DSC("\tpic_height %d", pps->pic_height);303 DC_LOG_DSC("\tpic_width %d", pps->pic_width);304 DC_LOG_DSC("\tslice_height %d", pps->slice_height);305 DC_LOG_DSC("\tslice_width %d", pps->slice_width);306 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);307 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);308 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);309 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);310 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);311 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);312 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);313 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);314 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);315 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);316 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);317 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);318 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);319 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */320 DC_LOG_DSC("\tnative_420 %d", pps->native_420);321 DC_LOG_DSC("\tnative_422 %d", pps->native_422);322 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);323 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);324 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);325 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);326 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);327 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);328 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);329 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);330 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);331 332 for (i = 0; i < NUM_BUF_RANGES - 1; i++)333 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);334 335 for (i = 0; i < NUM_BUF_RANGES; i++) {336 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);337 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);338 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);339 }340}341 342void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override)343{344 uint8_t i;345 346 rc->rc_model_size = override->rc_model_size;347 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++)348 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i];349 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) {350 rc->qp_min[i] = override->rc_minqp[i];351 rc->qp_max[i] = override->rc_maxqp[i];352 rc->ofs[i] = override->rc_offset[i];353 }354 355 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi;356 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo;357 rc->rc_edge_factor = override->rc_edge_factor;358 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0;359 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1;360 361 rc->initial_fullness_offset = override->initial_fullness_offset;362 rc->initial_xmit_delay = override->initial_delay;363 364 rc->flatness_min_qp = override->flatness_min_qp;365 rc->flatness_max_qp = override->flatness_max_qp;366 rc->flatness_det_thresh = override->flatness_det_thresh;367}368 369bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,370 struct dsc_optc_config *dsc_optc_cfg)371{372 struct dsc_parameters dsc_params;373 struct rc_params rc;374 375 /* Validate input parameters */376 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);377 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);378 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);379 ASSERT(dsc_cfg->pic_width);380 ASSERT(dsc_cfg->pic_height);381 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&382 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||383 (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&384 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||385 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));386 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375387 388 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||389 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||390 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||391 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:392 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||393 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:394 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||395 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||396 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {397 dm_output_to_console("%s: Invalid parameters\n", __func__);398 return false;399 }400 401 dsc_init_reg_values(dsc_reg_vals);402 403 /* Copy input config */404 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);405 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;406 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;407 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;408 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;409 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;410 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);411 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;412 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;413 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;414 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;415 416 // TODO: in addition to validating slice height (pic height must be divisible by slice height),417 // see what happens when the same condition doesn't apply for slice_width/pic_width.418 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;419 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;420 421 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);422 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {423 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);424 return false;425 }426 427 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;428 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)429 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;430 else431 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;432 433 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;434 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);435 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);436 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);437 438 calc_rc_params(&rc, &dsc_reg_vals->pps);439 440 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd)441 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd);442 443 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {444 dm_output_to_console("%s: DSC config failed\n", __func__);445 return false;446 }447 448 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);449 450 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;451 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;452 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||453 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||454 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;455 456 return true;457}458 459 460enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)461{462 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;463 464 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */465 466 switch (dc_pix_enc) {467 case PIXEL_ENCODING_RGB:468 dsc_pix_fmt = DSC_PIXFMT_RGB;469 break;470 case PIXEL_ENCODING_YCBCR422:471 if (is_ycbcr422_simple)472 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;473 else474 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;475 break;476 case PIXEL_ENCODING_YCBCR444:477 dsc_pix_fmt = DSC_PIXFMT_YCBCR444;478 break;479 case PIXEL_ENCODING_YCBCR420:480 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;481 break;482 default:483 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;484 break;485 }486 487 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);488 return dsc_pix_fmt;489}490 491 492enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)493{494 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;495 496 switch (dc_color_depth) {497 case COLOR_DEPTH_888:498 bpc = DSC_BPC_8;499 break;500 case COLOR_DEPTH_101010:501 bpc = DSC_BPC_10;502 break;503 case COLOR_DEPTH_121212:504 bpc = DSC_BPC_12;505 break;506 default:507 bpc = DSC_BPC_UNKNOWN;508 break;509 }510 511 return bpc;512}513 514 515void dsc_init_reg_values(struct dsc_reg_values *reg_vals)516{517 int i;518 519 memset(reg_vals, 0, sizeof(struct dsc_reg_values));520 521 /* Non-PPS values */522 reg_vals->dsc_clock_enable = 1;523 reg_vals->dsc_clock_gating_disable = 0;524 reg_vals->underflow_recovery_en = 0;525 reg_vals->underflow_occurred_int_en = 0;526 reg_vals->underflow_occurred_status = 0;527 reg_vals->ich_reset_at_eol = 0;528 reg_vals->alternate_ich_encoding_en = 0;529 reg_vals->rc_buffer_model_size = 0;530 /*reg_vals->disable_ich = 0;*/531 reg_vals->dsc_dbg_en = 0;532 533 for (i = 0; i < 4; i++)534 reg_vals->rc_buffer_model_overflow_int_en[i] = 0;535 536 /* PPS values */537 reg_vals->pps.dsc_version_minor = 2;538 reg_vals->pps.dsc_version_major = 1;539 reg_vals->pps.line_buf_depth = 9;540 reg_vals->pps.bits_per_component = 8;541 reg_vals->pps.block_pred_enable = 1;542 reg_vals->pps.slice_chunk_size = 0;543 reg_vals->pps.pic_width = 0;544 reg_vals->pps.pic_height = 0;545 reg_vals->pps.slice_width = 0;546 reg_vals->pps.slice_height = 0;547 reg_vals->pps.initial_xmit_delay = 170;548 reg_vals->pps.initial_dec_delay = 0;549 reg_vals->pps.initial_scale_value = 0;550 reg_vals->pps.scale_increment_interval = 0;551 reg_vals->pps.scale_decrement_interval = 0;552 reg_vals->pps.nfl_bpg_offset = 0;553 reg_vals->pps.slice_bpg_offset = 0;554 reg_vals->pps.nsl_bpg_offset = 0;555 reg_vals->pps.initial_offset = 6144;556 reg_vals->pps.final_offset = 0;557 reg_vals->pps.flatness_min_qp = 3;558 reg_vals->pps.flatness_max_qp = 12;559 reg_vals->pps.rc_model_size = 8192;560 reg_vals->pps.rc_edge_factor = 6;561 reg_vals->pps.rc_quant_incr_limit0 = 11;562 reg_vals->pps.rc_quant_incr_limit1 = 11;563 reg_vals->pps.rc_tgt_offset_low = 3;564 reg_vals->pps.rc_tgt_offset_high = 3;565}566 567/* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.568 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn569 * affects non-PPS register values.570 */571void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)572{573 int i;574 575 reg_vals->pps = dsc_params->pps;576 577 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.578 for (i = 0; i < NUM_BUF_RANGES - 1; i++)579 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;580 581 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;582}583 584static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)585{586 uint32_t temp_int;587 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);588 589 REG_SET(DSC_DEBUG_CONTROL, 0,590 DSC_DBG_EN, reg_vals->dsc_dbg_en);591 592 // dsccif registers593 REG_SET_5(DSCCIF_CONFIG0, 0,594 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,595 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,596 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,597 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,598 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);599 600 REG_SET_2(DSCCIF_CONFIG1, 0,601 PIC_WIDTH, reg_vals->pps.pic_width,602 PIC_HEIGHT, reg_vals->pps.pic_height);603 604 // dscc registers605 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {606 REG_SET_3(DSCC_CONFIG0, 0,607 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,608 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,609 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);610 } else {611 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,612 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,613 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,614 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,615 reg_vals->num_slices_v - 1);616 }617 618 REG_SET(DSCC_CONFIG1, 0,619 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);620 /*REG_SET_2(DSCC_CONFIG1, 0,621 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,622 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/623 624 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,625 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],626 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],627 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],628 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);629 630 REG_SET_3(DSCC_PPS_CONFIG0, 0,631 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,632 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,633 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);634 635 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)636 temp_int = reg_vals->bpp_x32;637 else638 temp_int = reg_vals->bpp_x32 >> 1;639 640 REG_SET_7(DSCC_PPS_CONFIG1, 0,641 BITS_PER_PIXEL, temp_int,642 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,643 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,644 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,645 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,646 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,647 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);648 649 REG_SET_2(DSCC_PPS_CONFIG2, 0,650 PIC_WIDTH, reg_vals->pps.pic_width,651 PIC_HEIGHT, reg_vals->pps.pic_height);652 653 REG_SET_2(DSCC_PPS_CONFIG3, 0,654 SLICE_WIDTH, reg_vals->pps.slice_width,655 SLICE_HEIGHT, reg_vals->pps.slice_height);656 657 REG_SET(DSCC_PPS_CONFIG4, 0,658 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);659 660 REG_SET_2(DSCC_PPS_CONFIG5, 0,661 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,662 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);663 664 REG_SET_3(DSCC_PPS_CONFIG6, 0,665 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,666 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,667 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);668 669 REG_SET_2(DSCC_PPS_CONFIG7, 0,670 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,671 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);672 673 REG_SET_2(DSCC_PPS_CONFIG8, 0,674 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,675 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);676 677 REG_SET_2(DSCC_PPS_CONFIG9, 0,678 INITIAL_OFFSET, reg_vals->pps.initial_offset,679 FINAL_OFFSET, reg_vals->pps.final_offset);680 681 REG_SET_3(DSCC_PPS_CONFIG10, 0,682 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,683 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,684 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);685 686 REG_SET_5(DSCC_PPS_CONFIG11, 0,687 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,688 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,689 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,690 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,691 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);692 693 REG_SET_4(DSCC_PPS_CONFIG12, 0,694 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],695 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],696 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],697 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);698 699 REG_SET_4(DSCC_PPS_CONFIG13, 0,700 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],701 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],702 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],703 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);704 705 REG_SET_4(DSCC_PPS_CONFIG14, 0,706 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],707 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],708 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],709 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);710 711 REG_SET_5(DSCC_PPS_CONFIG15, 0,712 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],713 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],714 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,715 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,716 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);717 718 REG_SET_6(DSCC_PPS_CONFIG16, 0,719 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,720 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,721 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,722 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,723 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,724 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);725 726 REG_SET_6(DSCC_PPS_CONFIG17, 0,727 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,728 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,729 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,730 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,731 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,732 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);733 734 REG_SET_6(DSCC_PPS_CONFIG18, 0,735 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,736 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,737 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,738 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,739 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,740 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);741 742 REG_SET_6(DSCC_PPS_CONFIG19, 0,743 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,744 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,745 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,746 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,747 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,748 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);749 750 REG_SET_6(DSCC_PPS_CONFIG20, 0,751 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,752 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,753 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,754 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,755 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,756 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);757 758 REG_SET_6(DSCC_PPS_CONFIG21, 0,759 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,760 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,761 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,762 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,763 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,764 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);765 766 REG_SET_6(DSCC_PPS_CONFIG22, 0,767 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,768 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,769 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,770 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,771 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,772 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);773 774}775