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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dcn35_dsc.h"28#include "reg_helper.h"29 30static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);31 32static const struct dsc_funcs dcn35_dsc_funcs = {33 .dsc_get_enc_caps = dsc2_get_enc_caps,34 .dsc_read_state = dsc2_read_state,35 .dsc_validate_stream = dsc2_validate_stream,36 .dsc_set_config = dsc2_set_config,37 .dsc_get_packed_pps = dsc2_get_packed_pps,38 .dsc_enable = dsc35_enable,39 .dsc_disable = dsc2_disable,40 .dsc_disconnect = dsc2_disconnect,41 .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,42};43 44/* Macro definitios for REG_SET macros*/45#define CTX \46 dsc20->base.ctx47 48#define REG(reg)\49 dsc20->dsc_regs->reg50 51#undef FN52#define FN(reg_name, field_name) \53 ((const struct dcn35_dsc_shift *)(dsc20->dsc_shift))->field_name, \54 ((const struct dcn35_dsc_mask *)(dsc20->dsc_mask))->field_name55 56#define DC_LOGGER \57 dsc->ctx->logger58 59void dsc35_construct(struct dcn20_dsc *dsc,60 struct dc_context *ctx,61 int inst,62 const struct dcn20_dsc_registers *dsc_regs,63 const struct dcn35_dsc_shift *dsc_shift,64 const struct dcn35_dsc_mask *dsc_mask)65{66 dsc->base.ctx = ctx;67 dsc->base.inst = inst;68 dsc->base.funcs = &dcn35_dsc_funcs;69 70 dsc->dsc_regs = dsc_regs;71 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);72 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);73 74 dsc->max_image_width = 5184;75}76 77static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)78{79 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);80 int dsc_clock_en;81 int dsc_fw_config;82 int enabled_opp_pipe;83 84 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);85 86 // TODO: After an idle exit, the HW default values for power control87 // are changed intermittently due to unknown reasons. There are cases88 // when dscc memory are still in shutdown state during enablement.89 // Reset power control to hw default values.90 REG_UPDATE_2(DSCC_MEM_POWER_CONTROL,91 DSCC_MEM_PWR_FORCE, 0,92 DSCC_MEM_PWR_DIS, 0);93 94 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);95 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);96 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {97 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);98 ASSERT(0);99 }100 101 REG_UPDATE(DSC_TOP_CONTROL,102 DSC_CLOCK_EN, 1);103 104 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,105 DSCRM_DSC_FORWARD_EN, 1,106 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);107}108 109void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)110{111 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);112}113