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1// SPDX-License-Identifier: MIT2//3// Copyright 2024 Advanced Micro Devices, Inc.4 5#include <drm/display/drm_dsc_helper.h>6 7#include "reg_helper.h"8#include "dcn401_dsc.h"9#include "dsc/dscc_types.h"10#include "dsc/rc_calc.h"11 12#define MAX_THROUGHPUT_PER_DSC_100HZ 2000000013#define MAX_DSC_UNIT_COMBINE 414 15static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);16 17/* Object I/F functions */18//static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);19static void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);20static bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);21static void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,22 struct dsc_optc_config *dsc_optc_cfg);23//static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);24static void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);25static void dsc401_disable(struct display_stream_compressor *dsc);26static void dsc401_disconnect(struct display_stream_compressor *dsc);27static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);28static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);29 30static const struct dsc_funcs dcn401_dsc_funcs = {31 .dsc_get_enc_caps = dsc401_get_enc_caps,32 .dsc_read_state = dsc401_read_state,33 .dsc_validate_stream = dsc401_validate_stream,34 .dsc_set_config = dsc401_set_config,35 .dsc_get_packed_pps = dsc2_get_packed_pps,36 .dsc_enable = dsc401_enable,37 .dsc_disable = dsc401_disable,38 .dsc_disconnect = dsc401_disconnect,39 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,40};41 42/* Macro definitios for REG_SET macros*/43#define CTX \44 dsc401->base.ctx45 46#define REG(reg)\47 dsc401->dsc_regs->reg48 49#undef FN50#define FN(reg_name, field_name) \51 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name52#define DC_LOGGER \53 dsc->ctx->logger54 55enum dsc_bits_per_comp {56 DSC_BPC_8 = 8,57 DSC_BPC_10 = 10,58 DSC_BPC_12 = 12,59 DSC_BPC_UNKNOWN60};61 62/* API functions (external or via structure->function_pointer) */63 64void dsc401_construct(struct dcn401_dsc *dsc,65 struct dc_context *ctx,66 int inst,67 const struct dcn401_dsc_registers *dsc_regs,68 const struct dcn401_dsc_shift *dsc_shift,69 const struct dcn401_dsc_mask *dsc_mask)70{71 dsc->base.ctx = ctx;72 dsc->base.inst = inst;73 dsc->base.funcs = &dcn401_dsc_funcs;74 75 dsc->dsc_regs = dsc_regs;76 dsc->dsc_shift = dsc_shift;77 dsc->dsc_mask = dsc_mask;78 79 dsc->max_image_width = 5184;80}81 82static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)83{84 int min_dsc_unit_required = (pixel_clock_100Hz + MAX_THROUGHPUT_PER_DSC_100HZ - 1) / MAX_THROUGHPUT_PER_DSC_100HZ;85 86 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */87 88 /* 1 slice is only supported with 1 DSC unit */89 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = min_dsc_unit_required == 1 ? 1 : 0;90 /* 2 slice is only supported with 1 or 2 DSC units */91 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = (min_dsc_unit_required == 1 || min_dsc_unit_required == 2) ? 1 : 0;92 /* 3 slice is only supported with 1 DSC unit */93 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = min_dsc_unit_required == 1 ? 1 : 0;94 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;95 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;96 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;97 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;98 99 dsc_enc_caps->lb_bit_depth = 13;100 dsc_enc_caps->is_block_pred_supported = true;101 102 dsc_enc_caps->color_formats.bits.RGB = 1;103 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;104 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;105 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;106 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;107 108 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;109 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;110 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;111 dsc_enc_caps->max_total_throughput_mps = MAX_THROUGHPUT_PER_DSC_100HZ * MAX_DSC_UNIT_COMBINE;112 113 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */114 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */115}116 117/* this function read dsc related register fields to be logged later in dcn10_log_hw_state118 * into a dcn_dsc_state struct.119 */120static void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)121{122 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);123 124 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);125 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);126 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);127 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);128 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);129 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);130 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);131 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);132 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,133 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);134}135 136 137static bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)138{139 struct dsc_optc_config dsc_optc_cfg;140 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);141 142 if (dsc_cfg->pic_width > dsc401->max_image_width)143 return false;144 145 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg);146}147 148static void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,149 struct dsc_optc_config *dsc_optc_cfg)150{151 bool is_config_ok;152 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);153 154 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);155 dsc_config_log(dsc, dsc_cfg);156 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg);157 ASSERT(is_config_ok);158 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");159 dsc_log_pps(dsc, &dsc401->reg_vals.pps);160 dsc_write_to_registers(dsc, &dsc401->reg_vals);161}162 163static void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)164{165 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);166 int dsc_clock_en;167 int dsc_fw_config;168 int enabled_opp_pipe;169 170 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);171 172 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);173 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);174 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {175 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);176 ASSERT(0);177 }178 179 REG_UPDATE(DSC_TOP_CONTROL,180 DSC_CLOCK_EN, 1);181 182 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,183 DSCRM_DSC_FORWARD_EN, 1,184 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);185}186 187 188static void dsc401_disable(struct display_stream_compressor *dsc)189{190 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);191 int dsc_clock_en;192 193 DC_LOG_DSC("disable DSC %d", dsc->inst);194 195 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);196 if (!dsc_clock_en) {197 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);198 }199 200 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,201 DSCRM_DSC_FORWARD_EN, 0);202 203 REG_UPDATE(DSC_TOP_CONTROL,204 DSC_CLOCK_EN, 0);205}206 207static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)208{209 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);210 211 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);212}213 214static void dsc401_disconnect(struct display_stream_compressor *dsc)215{216 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);217 218 DC_LOG_DSC("disconnect DSC %d", dsc->inst);219 220 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,221 DSCRM_DSC_FORWARD_EN, 0);222}223 224static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)225{226 uint32_t temp_int;227 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);228 229 REG_SET(DSC_DEBUG_CONTROL, 0,230 DSC_DBG_EN, reg_vals->dsc_dbg_en);231 232 // dsccif registers233 REG_SET_2(DSCCIF_CONFIG0, 0,234 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,235 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,236 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,237 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,238 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);239 240 /* REG_SET_2(DSCCIF_CONFIG1, 0,241 PIC_WIDTH, reg_vals->pps.pic_width,242 PIC_HEIGHT, reg_vals->pps.pic_height);243 */244 // dscc registers245 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {246 REG_SET_3(DSCC_CONFIG0, 0,247 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,248 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,249 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);250 } else {251 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,252 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,253 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,254 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,255 reg_vals->num_slices_v - 1);256 }257 258 REG_SET(DSCC_CONFIG1, 0,259 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);260 /*REG_SET_2(DSCC_CONFIG1, 0,261 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,262 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/263 264 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,265 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0],266 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1],267 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2],268 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]);269 270 REG_SET_3(DSCC_PPS_CONFIG0, 0,271 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,272 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,273 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);274 275 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)276 temp_int = reg_vals->bpp_x32;277 else278 temp_int = reg_vals->bpp_x32 >> 1;279 280 REG_SET_7(DSCC_PPS_CONFIG1, 0,281 BITS_PER_PIXEL, temp_int,282 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,283 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,284 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,285 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,286 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,287 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);288 289 REG_SET_2(DSCC_PPS_CONFIG2, 0,290 PIC_WIDTH, reg_vals->pps.pic_width,291 PIC_HEIGHT, reg_vals->pps.pic_height);292 293 REG_SET_2(DSCC_PPS_CONFIG3, 0,294 SLICE_WIDTH, reg_vals->pps.slice_width,295 SLICE_HEIGHT, reg_vals->pps.slice_height);296 297 REG_SET(DSCC_PPS_CONFIG4, 0,298 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);299 300 REG_SET_2(DSCC_PPS_CONFIG5, 0,301 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,302 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);303 304 REG_SET_3(DSCC_PPS_CONFIG6, 0,305 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,306 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,307 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);308 309 REG_SET_2(DSCC_PPS_CONFIG7, 0,310 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,311 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);312 313 REG_SET_2(DSCC_PPS_CONFIG8, 0,314 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,315 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);316 317 REG_SET_2(DSCC_PPS_CONFIG9, 0,318 INITIAL_OFFSET, reg_vals->pps.initial_offset,319 FINAL_OFFSET, reg_vals->pps.final_offset);320 321 REG_SET_3(DSCC_PPS_CONFIG10, 0,322 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,323 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,324 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);325 326 REG_SET_5(DSCC_PPS_CONFIG11, 0,327 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,328 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,329 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,330 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,331 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);332 333 REG_SET_4(DSCC_PPS_CONFIG12, 0,334 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],335 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],336 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],337 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);338 339 REG_SET_4(DSCC_PPS_CONFIG13, 0,340 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],341 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],342 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],343 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);344 345 REG_SET_4(DSCC_PPS_CONFIG14, 0,346 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],347 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],348 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],349 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);350 351 REG_SET_5(DSCC_PPS_CONFIG15, 0,352 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],353 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],354 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,355 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,356 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);357 358 REG_SET_6(DSCC_PPS_CONFIG16, 0,359 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,360 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,361 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,362 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,363 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,364 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);365 366 REG_SET_6(DSCC_PPS_CONFIG17, 0,367 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,368 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,369 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,370 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,371 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,372 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);373 374 REG_SET_6(DSCC_PPS_CONFIG18, 0,375 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,376 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,377 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,378 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,379 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,380 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);381 382 REG_SET_6(DSCC_PPS_CONFIG19, 0,383 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,384 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,385 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,386 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,387 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,388 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);389 390 REG_SET_6(DSCC_PPS_CONFIG20, 0,391 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,392 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,393 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,394 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,395 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,396 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);397 398 REG_SET_6(DSCC_PPS_CONFIG21, 0,399 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,400 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,401 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,402 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,403 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,404 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);405 406 REG_SET_6(DSCC_PPS_CONFIG22, 0,407 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,408 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,409 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,410 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,411 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,412 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);413}414 415void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)416{417 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);418}419