1701 lines · c
1/*2 * Copyright 2012-2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "dcn20_hubp.h"27 28#include "dm_services.h"29#include "dce_calcs.h"30#include "reg_helper.h"31#include "basics/conversion.h"32 33#define DC_LOGGER \34 ctx->logger35#define DC_LOGGER_INIT(logger)36 37#define REG(reg)\38 hubp2->hubp_regs->reg39 40#define CTX \41 hubp2->base.ctx42 43#undef FN44#define FN(reg_name, field_name) \45 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name46 47void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,48 struct vm_system_aperture_param *apt)49{50 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);51 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_default;53 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;54 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;55 56 // The format of default addr is 48:12 of the 48 bit addr57 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;58 59 // The format of high/low are 48:18 of the 48 bit addr60 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;61 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;62 63 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,64 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */65 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);66 67 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,68 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);69 70 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,71 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);72 73 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,74 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);75 76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,77 ENABLE_L1_TLB, 1,78 SYSTEM_ACCESS_MODE, 0x3);79}80 81void hubp2_program_deadline(82 struct hubp *hubp,83 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,84 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)85{86 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);87 88 /* DLG - Per hubp */89 REG_SET_2(BLANK_OFFSET_0, 0,90 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,91 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);92 93 REG_SET(BLANK_OFFSET_1, 0,94 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);95 96 REG_SET(DST_DIMENSIONS, 0,97 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);98 99 REG_SET_2(DST_AFTER_SCALER, 0,100 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,101 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);102 103 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,104 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);105 106 /* DLG - Per luma/chroma */107 REG_SET(VBLANK_PARAMETERS_1, 0,108 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);109 110 if (REG(NOM_PARAMETERS_0))111 REG_SET(NOM_PARAMETERS_0, 0,112 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);113 114 if (REG(NOM_PARAMETERS_1))115 REG_SET(NOM_PARAMETERS_1, 0,116 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);117 118 REG_SET(NOM_PARAMETERS_4, 0,119 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);120 121 REG_SET(NOM_PARAMETERS_5, 0,122 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);123 124 REG_SET_2(PER_LINE_DELIVERY, 0,125 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,126 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);127 128 REG_SET(VBLANK_PARAMETERS_2, 0,129 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);130 131 if (REG(NOM_PARAMETERS_2))132 REG_SET(NOM_PARAMETERS_2, 0,133 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);134 135 if (REG(NOM_PARAMETERS_3))136 REG_SET(NOM_PARAMETERS_3, 0,137 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);138 139 REG_SET(NOM_PARAMETERS_6, 0,140 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);141 142 REG_SET(NOM_PARAMETERS_7, 0,143 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);144 145 /* TTU - per hubp */146 REG_SET_2(DCN_TTU_QOS_WM, 0,147 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,148 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);149 150 /* TTU - per luma/chroma */151 /* Assumed surf0 is luma and 1 is chroma */152 153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,154 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,155 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,156 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);157 158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,159 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,160 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,161 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);162 163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,164 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,165 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,166 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);167 168 REG_SET(FLIP_PARAMETERS_1, 0,169 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);170}171 172void hubp2_vready_at_or_After_vsync(struct hubp *hubp,173 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)174{175 uint32_t value = 0;176 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);177 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */178 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);179 /*180 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)181 <= OTG_V_BLANK_END182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1183 else184 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0185 */186 if (pipe_dest->htotal != 0) {187 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {189 value = 1;190 } else191 value = 0;192 }193 194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);195}196 197static void hubp2_program_requestor(struct hubp *hubp,198 struct _vcs_dpi_display_rq_regs_st *rq_regs)199{200 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);201 202 REG_UPDATE(HUBPRET_CONTROL,203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);204 REG_SET_4(DCN_EXPANSION_MODE, 0,205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);209 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,214 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,215 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,216 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,217 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);218 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,219 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,220 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,221 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,222 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,223 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,224 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,225 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,226 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);227}228 229static void hubp2_setup(230 struct hubp *hubp,231 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,232 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,233 struct _vcs_dpi_display_rq_regs_st *rq_regs,234 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)235{236 /* otg is locked when this func is called. Register are double buffered.237 * disable the requestors is not needed238 */239 240 hubp2_vready_at_or_After_vsync(hubp, pipe_dest);241 hubp2_program_requestor(hubp, rq_regs);242 hubp2_program_deadline(hubp, dlg_attr, ttu_attr);243 244}245 246void hubp2_setup_interdependent(247 struct hubp *hubp,248 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,249 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)250{251 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);252 253 REG_SET_2(PREFETCH_SETTINGS, 0,254 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,255 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);256 257 REG_SET(PREFETCH_SETTINGS_C, 0,258 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);259 260 REG_SET_2(VBLANK_PARAMETERS_0, 0,261 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,262 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);263 264 REG_SET_2(FLIP_PARAMETERS_0, 0,265 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,266 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);267 268 REG_SET(VBLANK_PARAMETERS_3, 0,269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);270 271 REG_SET(VBLANK_PARAMETERS_4, 0,272 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);273 274 REG_SET(FLIP_PARAMETERS_2, 0,275 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);276 277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,278 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,279 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);280 281 REG_SET(DCN_SURF0_TTU_CNTL1, 0,282 REFCYC_PER_REQ_DELIVERY_PRE,283 ttu_attr->refcyc_per_req_delivery_pre_l);284 REG_SET(DCN_SURF1_TTU_CNTL1, 0,285 REFCYC_PER_REQ_DELIVERY_PRE,286 ttu_attr->refcyc_per_req_delivery_pre_c);287 REG_SET(DCN_CUR0_TTU_CNTL1, 0,288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);289 REG_SET(DCN_CUR1_TTU_CNTL1, 0,290 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);291 292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,293 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,294 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);295}296 297/* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:298 * NUM_BANKS299 * NUM_SE300 * NUM_RB_PER_SE301 * RB_ALIGNED302 * Other things can be defaulted, since they never change:303 * PIPE_ALIGNED = 0304 * META_LINEAR = 0305 * In GFX10, only these apply:306 * PIPE_INTERLEAVE307 * NUM_PIPES308 * MAX_COMPRESSED_FRAGS309 * SW_MODE310 */311static void hubp2_program_tiling(312 struct dcn20_hubp *hubp2,313 const union dc_tiling_info *info,314 const enum surface_pixel_format pixel_format)315{316 REG_UPDATE_3(DCSURF_ADDR_CONFIG,317 NUM_PIPES, log_2(info->gfx9.num_pipes),318 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,319 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));320 321 REG_UPDATE_4(DCSURF_TILING_CONFIG,322 SW_MODE, info->gfx9.swizzle,323 META_LINEAR, 0,324 RB_ALIGNED, 0,325 PIPE_ALIGNED, 0);326}327 328void hubp2_program_size(329 struct hubp *hubp,330 enum surface_pixel_format format,331 const struct plane_size *plane_size,332 struct dc_plane_dcc_param *dcc)333{334 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);335 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;336 bool use_pitch_c = false;337 338 /* Program data and meta surface pitch (calculation from addrlib)339 * 444 or 420 luma340 */341 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN342 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;343 use_pitch_c = use_pitch_c344 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);345 if (use_pitch_c) {346 ASSERT(plane_size->chroma_pitch != 0);347 /* Chroma pitch zero can cause system hang! */348 349 pitch = plane_size->surface_pitch - 1;350 meta_pitch = dcc->meta_pitch - 1;351 pitch_c = plane_size->chroma_pitch - 1;352 meta_pitch_c = dcc->meta_pitch_c - 1;353 } else {354 pitch = plane_size->surface_pitch - 1;355 meta_pitch = dcc->meta_pitch - 1;356 pitch_c = 0;357 meta_pitch_c = 0;358 }359 360 if (!dcc->enable) {361 meta_pitch = 0;362 meta_pitch_c = 0;363 }364 365 REG_UPDATE_2(DCSURF_SURFACE_PITCH,366 PITCH, pitch, META_PITCH, meta_pitch);367 368 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;369 use_pitch_c = use_pitch_c370 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);371 if (use_pitch_c)372 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,373 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);374}375 376void hubp2_program_rotation(377 struct hubp *hubp,378 enum dc_rotation_angle rotation,379 bool horizontal_mirror)380{381 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);382 uint32_t mirror;383 384 385 if (horizontal_mirror)386 mirror = 1;387 else388 mirror = 0;389 390 /* Program rotation angle and horz mirror - no mirror */391 if (rotation == ROTATION_ANGLE_0)392 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,393 ROTATION_ANGLE, 0,394 H_MIRROR_EN, mirror);395 else if (rotation == ROTATION_ANGLE_90)396 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,397 ROTATION_ANGLE, 1,398 H_MIRROR_EN, mirror);399 else if (rotation == ROTATION_ANGLE_180)400 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,401 ROTATION_ANGLE, 2,402 H_MIRROR_EN, mirror);403 else if (rotation == ROTATION_ANGLE_270)404 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,405 ROTATION_ANGLE, 3,406 H_MIRROR_EN, mirror);407}408 409void hubp2_dcc_control(struct hubp *hubp, bool enable,410 enum hubp_ind_block_size independent_64b_blks)411{412 uint32_t dcc_en = enable ? 1 : 0;413 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;414 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);415 416 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,417 PRIMARY_SURFACE_DCC_EN, dcc_en,418 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,419 SECONDARY_SURFACE_DCC_EN, dcc_en,420 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);421}422 423void hubp2_program_pixel_format(424 struct hubp *hubp,425 enum surface_pixel_format format)426{427 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);428 uint32_t red_bar = 3;429 uint32_t blue_bar = 2;430 431 /* swap for ABGR format */432 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888433 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010434 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS435 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616436 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {437 red_bar = 2;438 blue_bar = 3;439 }440 441 REG_UPDATE_2(HUBPRET_CONTROL,442 CROSSBAR_SRC_CB_B, blue_bar,443 CROSSBAR_SRC_CR_R, red_bar);444 445 /* Mapping is same as ipp programming (cnvc) */446 447 switch (format) {448 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:449 REG_UPDATE(DCSURF_SURFACE_CONFIG,450 SURFACE_PIXEL_FORMAT, 1);451 break;452 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:453 REG_UPDATE(DCSURF_SURFACE_CONFIG,454 SURFACE_PIXEL_FORMAT, 3);455 break;456 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:457 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:458 REG_UPDATE(DCSURF_SURFACE_CONFIG,459 SURFACE_PIXEL_FORMAT, 8);460 break;461 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:462 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:463 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:464 REG_UPDATE(DCSURF_SURFACE_CONFIG,465 SURFACE_PIXEL_FORMAT, 10);466 break;467 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:468 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/469 REG_UPDATE(DCSURF_SURFACE_CONFIG,470 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */471 break;472 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:473 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/474 REG_UPDATE(DCSURF_SURFACE_CONFIG,475 SURFACE_PIXEL_FORMAT, 24);476 break;477 478 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:479 REG_UPDATE(DCSURF_SURFACE_CONFIG,480 SURFACE_PIXEL_FORMAT, 65);481 break;482 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:483 REG_UPDATE(DCSURF_SURFACE_CONFIG,484 SURFACE_PIXEL_FORMAT, 64);485 break;486 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:487 REG_UPDATE(DCSURF_SURFACE_CONFIG,488 SURFACE_PIXEL_FORMAT, 67);489 break;490 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:491 REG_UPDATE(DCSURF_SURFACE_CONFIG,492 SURFACE_PIXEL_FORMAT, 66);493 break;494 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:495 REG_UPDATE(DCSURF_SURFACE_CONFIG,496 SURFACE_PIXEL_FORMAT, 12);497 break;498 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:499 REG_UPDATE(DCSURF_SURFACE_CONFIG,500 SURFACE_PIXEL_FORMAT, 112);501 break;502 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:503 REG_UPDATE(DCSURF_SURFACE_CONFIG,504 SURFACE_PIXEL_FORMAT, 113);505 break;506 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:507 REG_UPDATE(DCSURF_SURFACE_CONFIG,508 SURFACE_PIXEL_FORMAT, 114);509 break;510 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:511 REG_UPDATE(DCSURF_SURFACE_CONFIG,512 SURFACE_PIXEL_FORMAT, 118);513 break;514 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:515 REG_UPDATE(DCSURF_SURFACE_CONFIG,516 SURFACE_PIXEL_FORMAT, 119);517 break;518 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:519 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,520 SURFACE_PIXEL_FORMAT, 116,521 ALPHA_PLANE_EN, 0);522 break;523 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:524 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,525 SURFACE_PIXEL_FORMAT, 116,526 ALPHA_PLANE_EN, 1);527 break;528 default:529 BREAK_TO_DEBUGGER();530 break;531 }532 533 /* don't see the need of program the xbar in DCN 1.0 */534}535 536void hubp2_program_surface_config(537 struct hubp *hubp,538 enum surface_pixel_format format,539 union dc_tiling_info *tiling_info,540 struct plane_size *plane_size,541 enum dc_rotation_angle rotation,542 struct dc_plane_dcc_param *dcc,543 bool horizontal_mirror,544 unsigned int compat_level)545{546 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);547 548 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);549 hubp2_program_tiling(hubp2, tiling_info, format);550 hubp2_program_size(hubp, format, plane_size, dcc);551 hubp2_program_rotation(hubp, rotation, horizontal_mirror);552 hubp2_program_pixel_format(hubp, format);553}554 555enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(556 unsigned int cursor_width,557 enum dc_cursor_color_format cursor_mode)558{559 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;560 561 if (cursor_mode == CURSOR_MODE_MONO)562 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;563 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||564 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||565 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {566 if (cursor_width >= 1 && cursor_width <= 32)567 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;568 else if (cursor_width >= 33 && cursor_width <= 64)569 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;570 else if (cursor_width >= 65 && cursor_width <= 128)571 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;572 else if (cursor_width >= 129 && cursor_width <= 256)573 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;574 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||575 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {576 if (cursor_width >= 1 && cursor_width <= 16)577 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;578 else if (cursor_width >= 17 && cursor_width <= 32)579 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;580 else if (cursor_width >= 33 && cursor_width <= 64)581 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;582 else if (cursor_width >= 65 && cursor_width <= 128)583 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;584 else if (cursor_width >= 129 && cursor_width <= 256)585 line_per_chunk = CURSOR_LINE_PER_CHUNK_1;586 }587 588 return line_per_chunk;589}590 591void hubp2_cursor_set_attributes(592 struct hubp *hubp,593 const struct dc_cursor_attributes *attr)594{595 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);596 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);597 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(598 attr->width, attr->color_format);599 600 hubp->curs_attr = *attr;601 602 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,603 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);604 REG_UPDATE(CURSOR_SURFACE_ADDRESS,605 CURSOR_SURFACE_ADDRESS, attr->address.low_part);606 607 REG_UPDATE_2(CURSOR_SIZE,608 CURSOR_WIDTH, attr->width,609 CURSOR_HEIGHT, attr->height);610 611 REG_UPDATE_4(CURSOR_CONTROL,612 CURSOR_MODE, attr->color_format,613 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,614 CURSOR_PITCH, hw_pitch,615 CURSOR_LINES_PER_CHUNK, lpc);616 617 REG_SET_2(CURSOR_SETTINGS, 0,618 /* no shift of the cursor HDL schedule */619 CURSOR0_DST_Y_OFFSET, 0,620 /* used to shift the cursor chunk request deadline */621 CURSOR0_CHUNK_HDL_ADJUST, 3);622 623 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;624 hubp->att.SURFACE_ADDR = attr->address.low_part;625 hubp->att.size.bits.width = attr->width;626 hubp->att.size.bits.height = attr->height;627 hubp->att.cur_ctl.bits.mode = attr->color_format;628 629 hubp->cur_rect.w = attr->width;630 hubp->cur_rect.h = attr->height;631 632 hubp->att.cur_ctl.bits.pitch = hw_pitch;633 hubp->att.cur_ctl.bits.line_per_chunk = lpc;634 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;635 hubp->att.settings.bits.dst_y_offset = 0;636 hubp->att.settings.bits.chunk_hdl_adjust = 3;637}638 639void hubp2_dmdata_set_attributes(640 struct hubp *hubp,641 const struct dc_dmdata_attributes *attr)642{643 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);644 645 if (attr->dmdata_mode == DMDATA_HW_MODE) {646 /* set to HW mode */647 REG_UPDATE(DMDATA_CNTL,648 DMDATA_MODE, 1);649 650 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */651 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);652 653 /* toggle DMDATA_UPDATED and set repeat and size */654 REG_UPDATE(DMDATA_CNTL,655 DMDATA_UPDATED, 0);656 REG_UPDATE_3(DMDATA_CNTL,657 DMDATA_UPDATED, 1,658 DMDATA_REPEAT, attr->dmdata_repeat,659 DMDATA_SIZE, attr->dmdata_size);660 661 /* set DMDATA address */662 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);663 REG_UPDATE(DMDATA_ADDRESS_HIGH,664 DMDATA_ADDRESS_HIGH, attr->address.high_part);665 666 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);667 668 } else {669 /* set to SW mode before loading data */670 REG_SET(DMDATA_CNTL, 0,671 DMDATA_MODE, 0);672 /* toggle DMDATA_SW_UPDATED to start loading sequence */673 REG_UPDATE(DMDATA_SW_CNTL,674 DMDATA_SW_UPDATED, 0);675 REG_UPDATE_3(DMDATA_SW_CNTL,676 DMDATA_SW_UPDATED, 1,677 DMDATA_SW_REPEAT, attr->dmdata_repeat,678 DMDATA_SW_SIZE, attr->dmdata_size);679 /* load data into hubp dmdata buffer */680 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);681 }682 683 /* Note that DL_DELTA must be programmed if we want to use TTU mode */684 REG_SET_3(DMDATA_QOS_CNTL, 0,685 DMDATA_QOS_MODE, attr->dmdata_qos_mode,686 DMDATA_QOS_LEVEL, attr->dmdata_qos_level,687 DMDATA_DL_DELTA, attr->dmdata_dl_delta);688}689 690void hubp2_dmdata_load(691 struct hubp *hubp,692 uint32_t dmdata_sw_size,693 const uint32_t *dmdata_sw_data)694{695 int i;696 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);697 698 /* load dmdata into HUBP buffer in SW mode */699 for (i = 0; i < dmdata_sw_size / 4; i++)700 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);701}702 703bool hubp2_dmdata_status_done(struct hubp *hubp)704{705 uint32_t status;706 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);707 708 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);709 return (status == 1);710}711 712bool hubp2_program_surface_flip_and_addr(713 struct hubp *hubp,714 const struct dc_plane_address *address,715 bool flip_immediate)716{717 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);718 719 //program flip type720 REG_UPDATE(DCSURF_FLIP_CONTROL,721 SURFACE_FLIP_TYPE, flip_immediate);722 723 // Program VMID reg724 REG_UPDATE(VMID_SETTINGS_0,725 VMID, address->vmid);726 727 728 /* HW automatically latch rest of address register on write to729 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used730 *731 * program high first and then the low addr, order matters!732 */733 switch (address->type) {734 case PLN_ADDR_TYPE_GRAPHICS:735 /* DCN1.0 does not support const color736 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1737 * base on address->grph.dcc_const_color738 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma739 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma740 */741 742 if (address->grph.addr.quad_part == 0)743 break;744 745 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,746 PRIMARY_SURFACE_TMZ, address->tmz_surface,747 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);748 749 if (address->grph.meta_addr.quad_part != 0) {750 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,751 PRIMARY_META_SURFACE_ADDRESS_HIGH,752 address->grph.meta_addr.high_part);753 754 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,755 PRIMARY_META_SURFACE_ADDRESS,756 address->grph.meta_addr.low_part);757 }758 759 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,760 PRIMARY_SURFACE_ADDRESS_HIGH,761 address->grph.addr.high_part);762 763 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,764 PRIMARY_SURFACE_ADDRESS,765 address->grph.addr.low_part);766 break;767 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:768 if (address->video_progressive.luma_addr.quad_part == 0769 || address->video_progressive.chroma_addr.quad_part == 0)770 break;771 772 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,773 PRIMARY_SURFACE_TMZ, address->tmz_surface,774 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,775 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,776 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);777 778 if (address->video_progressive.luma_meta_addr.quad_part != 0) {779 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,780 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,781 address->video_progressive.chroma_meta_addr.high_part);782 783 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,784 PRIMARY_META_SURFACE_ADDRESS_C,785 address->video_progressive.chroma_meta_addr.low_part);786 787 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,788 PRIMARY_META_SURFACE_ADDRESS_HIGH,789 address->video_progressive.luma_meta_addr.high_part);790 791 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,792 PRIMARY_META_SURFACE_ADDRESS,793 address->video_progressive.luma_meta_addr.low_part);794 }795 796 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,797 PRIMARY_SURFACE_ADDRESS_HIGH_C,798 address->video_progressive.chroma_addr.high_part);799 800 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,801 PRIMARY_SURFACE_ADDRESS_C,802 address->video_progressive.chroma_addr.low_part);803 804 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,805 PRIMARY_SURFACE_ADDRESS_HIGH,806 address->video_progressive.luma_addr.high_part);807 808 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,809 PRIMARY_SURFACE_ADDRESS,810 address->video_progressive.luma_addr.low_part);811 break;812 case PLN_ADDR_TYPE_GRPH_STEREO:813 if (address->grph_stereo.left_addr.quad_part == 0)814 break;815 if (address->grph_stereo.right_addr.quad_part == 0)816 break;817 818 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,819 PRIMARY_SURFACE_TMZ, address->tmz_surface,820 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,821 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,822 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,823 SECONDARY_SURFACE_TMZ, address->tmz_surface,824 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,825 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,826 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);827 828 if (address->grph_stereo.right_meta_addr.quad_part != 0) {829 830 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,831 SECONDARY_META_SURFACE_ADDRESS_HIGH,832 address->grph_stereo.right_meta_addr.high_part);833 834 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,835 SECONDARY_META_SURFACE_ADDRESS,836 address->grph_stereo.right_meta_addr.low_part);837 }838 if (address->grph_stereo.left_meta_addr.quad_part != 0) {839 840 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,841 PRIMARY_META_SURFACE_ADDRESS_HIGH,842 address->grph_stereo.left_meta_addr.high_part);843 844 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,845 PRIMARY_META_SURFACE_ADDRESS,846 address->grph_stereo.left_meta_addr.low_part);847 }848 849 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,850 SECONDARY_SURFACE_ADDRESS_HIGH,851 address->grph_stereo.right_addr.high_part);852 853 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,854 SECONDARY_SURFACE_ADDRESS,855 address->grph_stereo.right_addr.low_part);856 857 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,858 PRIMARY_SURFACE_ADDRESS_HIGH,859 address->grph_stereo.left_addr.high_part);860 861 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,862 PRIMARY_SURFACE_ADDRESS,863 address->grph_stereo.left_addr.low_part);864 break;865 default:866 BREAK_TO_DEBUGGER();867 break;868 }869 870 hubp->request_address = *address;871 872 return true;873}874 875void hubp2_enable_triplebuffer(876 struct hubp *hubp,877 bool enable)878{879 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);880 uint32_t triple_buffer_en = 0;881 bool tri_buffer_en;882 883 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);884 tri_buffer_en = (triple_buffer_en == 1);885 if (tri_buffer_en != enable) {886 REG_UPDATE(DCSURF_FLIP_CONTROL2,887 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);888 }889}890 891bool hubp2_is_triplebuffer_enabled(892 struct hubp *hubp)893{894 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);895 uint32_t triple_buffer_en = 0;896 897 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);898 899 return (bool)triple_buffer_en;900}901 902void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)903{904 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);905 906 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);907}908 909bool hubp2_is_flip_pending(struct hubp *hubp)910{911 uint32_t flip_pending = 0;912 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);913 struct dc_plane_address earliest_inuse_address;914 915 if (hubp && hubp->power_gated)916 return false;917 918 REG_GET(DCSURF_FLIP_CONTROL,919 SURFACE_FLIP_PENDING, &flip_pending);920 921 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,922 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);923 924 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,925 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);926 927 if (flip_pending)928 return true;929 930 if (hubp &&931 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)932 return true;933 934 return false;935}936 937void hubp2_set_blank(struct hubp *hubp, bool blank)938{939 hubp2_set_blank_regs(hubp, blank);940 941 if (blank) {942 hubp->mpcc_id = 0xf;943 hubp->opp_id = OPP_ID_INVALID;944 }945}946 947void hubp2_set_blank_regs(struct hubp *hubp, bool blank)948{949 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);950 uint32_t blank_en = blank ? 1 : 0;951 952 if (blank) {953 uint32_t reg_val = REG_READ(DCHUBP_CNTL);954 955 if (reg_val) {956 /* init sequence workaround: in case HUBP is957 * power gated, this wait would timeout.958 *959 * we just wrote reg_val to non-0, if it stay 0960 * it means HUBP is gated961 */962 REG_WAIT(DCHUBP_CNTL,963 HUBP_NO_OUTSTANDING_REQ, 1,964 1, 100000);965 }966 }967 968 REG_UPDATE_2(DCHUBP_CNTL,969 HUBP_BLANK_EN, blank_en,970 HUBP_TTU_DISABLE, 0);971}972 973void hubp2_cursor_set_position(974 struct hubp *hubp,975 const struct dc_cursor_position *pos,976 const struct dc_cursor_mi_param *param)977{978 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);979 int x_pos = pos->x - param->viewport.x;980 int y_pos = pos->y - param->viewport.y;981 int x_hotspot = pos->x_hotspot;982 int y_hotspot = pos->y_hotspot;983 int src_x_offset = x_pos - pos->x_hotspot;984 int src_y_offset = y_pos - pos->y_hotspot;985 int cursor_height = (int)hubp->curs_attr.height;986 int cursor_width = (int)hubp->curs_attr.width;987 uint32_t dst_x_offset;988 uint32_t cur_en = pos->enable ? 1 : 0;989 990 hubp->curs_pos = *pos;991 992 /*993 * Guard aganst cursor_set_position() from being called with invalid994 * attributes995 *996 * TODO: Look at combining cursor_set_position() and997 * cursor_set_attributes() into cursor_update()998 */999 if (hubp->curs_attr.address.quad_part == 0)1000 return;1001 1002 // Transform cursor width / height and hotspots for offset calculations1003 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {1004 swap(cursor_height, cursor_width);1005 swap(x_hotspot, y_hotspot);1006 1007 if (param->rotation == ROTATION_ANGLE_90) {1008 // hotspot = (-y, x)1009 src_x_offset = x_pos - (cursor_width - x_hotspot);1010 src_y_offset = y_pos - y_hotspot;1011 } else if (param->rotation == ROTATION_ANGLE_270) {1012 // hotspot = (y, -x)1013 src_x_offset = x_pos - x_hotspot;1014 src_y_offset = y_pos - (cursor_height - y_hotspot);1015 }1016 } else if (param->rotation == ROTATION_ANGLE_180) {1017 // hotspot = (-x, -y)1018 if (!param->mirror)1019 src_x_offset = x_pos - (cursor_width - x_hotspot);1020 1021 src_y_offset = y_pos - (cursor_height - y_hotspot);1022 }1023 1024 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;1025 dst_x_offset *= param->ref_clk_khz;1026 dst_x_offset /= param->pixel_clk_khz;1027 1028 ASSERT(param->h_scale_ratio.value);1029 1030 if (param->h_scale_ratio.value)1031 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(1032 dc_fixpt_from_int(dst_x_offset),1033 param->h_scale_ratio));1034 1035 if (src_x_offset >= (int)param->viewport.width)1036 cur_en = 0; /* not visible beyond right edge*/1037 1038 if (src_x_offset + cursor_width <= 0)1039 cur_en = 0; /* not visible beyond left edge*/1040 1041 if (src_y_offset >= (int)param->viewport.height)1042 cur_en = 0; /* not visible beyond bottom edge*/1043 1044 if (src_y_offset + cursor_height <= 0)1045 cur_en = 0; /* not visible beyond top edge*/1046 1047 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)1048 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);1049 1050 REG_UPDATE(CURSOR_CONTROL,1051 CURSOR_ENABLE, cur_en);1052 1053 REG_SET_2(CURSOR_POSITION, 0,1054 CURSOR_X_POSITION, pos->x,1055 CURSOR_Y_POSITION, pos->y);1056 1057 REG_SET_2(CURSOR_HOT_SPOT, 0,1058 CURSOR_HOT_SPOT_X, pos->x_hotspot,1059 CURSOR_HOT_SPOT_Y, pos->y_hotspot);1060 1061 REG_SET(CURSOR_DST_OFFSET, 0,1062 CURSOR_DST_X_OFFSET, dst_x_offset);1063 /* TODO Handle surface pixel formats other than 4:4:4 */1064 /* Cursor Position Register Config */1065 hubp->pos.cur_ctl.bits.cur_enable = cur_en;1066 hubp->pos.position.bits.x_pos = pos->x;1067 hubp->pos.position.bits.y_pos = pos->y;1068 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;1069 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;1070 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;1071 /* Cursor Rectangle Cache1072 * Cursor bitmaps have different hotspot values1073 * There's a possibility that the above logic returns a negative value,1074 * so we clamp them to 01075 */1076 if (src_x_offset < 0)1077 src_x_offset = 0;1078 if (src_y_offset < 0)1079 src_y_offset = 0;1080 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */1081 if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&1082 param->rotation != ROTATION_ANGLE_0) {1083 hubp->cur_rect.x = 0;1084 hubp->cur_rect.y = 0;1085 hubp->cur_rect.w = param->stream->timing.h_addressable;1086 hubp->cur_rect.h = param->stream->timing.v_addressable;1087 } else {1088 hubp->cur_rect.x = src_x_offset + param->viewport.x;1089 hubp->cur_rect.y = src_y_offset + param->viewport.y;1090 }1091}1092 1093void hubp2_clk_cntl(struct hubp *hubp, bool enable)1094{1095 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1096 uint32_t clk_enable = enable ? 1 : 0;1097 1098 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);1099}1100 1101void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)1102{1103 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1104 1105 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);1106}1107 1108void hubp2_clear_underflow(struct hubp *hubp)1109{1110 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1111 1112 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);1113}1114 1115void hubp2_read_state_common(struct hubp *hubp)1116{1117 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1118 struct dcn_hubp_state *s = &hubp2->state;1119 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;1120 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;1121 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;1122 1123 /* Requester */1124 REG_GET(HUBPRET_CONTROL,1125 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);1126 REG_GET_4(DCN_EXPANSION_MODE,1127 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,1128 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,1129 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,1130 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);1131 1132 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,1133 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);1134 1135 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,1136 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);1137 1138 /* DLG - Per hubp */1139 REG_GET_2(BLANK_OFFSET_0,1140 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,1141 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);1142 1143 REG_GET(BLANK_OFFSET_1,1144 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);1145 1146 REG_GET(DST_DIMENSIONS,1147 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);1148 1149 REG_GET_2(DST_AFTER_SCALER,1150 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,1151 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);1152 1153 if (REG(PREFETCH_SETTINS))1154 REG_GET_2(PREFETCH_SETTINS,1155 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,1156 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);1157 else1158 REG_GET_2(PREFETCH_SETTINGS,1159 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,1160 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);1161 1162 REG_GET_2(VBLANK_PARAMETERS_0,1163 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,1164 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);1165 1166 REG_GET(REF_FREQ_TO_PIX_FREQ,1167 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);1168 1169 /* DLG - Per luma/chroma */1170 REG_GET(VBLANK_PARAMETERS_1,1171 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);1172 1173 REG_GET(VBLANK_PARAMETERS_3,1174 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);1175 1176 if (REG(NOM_PARAMETERS_0))1177 REG_GET(NOM_PARAMETERS_0,1178 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);1179 1180 if (REG(NOM_PARAMETERS_1))1181 REG_GET(NOM_PARAMETERS_1,1182 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);1183 1184 REG_GET(NOM_PARAMETERS_4,1185 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);1186 1187 REG_GET(NOM_PARAMETERS_5,1188 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);1189 1190 REG_GET_2(PER_LINE_DELIVERY_PRE,1191 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,1192 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);1193 1194 REG_GET_2(PER_LINE_DELIVERY,1195 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,1196 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);1197 1198 if (REG(PREFETCH_SETTINS_C))1199 REG_GET(PREFETCH_SETTINS_C,1200 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);1201 else1202 REG_GET(PREFETCH_SETTINGS_C,1203 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);1204 1205 REG_GET(VBLANK_PARAMETERS_2,1206 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);1207 1208 REG_GET(VBLANK_PARAMETERS_4,1209 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);1210 1211 if (REG(NOM_PARAMETERS_2))1212 REG_GET(NOM_PARAMETERS_2,1213 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);1214 1215 if (REG(NOM_PARAMETERS_3))1216 REG_GET(NOM_PARAMETERS_3,1217 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);1218 1219 REG_GET(NOM_PARAMETERS_6,1220 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);1221 1222 REG_GET(NOM_PARAMETERS_7,1223 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);1224 1225 /* TTU - per hubp */1226 REG_GET_2(DCN_TTU_QOS_WM,1227 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,1228 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);1229 1230 REG_GET_2(DCN_GLOBAL_TTU_CNTL,1231 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,1232 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);1233 1234 /* TTU - per luma/chroma */1235 /* Assumed surf0 is luma and 1 is chroma */1236 1237 REG_GET_3(DCN_SURF0_TTU_CNTL0,1238 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,1239 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,1240 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);1241 1242 REG_GET(DCN_SURF0_TTU_CNTL1,1243 REFCYC_PER_REQ_DELIVERY_PRE,1244 &ttu_attr->refcyc_per_req_delivery_pre_l);1245 1246 REG_GET_3(DCN_SURF1_TTU_CNTL0,1247 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,1248 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,1249 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);1250 1251 REG_GET(DCN_SURF1_TTU_CNTL1,1252 REFCYC_PER_REQ_DELIVERY_PRE,1253 &ttu_attr->refcyc_per_req_delivery_pre_c);1254 1255 /* Rest of hubp */1256 REG_GET(DCSURF_SURFACE_CONFIG,1257 SURFACE_PIXEL_FORMAT, &s->pixel_format);1258 1259 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,1260 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);1261 1262 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,1263 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);1264 1265 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,1266 PRI_VIEWPORT_WIDTH, &s->viewport_width,1267 PRI_VIEWPORT_HEIGHT, &s->viewport_height);1268 1269 REG_GET_2(DCSURF_SURFACE_CONFIG,1270 ROTATION_ANGLE, &s->rotation_angle,1271 H_MIRROR_EN, &s->h_mirror_en);1272 1273 REG_GET(DCSURF_TILING_CONFIG,1274 SW_MODE, &s->sw_mode);1275 1276 REG_GET(DCSURF_SURFACE_CONTROL,1277 PRIMARY_SURFACE_DCC_EN, &s->dcc_en);1278 1279 REG_GET_3(DCHUBP_CNTL,1280 HUBP_BLANK_EN, &s->blank_en,1281 HUBP_TTU_DISABLE, &s->ttu_disable,1282 HUBP_UNDERFLOW_STATUS, &s->underflow_status);1283 1284 REG_GET(HUBP_CLK_CNTL,1285 HUBP_CLOCK_ENABLE, &s->clock_en);1286 1287 REG_GET(DCN_GLOBAL_TTU_CNTL,1288 MIN_TTU_VBLANK, &s->min_ttu_vblank);1289 1290 REG_GET_2(DCN_TTU_QOS_WM,1291 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,1292 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);1293 1294 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,1295 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);1296 1297 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,1298 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);1299 1300 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,1301 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);1302 1303 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,1304 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);1305}1306 1307void hubp2_read_state(struct hubp *hubp)1308{1309 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1310 struct dcn_hubp_state *s = &hubp2->state;1311 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;1312 1313 hubp2_read_state_common(hubp);1314 1315 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,1316 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,1317 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,1318 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,1319 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,1320 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,1321 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,1322 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,1323 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);1324 1325 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,1326 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,1327 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,1328 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,1329 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,1330 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,1331 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,1332 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,1333 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);1334 1335 if (REG(DCHUBP_CNTL))1336 s->hubp_cntl = REG_READ(DCHUBP_CNTL);1337 1338 if (REG(DCSURF_FLIP_CONTROL))1339 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);1340 1341}1342 1343static void hubp2_validate_dml_output(struct hubp *hubp,1344 struct dc_context *ctx,1345 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,1346 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,1347 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)1348{1349 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);1350 struct _vcs_dpi_display_rq_regs_st rq_regs = {0};1351 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};1352 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};1353 DC_LOGGER_INIT(ctx->logger);1354 DC_LOG_DEBUG("DML Validation | Running Validation");1355 1356 /* Requestor Regs */1357 REG_GET(HUBPRET_CONTROL,1358 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);1359 REG_GET_4(DCN_EXPANSION_MODE,1360 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,1361 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,1362 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,1363 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);1364 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,1365 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,1366 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,1367 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,1368 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,1369 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,1370 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,1371 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,1372 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);1373 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,1374 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,1375 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,1376 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,1377 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,1378 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,1379 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,1380 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,1381 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);1382 1383 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)1384 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",1385 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);1386 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)1387 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",1388 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);1389 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)1390 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",1391 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);1392 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)1393 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",1394 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);1395 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)1396 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",1397 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);1398 1399 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)1400 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",1401 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);1402 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)1403 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",1404 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);1405 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)1406 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",1407 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);1408 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)1409 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",1410 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);1411 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)1412 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",1413 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);1414 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)1415 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n",1416 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);1417 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)1418 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",1419 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);1420 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)1421 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",1422 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);1423 1424 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)1425 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",1426 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);1427 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)1428 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",1429 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);1430 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)1431 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",1432 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);1433 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)1434 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",1435 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);1436 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)1437 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",1438 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);1439 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)1440 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",1441 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);1442 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)1443 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",1444 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);1445 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)1446 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",1447 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);1448 1449 /* DLG - Per hubp */1450 REG_GET_2(BLANK_OFFSET_0,1451 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,1452 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);1453 REG_GET(BLANK_OFFSET_1,1454 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);1455 REG_GET(DST_DIMENSIONS,1456 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);1457 REG_GET_2(DST_AFTER_SCALER,1458 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,1459 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);1460 REG_GET(REF_FREQ_TO_PIX_FREQ,1461 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);1462 1463 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)1464 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",1465 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);1466 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)1467 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",1468 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);1469 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)1470 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",1471 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);1472 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)1473 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",1474 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);1475 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)1476 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",1477 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);1478 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)1479 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",1480 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);1481 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)1482 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",1483 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);1484 1485 /* DLG - Per luma/chroma */1486 REG_GET(VBLANK_PARAMETERS_1,1487 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);1488 if (REG(NOM_PARAMETERS_0))1489 REG_GET(NOM_PARAMETERS_0,1490 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);1491 if (REG(NOM_PARAMETERS_1))1492 REG_GET(NOM_PARAMETERS_1,1493 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);1494 REG_GET(NOM_PARAMETERS_4,1495 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);1496 REG_GET(NOM_PARAMETERS_5,1497 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);1498 REG_GET_2(PER_LINE_DELIVERY,1499 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,1500 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);1501 REG_GET_2(PER_LINE_DELIVERY_PRE,1502 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,1503 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);1504 REG_GET(VBLANK_PARAMETERS_2,1505 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);1506 if (REG(NOM_PARAMETERS_2))1507 REG_GET(NOM_PARAMETERS_2,1508 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);1509 if (REG(NOM_PARAMETERS_3))1510 REG_GET(NOM_PARAMETERS_3,1511 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);1512 REG_GET(NOM_PARAMETERS_6,1513 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);1514 REG_GET(NOM_PARAMETERS_7,1515 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);1516 REG_GET(VBLANK_PARAMETERS_3,1517 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);1518 REG_GET(VBLANK_PARAMETERS_4,1519 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);1520 1521 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)1522 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",1523 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);1524 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)1525 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",1526 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);1527 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)1528 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",1529 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);1530 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)1531 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",1532 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);1533 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)1534 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",1535 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);1536 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)1537 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",1538 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);1539 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)1540 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",1541 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);1542 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)1543 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",1544 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);1545 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)1546 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",1547 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);1548 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)1549 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",1550 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);1551 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)1552 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",1553 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);1554 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)1555 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",1556 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);1557 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)1558 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",1559 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);1560 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)1561 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",1562 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);1563 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)1564 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",1565 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);1566 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)1567 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",1568 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);1569 1570 /* TTU - per hubp */1571 REG_GET_2(DCN_TTU_QOS_WM,1572 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,1573 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);1574 1575 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)1576 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",1577 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);1578 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)1579 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",1580 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);1581 1582 /* TTU - per luma/chroma */1583 /* Assumed surf0 is luma and 1 is chroma */1584 REG_GET_3(DCN_SURF0_TTU_CNTL0,1585 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,1586 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,1587 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);1588 REG_GET_3(DCN_SURF1_TTU_CNTL0,1589 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,1590 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,1591 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);1592 REG_GET_3(DCN_CUR0_TTU_CNTL0,1593 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,1594 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,1595 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);1596 REG_GET(FLIP_PARAMETERS_1,1597 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);1598 REG_GET(DCN_CUR0_TTU_CNTL1,1599 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);1600 REG_GET(DCN_CUR1_TTU_CNTL1,1601 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);1602 REG_GET(DCN_SURF0_TTU_CNTL1,1603 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);1604 REG_GET(DCN_SURF1_TTU_CNTL1,1605 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);1606 1607 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)1608 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",1609 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);1610 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)1611 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",1612 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);1613 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)1614 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",1615 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);1616 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)1617 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",1618 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);1619 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)1620 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",1621 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);1622 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)1623 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",1624 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);1625 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)1626 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",1627 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);1628 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)1629 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",1630 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);1631 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)1632 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",1633 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);1634 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)1635 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",1636 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);1637 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)1638 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",1639 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);1640 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)1641 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",1642 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);1643 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)1644 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",1645 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);1646 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)1647 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",1648 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);1649}1650 1651static struct hubp_funcs dcn20_hubp_funcs = {1652 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,1653 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,1654 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,1655 .hubp_program_surface_config = hubp2_program_surface_config,1656 .hubp_is_flip_pending = hubp2_is_flip_pending,1657 .hubp_setup = hubp2_setup,1658 .hubp_setup_interdependent = hubp2_setup_interdependent,1659 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,1660 .set_blank = hubp2_set_blank,1661 .set_blank_regs = hubp2_set_blank_regs,1662 .dcc_control = hubp2_dcc_control,1663 .mem_program_viewport = min_set_viewport,1664 .set_cursor_attributes = hubp2_cursor_set_attributes,1665 .set_cursor_position = hubp2_cursor_set_position,1666 .hubp_clk_cntl = hubp2_clk_cntl,1667 .hubp_vtg_sel = hubp2_vtg_sel,1668 .dmdata_set_attributes = hubp2_dmdata_set_attributes,1669 .dmdata_load = hubp2_dmdata_load,1670 .dmdata_status_done = hubp2_dmdata_status_done,1671 .hubp_read_state = hubp2_read_state,1672 .hubp_clear_underflow = hubp2_clear_underflow,1673 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,1674 .hubp_init = hubp1_init,1675 .validate_dml_output = hubp2_validate_dml_output,1676 .hubp_in_blank = hubp1_in_blank,1677 .hubp_soft_reset = hubp1_soft_reset,1678 .hubp_set_flip_int = hubp1_set_flip_int,1679};1680 1681 1682bool hubp2_construct(1683 struct dcn20_hubp *hubp2,1684 struct dc_context *ctx,1685 uint32_t inst,1686 const struct dcn_hubp2_registers *hubp_regs,1687 const struct dcn_hubp2_shift *hubp_shift,1688 const struct dcn_hubp2_mask *hubp_mask)1689{1690 hubp2->base.funcs = &dcn20_hubp_funcs;1691 hubp2->base.ctx = ctx;1692 hubp2->hubp_regs = hubp_regs;1693 hubp2->hubp_shift = hubp_shift;1694 hubp2->hubp_mask = hubp_mask;1695 hubp2->base.inst = inst;1696 hubp2->base.opp_id = OPP_ID_INVALID;1697 hubp2->base.mpcc_id = 0xf;1698 1699 return true;1700}1701