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1/*2 * Copyright 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "dcn30_hubp.h"27 28#include "dm_services.h"29#include "dce_calcs.h"30#include "reg_helper.h"31#include "basics/conversion.h"32#include "dcn20/dcn20_hubp.h"33#include "dcn21/dcn21_hubp.h"34 35#define REG(reg)\36 hubp2->hubp_regs->reg37 38#define CTX \39 hubp2->base.ctx40 41#undef FN42#define FN(reg_name, field_name) \43 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name44 45void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,46 struct vm_system_aperture_param *apt)47{48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);49 50 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;51 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;52 53 // The format of high/low are 48:18 of the 48 bit addr54 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;55 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;56 57 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,58 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);59 60 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,61 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);62 63 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,64 ENABLE_L1_TLB, 1,65 SYSTEM_ACCESS_MODE, 0x3);66}67 68bool hubp3_program_surface_flip_and_addr(69 struct hubp *hubp,70 const struct dc_plane_address *address,71 bool flip_immediate)72{73 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);74 75 //program flip type76 REG_UPDATE(DCSURF_FLIP_CONTROL,77 SURFACE_FLIP_TYPE, flip_immediate);78 79 // Program VMID reg80 if (flip_immediate == 0)81 REG_UPDATE(VMID_SETTINGS_0,82 VMID, address->vmid);83 84 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {85 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);86 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);87 88 } else {89 // turn off stereo if not in stereo90 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);91 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);92 }93 94 /* HW automatically latch rest of address register on write to95 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used96 *97 * program high first and then the low addr, order matters!98 */99 switch (address->type) {100 case PLN_ADDR_TYPE_GRAPHICS:101 /* DCN1.0 does not support const color102 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1103 * base on address->grph.dcc_const_color104 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma105 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma106 */107 108 if (address->grph.addr.quad_part == 0)109 break;110 111 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,112 PRIMARY_SURFACE_TMZ, address->tmz_surface,113 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);114 115 if (address->grph.meta_addr.quad_part != 0) {116 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,117 PRIMARY_META_SURFACE_ADDRESS_HIGH,118 address->grph.meta_addr.high_part);119 120 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,121 PRIMARY_META_SURFACE_ADDRESS,122 address->grph.meta_addr.low_part);123 }124 125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,126 PRIMARY_SURFACE_ADDRESS_HIGH,127 address->grph.addr.high_part);128 129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,130 PRIMARY_SURFACE_ADDRESS,131 address->grph.addr.low_part);132 break;133 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:134 if (address->video_progressive.luma_addr.quad_part == 0135 || address->video_progressive.chroma_addr.quad_part == 0)136 break;137 138 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,139 PRIMARY_SURFACE_TMZ, address->tmz_surface,140 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,141 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,142 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);143 144 if (address->video_progressive.luma_meta_addr.quad_part != 0) {145 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,146 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,147 address->video_progressive.chroma_meta_addr.high_part);148 149 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,150 PRIMARY_META_SURFACE_ADDRESS_C,151 address->video_progressive.chroma_meta_addr.low_part);152 153 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,154 PRIMARY_META_SURFACE_ADDRESS_HIGH,155 address->video_progressive.luma_meta_addr.high_part);156 157 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,158 PRIMARY_META_SURFACE_ADDRESS,159 address->video_progressive.luma_meta_addr.low_part);160 }161 162 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,163 PRIMARY_SURFACE_ADDRESS_HIGH_C,164 address->video_progressive.chroma_addr.high_part);165 166 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,167 PRIMARY_SURFACE_ADDRESS_C,168 address->video_progressive.chroma_addr.low_part);169 170 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,171 PRIMARY_SURFACE_ADDRESS_HIGH,172 address->video_progressive.luma_addr.high_part);173 174 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,175 PRIMARY_SURFACE_ADDRESS,176 address->video_progressive.luma_addr.low_part);177 break;178 case PLN_ADDR_TYPE_GRPH_STEREO:179 if (address->grph_stereo.left_addr.quad_part == 0)180 break;181 if (address->grph_stereo.right_addr.quad_part == 0)182 break;183 184 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,185 PRIMARY_SURFACE_TMZ, address->tmz_surface,186 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,187 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,188 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,189 SECONDARY_SURFACE_TMZ, address->tmz_surface,190 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,191 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,192 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);193 194 if (address->grph_stereo.right_meta_addr.quad_part != 0) {195 196 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,197 SECONDARY_META_SURFACE_ADDRESS_HIGH_C,198 address->grph_stereo.right_alpha_meta_addr.high_part);199 200 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,201 SECONDARY_META_SURFACE_ADDRESS_C,202 address->grph_stereo.right_alpha_meta_addr.low_part);203 204 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,205 SECONDARY_META_SURFACE_ADDRESS_HIGH,206 address->grph_stereo.right_meta_addr.high_part);207 208 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,209 SECONDARY_META_SURFACE_ADDRESS,210 address->grph_stereo.right_meta_addr.low_part);211 }212 if (address->grph_stereo.left_meta_addr.quad_part != 0) {213 214 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,215 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,216 address->grph_stereo.left_alpha_meta_addr.high_part);217 218 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,219 PRIMARY_META_SURFACE_ADDRESS_C,220 address->grph_stereo.left_alpha_meta_addr.low_part);221 222 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,223 PRIMARY_META_SURFACE_ADDRESS_HIGH,224 address->grph_stereo.left_meta_addr.high_part);225 226 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,227 PRIMARY_META_SURFACE_ADDRESS,228 address->grph_stereo.left_meta_addr.low_part);229 }230 231 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,232 SECONDARY_SURFACE_ADDRESS_HIGH_C,233 address->grph_stereo.right_alpha_addr.high_part);234 235 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,236 SECONDARY_SURFACE_ADDRESS_C,237 address->grph_stereo.right_alpha_addr.low_part);238 239 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,240 SECONDARY_SURFACE_ADDRESS_HIGH,241 address->grph_stereo.right_addr.high_part);242 243 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,244 SECONDARY_SURFACE_ADDRESS,245 address->grph_stereo.right_addr.low_part);246 247 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,248 PRIMARY_SURFACE_ADDRESS_HIGH_C,249 address->grph_stereo.left_alpha_addr.high_part);250 251 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,252 PRIMARY_SURFACE_ADDRESS_C,253 address->grph_stereo.left_alpha_addr.low_part);254 255 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,256 PRIMARY_SURFACE_ADDRESS_HIGH,257 address->grph_stereo.left_addr.high_part);258 259 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,260 PRIMARY_SURFACE_ADDRESS,261 address->grph_stereo.left_addr.low_part);262 break;263 case PLN_ADDR_TYPE_RGBEA:264 if (address->rgbea.addr.quad_part == 0265 || address->rgbea.alpha_addr.quad_part == 0)266 break;267 268 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,269 PRIMARY_SURFACE_TMZ, address->tmz_surface,270 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,271 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,272 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);273 274 if (address->rgbea.meta_addr.quad_part != 0) {275 276 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,277 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,278 address->rgbea.alpha_meta_addr.high_part);279 280 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,281 PRIMARY_META_SURFACE_ADDRESS_C,282 address->rgbea.alpha_meta_addr.low_part);283 284 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,285 PRIMARY_META_SURFACE_ADDRESS_HIGH,286 address->rgbea.meta_addr.high_part);287 288 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,289 PRIMARY_META_SURFACE_ADDRESS,290 address->rgbea.meta_addr.low_part);291 }292 293 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,294 PRIMARY_SURFACE_ADDRESS_HIGH_C,295 address->rgbea.alpha_addr.high_part);296 297 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,298 PRIMARY_SURFACE_ADDRESS_C,299 address->rgbea.alpha_addr.low_part);300 301 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,302 PRIMARY_SURFACE_ADDRESS_HIGH,303 address->rgbea.addr.high_part);304 305 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,306 PRIMARY_SURFACE_ADDRESS,307 address->rgbea.addr.low_part);308 break;309 default:310 BREAK_TO_DEBUGGER();311 break;312 }313 314 hubp->request_address = *address;315 316 return true;317}318 319void hubp3_program_tiling(320 struct dcn20_hubp *hubp2,321 const union dc_tiling_info *info,322 const enum surface_pixel_format pixel_format)323{324 REG_UPDATE_4(DCSURF_ADDR_CONFIG,325 NUM_PIPES, log_2(info->gfx9.num_pipes),326 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,327 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),328 NUM_PKRS, log_2(info->gfx9.num_pkrs));329 330 REG_UPDATE_3(DCSURF_TILING_CONFIG,331 SW_MODE, info->gfx9.swizzle,332 META_LINEAR, info->gfx9.meta_linear,333 PIPE_ALIGNED, info->gfx9.pipe_aligned);334 335}336 337void hubp3_dcc_control(struct hubp *hubp, bool enable,338 enum hubp_ind_block_size blk_size)339{340 uint32_t dcc_en = enable ? 1 : 0;341 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);342 343 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,344 PRIMARY_SURFACE_DCC_EN, dcc_en,345 PRIMARY_SURFACE_DCC_IND_BLK, blk_size,346 SECONDARY_SURFACE_DCC_EN, dcc_en,347 SECONDARY_SURFACE_DCC_IND_BLK, blk_size);348}349 350void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,351 struct dc_plane_dcc_param *dcc)352{353 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);354 355 REG_UPDATE_6(DCSURF_SURFACE_CONTROL,356 PRIMARY_SURFACE_DCC_EN, dcc->enable,357 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,358 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,359 SECONDARY_SURFACE_DCC_EN, dcc->enable,360 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,361 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);362}363 364void hubp3_dmdata_set_attributes(365 struct hubp *hubp,366 const struct dc_dmdata_attributes *attr)367{368 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);369 370 /*always HW mode */371 REG_UPDATE(DMDATA_CNTL,372 DMDATA_MODE, 1);373 374 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */375 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);376 377 /* toggle DMDATA_UPDATED and set repeat and size */378 REG_UPDATE(DMDATA_CNTL,379 DMDATA_UPDATED, 0);380 REG_UPDATE_3(DMDATA_CNTL,381 DMDATA_UPDATED, 1,382 DMDATA_REPEAT, attr->dmdata_repeat,383 DMDATA_SIZE, attr->dmdata_size);384 385 /* set DMDATA address */386 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);387 REG_UPDATE(DMDATA_ADDRESS_HIGH,388 DMDATA_ADDRESS_HIGH, attr->address.high_part);389 390 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);391 392}393 394 395void hubp3_program_surface_config(396 struct hubp *hubp,397 enum surface_pixel_format format,398 union dc_tiling_info *tiling_info,399 struct plane_size *plane_size,400 enum dc_rotation_angle rotation,401 struct dc_plane_dcc_param *dcc,402 bool horizontal_mirror,403 unsigned int compat_level)404{405 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);406 407 hubp3_dcc_control_sienna_cichlid(hubp, dcc);408 hubp3_program_tiling(hubp2, tiling_info, format);409 hubp2_program_size(hubp, format, plane_size, dcc);410 hubp2_program_rotation(hubp, rotation, horizontal_mirror);411 hubp2_program_pixel_format(hubp, format);412}413 414static void hubp3_program_deadline(415 struct hubp *hubp,416 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,417 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)418{419 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);420 421 hubp2_program_deadline(hubp, dlg_attr, ttu_attr);422 REG_UPDATE(DCN_DMDATA_VM_CNTL,423 REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);424}425 426void hubp3_read_state(struct hubp *hubp)427{428 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);429 struct dcn_hubp_state *s = &hubp2->state;430 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;431 432 hubp2_read_state_common(hubp);433 434 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,435 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,436 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,437 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,438 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,439 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,440 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,441 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);442 443 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,444 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,445 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,446 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,447 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,448 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,449 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,450 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);451 452 if (REG(UCLK_PSTATE_FORCE))453 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);454 455 if (REG(DCHUBP_CNTL))456 s->hubp_cntl = REG_READ(DCHUBP_CNTL);457 458 if (REG(DCSURF_FLIP_CONTROL))459 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);460 461}462 463void hubp3_setup(464 struct hubp *hubp,465 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,466 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,467 struct _vcs_dpi_display_rq_regs_st *rq_regs,468 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)469{470 /* otg is locked when this func is called. Register are double buffered.471 * disable the requestors is not needed472 */473 hubp2_vready_at_or_After_vsync(hubp, pipe_dest);474 hubp21_program_requestor(hubp, rq_regs);475 hubp3_program_deadline(hubp, dlg_attr, ttu_attr);476}477 478void hubp3_init(struct hubp *hubp)479{480 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta481 // This is a chicken bit to enable the ECO fix.482 483 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);484 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;485 REG_WRITE(HUBPREQ_DEBUG, 1 << 26);486}487 488static struct hubp_funcs dcn30_hubp_funcs = {489 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,490 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,491 .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,492 .hubp_program_surface_config = hubp3_program_surface_config,493 .hubp_is_flip_pending = hubp2_is_flip_pending,494 .hubp_setup = hubp3_setup,495 .hubp_setup_interdependent = hubp2_setup_interdependent,496 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,497 .set_blank = hubp2_set_blank,498 .set_blank_regs = hubp2_set_blank_regs,499 .dcc_control = hubp3_dcc_control,500 .mem_program_viewport = min_set_viewport,501 .set_cursor_attributes = hubp2_cursor_set_attributes,502 .set_cursor_position = hubp2_cursor_set_position,503 .hubp_clk_cntl = hubp2_clk_cntl,504 .hubp_vtg_sel = hubp2_vtg_sel,505 .dmdata_set_attributes = hubp3_dmdata_set_attributes,506 .dmdata_load = hubp2_dmdata_load,507 .dmdata_status_done = hubp2_dmdata_status_done,508 .hubp_read_state = hubp3_read_state,509 .hubp_clear_underflow = hubp2_clear_underflow,510 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,511 .hubp_init = hubp3_init,512 .hubp_in_blank = hubp1_in_blank,513 .hubp_soft_reset = hubp1_soft_reset,514 .hubp_set_flip_int = hubp1_set_flip_int,515};516 517bool hubp3_construct(518 struct dcn20_hubp *hubp2,519 struct dc_context *ctx,520 uint32_t inst,521 const struct dcn_hubp2_registers *hubp_regs,522 const struct dcn_hubp2_shift *hubp_shift,523 const struct dcn_hubp2_mask *hubp_mask)524{525 hubp2->base.funcs = &dcn30_hubp_funcs;526 hubp2->base.ctx = ctx;527 hubp2->hubp_regs = hubp_regs;528 hubp2->hubp_shift = hubp_shift;529 hubp2->hubp_mask = hubp_mask;530 hubp2->base.inst = inst;531 hubp2->base.opp_id = OPP_ID_INVALID;532 hubp2->base.mpcc_id = 0xf;533 534 return true;535}536