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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "dm_services.h"27#include "dc.h"28#include "dc_bios_types.h"29#include "core_types.h"30#include "core_status.h"31#include "resource.h"32#include "dm_helpers.h"33#include "dce110_hwseq.h"34#include "dce110/dce110_timing_generator.h"35#include "dce/dce_hwseq.h"36#include "gpio_service_interface.h"37 38#include "dce110/dce110_compressor.h"39 40#include "bios/bios_parser_helper.h"41#include "timing_generator.h"42#include "mem_input.h"43#include "opp.h"44#include "ipp.h"45#include "transform.h"46#include "stream_encoder.h"47#include "link_encoder.h"48#include "link_enc_cfg.h"49#include "link_hwss.h"50#include "link.h"51#include "dccg.h"52#include "clock_source.h"53#include "clk_mgr.h"54#include "abm.h"55#include "audio.h"56#include "reg_helper.h"57#include "panel_cntl.h"58#include "dc_state_priv.h"59#include "dpcd_defs.h"60#include "dsc.h"61/* include DCE11 register header files */62#include "dce/dce_11_0_d.h"63#include "dce/dce_11_0_sh_mask.h"64#include "custom_float.h"65 66#include "atomfirmware.h"67 68#include "dcn10/dcn10_hwseq.h"69 70#define GAMMA_HW_POINTS_NUM 25671 72/*73 * All values are in milliseconds;74 * For eDP, after power-up/power/down,75 * 300/500 msec max. delay from LCDVCC to black video generation76 */77#define PANEL_POWER_UP_TIMEOUT 30078#define PANEL_POWER_DOWN_TIMEOUT 50079#define HPD_CHECK_INTERVAL 1080#define OLED_POST_T7_DELAY 10081#define OLED_PRE_T11_DELAY 15082 83#define CTX \84 hws->ctx85 86#define DC_LOGGER \87 ctx->logger88#define DC_LOGGER_INIT() \89 struct dc_context *ctx = dc->ctx90 91#define REG(reg)\92 hws->regs->reg93 94#undef FN95#define FN(reg_name, field_name) \96 hws->shifts->field_name, hws->masks->field_name97 98struct dce110_hw_seq_reg_offsets {99 uint32_t crtc;100};101 102static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {103{104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),105},106{107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),108},109{110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),111},112{113 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),114}115};116 117#define HW_REG_BLND(reg, id)\118 (reg + reg_offsets[id].blnd)119 120#define HW_REG_CRTC(reg, id)\121 (reg + reg_offsets[id].crtc)122 123#define MAX_WATERMARK 0xFFFF124#define SAFE_NBP_MARK 0x7FFF125 126/*******************************************************************************127 * Private definitions128 ******************************************************************************/129/***************************PIPE_CONTROL***********************************/130static void dce110_init_pte(struct dc_context *ctx)131{132 uint32_t addr;133 uint32_t value = 0;134 uint32_t chunk_int = 0;135 uint32_t chunk_mul = 0;136 137 addr = mmUNP_DVMM_PTE_CONTROL;138 value = dm_read_reg(ctx, addr);139 140 set_reg_field_value(141 value,142 0,143 DVMM_PTE_CONTROL,144 DVMM_USE_SINGLE_PTE);145 146 set_reg_field_value(147 value,148 1,149 DVMM_PTE_CONTROL,150 DVMM_PTE_BUFFER_MODE0);151 152 set_reg_field_value(153 value,154 1,155 DVMM_PTE_CONTROL,156 DVMM_PTE_BUFFER_MODE1);157 158 dm_write_reg(ctx, addr, value);159 160 addr = mmDVMM_PTE_REQ;161 value = dm_read_reg(ctx, addr);162 163 chunk_int = get_reg_field_value(164 value,165 DVMM_PTE_REQ,166 HFLIP_PTEREQ_PER_CHUNK_INT);167 168 chunk_mul = get_reg_field_value(169 value,170 DVMM_PTE_REQ,171 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);172 173 if (chunk_int != 0x4 || chunk_mul != 0x4) {174 175 set_reg_field_value(176 value,177 255,178 DVMM_PTE_REQ,179 MAX_PTEREQ_TO_ISSUE);180 181 set_reg_field_value(182 value,183 4,184 DVMM_PTE_REQ,185 HFLIP_PTEREQ_PER_CHUNK_INT);186 187 set_reg_field_value(188 value,189 4,190 DVMM_PTE_REQ,191 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);192 193 dm_write_reg(ctx, addr, value);194 }195}196/**************************************************************************/197 198static void enable_display_pipe_clock_gating(199 struct dc_context *ctx,200 bool clock_gating)201{202 /*TODO*/203}204 205static bool dce110_enable_display_power_gating(206 struct dc *dc,207 uint8_t controller_id,208 struct dc_bios *dcb,209 enum pipe_gating_control power_gating)210{211 enum bp_result bp_result = BP_RESULT_OK;212 enum bp_pipe_control_action cntl;213 struct dc_context *ctx = dc->ctx;214 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;215 216 if (power_gating == PIPE_GATING_CONTROL_INIT)217 cntl = ASIC_PIPE_INIT;218 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)219 cntl = ASIC_PIPE_ENABLE;220 else221 cntl = ASIC_PIPE_DISABLE;222 223 if (controller_id == underlay_idx)224 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;225 226 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {227 228 bp_result = dcb->funcs->enable_disp_power_gating(229 dcb, controller_id + 1, cntl);230 231 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2232 * by default when command table is called233 *234 * Bios parser accepts controller_id = 6 as indicative of235 * underlay pipe in dce110. But we do not support more236 * than 3.237 */238 if (controller_id < CONTROLLER_ID_MAX - 1)239 dm_write_reg(ctx,240 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),241 0);242 }243 244 if (power_gating != PIPE_GATING_CONTROL_ENABLE)245 dce110_init_pte(ctx);246 247 if (bp_result == BP_RESULT_OK)248 return true;249 else250 return false;251}252 253static void dce110_prescale_params(struct ipp_prescale_params *prescale_params,254 const struct dc_plane_state *plane_state)255{256 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;257 258 switch (plane_state->format) {259 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:260 prescale_params->scale = 0x2082;261 break;262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:263 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:264 prescale_params->scale = 0x2020;265 break;266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:268 prescale_params->scale = 0x2008;269 break;270 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:272 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:273 prescale_params->scale = 0x2000;274 break;275 default:276 ASSERT(false);277 break;278 }279}280 281static bool282dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,283 const struct dc_plane_state *plane_state)284{285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;286 const struct dc_transfer_func *tf = NULL;287 struct ipp_prescale_params prescale_params = { 0 };288 bool result = true;289 290 if (ipp == NULL)291 return false;292 293 tf = &plane_state->in_transfer_func;294 295 dce110_prescale_params(&prescale_params, plane_state);296 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);297 298 if (!plane_state->gamma_correction.is_identity &&299 dce_use_lut(plane_state->format))300 ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);301 302 if (tf->type == TF_TYPE_PREDEFINED) {303 switch (tf->tf) {304 case TRANSFER_FUNCTION_SRGB:305 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);306 break;307 case TRANSFER_FUNCTION_BT709:308 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);309 break;310 case TRANSFER_FUNCTION_LINEAR:311 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);312 break;313 case TRANSFER_FUNCTION_PQ:314 default:315 result = false;316 break;317 }318 } else if (tf->type == TF_TYPE_BYPASS) {319 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);320 } else {321 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/322 result = false;323 }324 325 return result;326}327 328static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,329 struct curve_points *arr_points,330 uint32_t hw_points_num)331{332 struct custom_float_format fmt;333 334 struct pwl_result_data *rgb = rgb_resulted;335 336 uint32_t i = 0;337 338 fmt.exponenta_bits = 6;339 fmt.mantissa_bits = 12;340 fmt.sign = true;341 342 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,343 &arr_points[0].custom_float_x)) {344 BREAK_TO_DEBUGGER();345 return false;346 }347 348 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,349 &arr_points[0].custom_float_offset)) {350 BREAK_TO_DEBUGGER();351 return false;352 }353 354 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,355 &arr_points[0].custom_float_slope)) {356 BREAK_TO_DEBUGGER();357 return false;358 }359 360 fmt.mantissa_bits = 10;361 fmt.sign = false;362 363 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,364 &arr_points[1].custom_float_x)) {365 BREAK_TO_DEBUGGER();366 return false;367 }368 369 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,370 &arr_points[1].custom_float_y)) {371 BREAK_TO_DEBUGGER();372 return false;373 }374 375 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,376 &arr_points[1].custom_float_slope)) {377 BREAK_TO_DEBUGGER();378 return false;379 }380 381 fmt.mantissa_bits = 12;382 fmt.sign = true;383 384 while (i != hw_points_num) {385 if (!convert_to_custom_float_format(rgb->red, &fmt,386 &rgb->red_reg)) {387 BREAK_TO_DEBUGGER();388 return false;389 }390 391 if (!convert_to_custom_float_format(rgb->green, &fmt,392 &rgb->green_reg)) {393 BREAK_TO_DEBUGGER();394 return false;395 }396 397 if (!convert_to_custom_float_format(rgb->blue, &fmt,398 &rgb->blue_reg)) {399 BREAK_TO_DEBUGGER();400 return false;401 }402 403 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,404 &rgb->delta_red_reg)) {405 BREAK_TO_DEBUGGER();406 return false;407 }408 409 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,410 &rgb->delta_green_reg)) {411 BREAK_TO_DEBUGGER();412 return false;413 }414 415 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,416 &rgb->delta_blue_reg)) {417 BREAK_TO_DEBUGGER();418 return false;419 }420 421 ++rgb;422 ++i;423 }424 425 return true;426}427 428#define MAX_LOW_POINT 25429#define NUMBER_REGIONS 16430#define NUMBER_SW_SEGMENTS 16431 432static bool433dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,434 struct pwl_params *regamma_params)435{436 struct curve_points *arr_points;437 struct pwl_result_data *rgb_resulted;438 struct pwl_result_data *rgb;439 struct pwl_result_data *rgb_plus_1;440 struct fixed31_32 y_r;441 struct fixed31_32 y_g;442 struct fixed31_32 y_b;443 struct fixed31_32 y1_min;444 struct fixed31_32 y3_max;445 446 int32_t region_start, region_end;447 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;448 449 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)450 return false;451 452 arr_points = regamma_params->arr_points;453 rgb_resulted = regamma_params->rgb_resulted;454 hw_points = 0;455 456 memset(regamma_params, 0, sizeof(struct pwl_params));457 458 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {459 /* 16 segments460 * segments are from 2^-11 to 2^5461 */462 region_start = -11;463 region_end = region_start + NUMBER_REGIONS;464 465 for (i = 0; i < NUMBER_REGIONS; i++)466 seg_distr[i] = 4;467 468 } else {469 /* 10 segments470 * segment is from 2^-10 to 2^1471 * We include an extra segment for range [2^0, 2^1). This is to472 * ensure that colors with normalized values of 1 don't miss the473 * LUT.474 */475 region_start = -10;476 region_end = 1;477 478 seg_distr[0] = 4;479 seg_distr[1] = 4;480 seg_distr[2] = 4;481 seg_distr[3] = 4;482 seg_distr[4] = 4;483 seg_distr[5] = 4;484 seg_distr[6] = 4;485 seg_distr[7] = 4;486 seg_distr[8] = 4;487 seg_distr[9] = 4;488 seg_distr[10] = 0;489 seg_distr[11] = -1;490 seg_distr[12] = -1;491 seg_distr[13] = -1;492 seg_distr[14] = -1;493 seg_distr[15] = -1;494 }495 496 for (k = 0; k < 16; k++) {497 if (seg_distr[k] != -1)498 hw_points += (1 << seg_distr[k]);499 }500 501 j = 0;502 for (k = 0; k < (region_end - region_start); k++) {503 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);504 start_index = (region_start + k + MAX_LOW_POINT) *505 NUMBER_SW_SEGMENTS;506 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;507 i += increment) {508 if (j == hw_points - 1)509 break;510 rgb_resulted[j].red = output_tf->tf_pts.red[i];511 rgb_resulted[j].green = output_tf->tf_pts.green[i];512 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];513 j++;514 }515 }516 517 /* last point */518 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;519 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];520 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];521 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];522 523 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),524 dc_fixpt_from_int(region_start));525 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),526 dc_fixpt_from_int(region_end));527 528 y_r = rgb_resulted[0].red;529 y_g = rgb_resulted[0].green;530 y_b = rgb_resulted[0].blue;531 532 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));533 534 arr_points[0].y = y1_min;535 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,536 arr_points[0].x);537 538 y_r = rgb_resulted[hw_points - 1].red;539 y_g = rgb_resulted[hw_points - 1].green;540 y_b = rgb_resulted[hw_points - 1].blue;541 542 /* see comment above, m_arrPoints[1].y should be the Y value for the543 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)544 */545 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));546 547 arr_points[1].y = y3_max;548 549 arr_points[1].slope = dc_fixpt_zero;550 551 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {552 /* for PQ, we want to have a straight line from last HW X point,553 * and the slope to be such that we hit 1.0 at 10000 nits.554 */555 const struct fixed31_32 end_value = dc_fixpt_from_int(125);556 557 arr_points[1].slope = dc_fixpt_div(558 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),559 dc_fixpt_sub(end_value, arr_points[1].x));560 }561 562 regamma_params->hw_points_num = hw_points;563 564 k = 0;565 for (i = 1; i < 16; i++) {566 if (seg_distr[k] != -1) {567 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];568 regamma_params->arr_curve_points[i].offset =569 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);570 }571 k++;572 }573 574 if (seg_distr[k] != -1)575 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];576 577 rgb = rgb_resulted;578 rgb_plus_1 = rgb_resulted + 1;579 580 i = 1;581 582 while (i != hw_points + 1) {583 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))584 rgb_plus_1->red = rgb->red;585 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))586 rgb_plus_1->green = rgb->green;587 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))588 rgb_plus_1->blue = rgb->blue;589 590 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);591 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);592 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);593 594 ++rgb_plus_1;595 ++rgb;596 ++i;597 }598 599 convert_to_custom_float(rgb_resulted, arr_points, hw_points);600 601 return true;602}603 604static bool605dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,606 const struct dc_stream_state *stream)607{608 struct transform *xfm = pipe_ctx->plane_res.xfm;609 610 xfm->funcs->opp_power_on_regamma_lut(xfm, true);611 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;612 613 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED &&614 stream->out_transfer_func.tf == TRANSFER_FUNCTION_SRGB) {615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);616 } else if (dce110_translate_regamma_to_hw_format(&stream->out_transfer_func,617 &xfm->regamma_params)) {618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);620 } else {621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);622 }623 624 xfm->funcs->opp_power_on_regamma_lut(xfm, false);625 626 return true;627}628 629void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)630{631 bool is_hdmi_tmds;632 bool is_dp;633 634 ASSERT(pipe_ctx->stream);635 636 if (pipe_ctx->stream_res.stream_enc == NULL)637 return; /* this is not root pipe */638 639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);641 642 if (!is_hdmi_tmds && !is_dp)643 return;644 645 if (is_hdmi_tmds)646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(647 pipe_ctx->stream_res.stream_enc,648 &pipe_ctx->stream_res.encoder_info_frame);649 else {650 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)651 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(652 pipe_ctx->stream_res.stream_enc,653 &pipe_ctx->stream_res.encoder_info_frame);654 655 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(656 pipe_ctx->stream_res.stream_enc,657 &pipe_ctx->stream_res.encoder_info_frame);658 }659}660 661void dce110_enable_stream(struct pipe_ctx *pipe_ctx)662{663 enum dc_lane_count lane_count =664 pipe_ctx->stream->link->cur_link_settings.lane_count;665 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;666 struct dc_link *link = pipe_ctx->stream->link;667 const struct dc *dc = link->dc;668 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);669 uint32_t active_total_with_borders;670 uint32_t early_control = 0;671 struct timing_generator *tg = pipe_ctx->stream_res.tg;672 673 link_hwss->setup_stream_encoder(pipe_ctx);674 675 dc->hwss.update_info_frame(pipe_ctx);676 677 /* enable early control to avoid corruption on DP monitor*/678 active_total_with_borders =679 timing->h_addressable680 + timing->h_border_left681 + timing->h_border_right;682 683 if (lane_count != 0)684 early_control = active_total_with_borders % lane_count;685 686 if (early_control == 0)687 early_control = lane_count;688 689 tg->funcs->set_early_control(tg, early_control);690}691 692static enum bp_result link_transmitter_control(693 struct dc_bios *bios,694 struct bp_transmitter_control *cntl)695{696 enum bp_result result;697 698 result = bios->funcs->transmitter_control(bios, cntl);699 700 return result;701}702 703/*704 * @brief705 * eDP only.706 */707void dce110_edp_wait_for_hpd_ready(708 struct dc_link *link,709 bool power_up)710{711 struct dc_context *ctx = link->ctx;712 struct graphics_object_id connector = link->link_enc->connector;713 struct gpio *hpd;714 bool edp_hpd_high = false;715 uint32_t time_elapsed = 0;716 uint32_t timeout = power_up ?717 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;718 719 if (dal_graphics_object_id_get_connector_id(connector)720 != CONNECTOR_ID_EDP) {721 BREAK_TO_DEBUGGER();722 return;723 }724 725 if (!power_up)726 /*727 * From KV, we will not HPD low after turning off VCC -728 * instead, we will check the SW timer in power_up().729 */730 return;731 732 /*733 * When we power on/off the eDP panel,734 * we need to wait until SENSE bit is high/low.735 */736 737 /* obtain HPD */738 /* TODO what to do with this? */739 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);740 741 if (!hpd) {742 BREAK_TO_DEBUGGER();743 return;744 }745 746 if (link->panel_config.pps.extra_t3_ms > 0) {747 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;748 749 msleep(extra_t3_in_ms);750 }751 752 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);753 754 /* wait until timeout or panel detected */755 756 do {757 uint32_t detected = 0;758 759 dal_gpio_get_value(hpd, &detected);760 761 if (!(detected ^ power_up)) {762 edp_hpd_high = true;763 break;764 }765 766 msleep(HPD_CHECK_INTERVAL);767 768 time_elapsed += HPD_CHECK_INTERVAL;769 } while (time_elapsed < timeout);770 771 dal_gpio_close(hpd);772 773 dal_gpio_destroy_irq(&hpd);774 775 /* ensure that the panel is detected */776 if (!edp_hpd_high)777 DC_LOG_DC("%s: wait timed out!\n", __func__);778}779 780void dce110_edp_power_control(781 struct dc_link *link,782 bool power_up)783{784 struct dc_context *ctx = link->ctx;785 struct bp_transmitter_control cntl = { 0 };786 enum bp_result bp_result;787 uint8_t pwrseq_instance;788 789 790 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)791 != CONNECTOR_ID_EDP) {792 BREAK_TO_DEBUGGER();793 return;794 }795 796 if (!link->panel_cntl)797 return;798 if (power_up !=799 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {800 801 unsigned long long current_ts = dm_get_timestamp(ctx);802 unsigned long long time_since_edp_poweroff_ms =803 div64_u64(dm_get_elapse_time_in_ns(804 ctx,805 current_ts,806 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);807 unsigned long long time_since_edp_poweron_ms =808 div64_u64(dm_get_elapse_time_in_ns(809 ctx,810 current_ts,811 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);812 DC_LOG_HW_RESUME_S3(813 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",814 __func__,815 power_up,816 current_ts,817 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),818 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),819 time_since_edp_poweroff_ms,820 time_since_edp_poweron_ms);821 822 /* Send VBIOS command to prompt eDP panel power */823 if (power_up) {824 /* edp requires a min of 500ms from LCDVDD off to on */825 unsigned long long remaining_min_edp_poweroff_time_ms = 500;826 827 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */828 if (link->local_sink != NULL)829 remaining_min_edp_poweroff_time_ms +=830 link->panel_config.pps.extra_t12_ms;831 832 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */833 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {834 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)835 remaining_min_edp_poweroff_time_ms =836 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;837 else838 remaining_min_edp_poweroff_time_ms = 0;839 }840 841 if (remaining_min_edp_poweroff_time_ms) {842 DC_LOG_HW_RESUME_S3(843 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",844 __func__, remaining_min_edp_poweroff_time_ms);845 msleep(remaining_min_edp_poweroff_time_ms);846 DC_LOG_HW_RESUME_S3(847 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",848 __func__, remaining_min_edp_poweroff_time_ms);849 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",850 __func__, remaining_min_edp_poweroff_time_ms);851 } else {852 DC_LOG_HW_RESUME_S3(853 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",854 __func__, remaining_min_edp_poweroff_time_ms);855 }856 }857 858 DC_LOG_HW_RESUME_S3(859 "%s: BEGIN: Panel Power action: %s\n",860 __func__, (power_up ? "On":"Off"));861 862 cntl.action = power_up ?863 TRANSMITTER_CONTROL_POWER_ON :864 TRANSMITTER_CONTROL_POWER_OFF;865 cntl.transmitter = link->link_enc->transmitter;866 cntl.connector_obj_id = link->link_enc->connector;867 cntl.coherent = false;868 cntl.lanes_number = LANE_COUNT_FOUR;869 cntl.hpd_sel = link->link_enc->hpd_source;870 pwrseq_instance = link->panel_cntl->pwrseq_inst;871 872 if (ctx->dc->ctx->dmub_srv &&873 ctx->dc->debug.dmub_command_table) {874 875 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {876 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,877 LVTMA_CONTROL_POWER_ON,878 pwrseq_instance, link->link_powered_externally);879 } else {880 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,881 LVTMA_CONTROL_POWER_OFF,882 pwrseq_instance, link->link_powered_externally);883 }884 }885 886 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);887 888 DC_LOG_HW_RESUME_S3(889 "%s: END: Panel Power action: %s bp_result=%u\n",890 __func__, (power_up ? "On":"Off"),891 bp_result);892 893 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);894 895 DC_LOG_HW_RESUME_S3(896 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",897 __func__,898 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),899 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));900 901 if (bp_result != BP_RESULT_OK)902 DC_LOG_ERROR(903 "%s: Panel Power bp_result: %d\n",904 __func__, bp_result);905 } else {906 DC_LOG_HW_RESUME_S3(907 "%s: Skipping Panel Power action: %s\n",908 __func__, (power_up ? "On":"Off"));909 }910}911 912void dce110_edp_wait_for_T12(913 struct dc_link *link)914{915 struct dc_context *ctx = link->ctx;916 917 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)918 != CONNECTOR_ID_EDP) {919 BREAK_TO_DEBUGGER();920 return;921 }922 923 if (!link->panel_cntl)924 return;925 926 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&927 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {928 unsigned int t12_duration = 500; // Default T12 as per spec929 unsigned long long current_ts = dm_get_timestamp(ctx);930 unsigned long long time_since_edp_poweroff_ms =931 div64_u64(dm_get_elapse_time_in_ns(932 ctx,933 current_ts,934 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);935 936 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12937 938 if (time_since_edp_poweroff_ms < t12_duration)939 msleep(t12_duration - time_since_edp_poweroff_ms);940 }941}942/*todo: cloned in stream enc, fix*/943/*944 * @brief945 * eDP only. Control the backlight of the eDP panel946 */947void dce110_edp_backlight_control(948 struct dc_link *link,949 bool enable)950{951 struct dc_context *ctx = link->ctx;952 struct bp_transmitter_control cntl = { 0 };953 uint8_t pwrseq_instance = 0;954 unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;955 unsigned int post_T7_delay = OLED_POST_T7_DELAY;956 957 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)958 != CONNECTOR_ID_EDP) {959 BREAK_TO_DEBUGGER();960 return;961 }962 963 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||964 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||965 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {966 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);967 968 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {969 DC_LOG_HW_RESUME_S3(970 "%s: panel already powered up/off. Do nothing.\n",971 __func__);972 return;973 }974 }975 976 /* Send VBIOS command to control eDP panel backlight */977 978 DC_LOG_HW_RESUME_S3(979 "%s: backlight action: %s\n",980 __func__, (enable ? "On":"Off"));981 982 cntl.action = enable ?983 TRANSMITTER_CONTROL_BACKLIGHT_ON :984 TRANSMITTER_CONTROL_BACKLIGHT_OFF;985 986 /*cntl.engine_id = ctx->engine;*/987 cntl.transmitter = link->link_enc->transmitter;988 cntl.connector_obj_id = link->link_enc->connector;989 /*todo: unhardcode*/990 cntl.lanes_number = LANE_COUNT_FOUR;991 cntl.hpd_sel = link->link_enc->hpd_source;992 cntl.signal = SIGNAL_TYPE_EDP;993 994 /* For eDP, the following delays might need to be considered995 * after link training completed:996 * idle period - min. accounts for required BS-Idle pattern,997 * max. allows for source frame synchronization);998 * 50 msec max. delay from valid video data from source999 * to video on dislpay or backlight enable.1000 *1001 * Disable the delay for now.1002 * Enable it in the future if necessary.1003 */1004 /* dc_service_sleep_in_milliseconds(50); */1005 /*edp 1.2*/1006 if (link->panel_cntl)1007 pwrseq_instance = link->panel_cntl->pwrseq_inst;1008 1009 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {1010 if (!link->dc->config.edp_no_power_sequencing)1011 /*1012 * Sometimes, DP receiver chip power-controlled externally by an1013 * Embedded Controller could be treated and used as eDP,1014 * if it drives mobile display. In this case,1015 * we shouldn't be doing power-sequencing, hence we can skip1016 * waiting for T7-ready.1017 */1018 ctx->dc->link_srv->edp_receiver_ready_T7(link);1019 else1020 DC_LOG_DC("edp_receiver_ready_T7 skipped\n");1021 }1022 1023 /* Setting link_powered_externally will bypass delays in the backlight1024 * as they are not required if the link is being powered by a different1025 * source.1026 */1027 if (ctx->dc->ctx->dmub_srv &&1028 ctx->dc->debug.dmub_command_table) {1029 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)1030 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,1031 LVTMA_CONTROL_LCD_BLON,1032 pwrseq_instance, link->link_powered_externally);1033 else1034 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,1035 LVTMA_CONTROL_LCD_BLOFF,1036 pwrseq_instance, link->link_powered_externally);1037 }1038 1039 link_transmitter_control(ctx->dc_bios, &cntl);1040 1041 if (enable && link->dpcd_sink_ext_caps.bits.oled &&1042 !link->dc->config.edp_no_power_sequencing) {1043 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;1044 msleep(post_T7_delay);1045 }1046 1047 if (link->dpcd_sink_ext_caps.bits.oled ||1048 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||1049 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)1050 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);1051 1052 /*edp 1.2*/1053 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {1054 if (!link->dc->config.edp_no_power_sequencing)1055 /*1056 * Sometimes, DP receiver chip power-controlled externally by an1057 * Embedded Controller could be treated and used as eDP,1058 * if it drives mobile display. In this case,1059 * we shouldn't be doing power-sequencing, hence we can skip1060 * waiting for T9-ready.1061 */1062 ctx->dc->link_srv->edp_add_delay_for_T9(link);1063 else1064 DC_LOG_DC("edp_receiver_ready_T9 skipped\n");1065 }1066 1067 if (!enable && link->dpcd_sink_ext_caps.bits.oled) {1068 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;1069 msleep(pre_T11_delay);1070 }1071}1072 1073void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)1074{1075 /* notify audio driver for audio modes of monitor */1076 struct dc *dc;1077 struct clk_mgr *clk_mgr;1078 unsigned int i, num_audio = 1;1079 const struct link_hwss *link_hwss;1080 1081 if (!pipe_ctx->stream)1082 return;1083 1084 dc = pipe_ctx->stream->ctx->dc;1085 clk_mgr = dc->clk_mgr;1086 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);1087 1088 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)1089 return;1090 1091 if (pipe_ctx->stream_res.audio) {1092 for (i = 0; i < MAX_PIPES; i++) {1093 /*current_state not updated yet*/1094 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)1095 num_audio++;1096 }1097 1098 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);1099 1100 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)1101 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/1102 clk_mgr->funcs->enable_pme_wa(clk_mgr);1103 1104 link_hwss->enable_audio_packet(pipe_ctx);1105 1106 if (pipe_ctx->stream_res.audio)1107 pipe_ctx->stream_res.audio->enabled = true;1108 }1109}1110 1111void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)1112{1113 struct dc *dc;1114 struct clk_mgr *clk_mgr;1115 const struct link_hwss *link_hwss;1116 1117 if (!pipe_ctx || !pipe_ctx->stream)1118 return;1119 1120 dc = pipe_ctx->stream->ctx->dc;1121 clk_mgr = dc->clk_mgr;1122 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);1123 1124 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)1125 return;1126 1127 link_hwss->disable_audio_packet(pipe_ctx);1128 1129 if (pipe_ctx->stream_res.audio) {1130 pipe_ctx->stream_res.audio->enabled = false;1131 1132 if (clk_mgr->funcs->enable_pme_wa)1133 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/1134 clk_mgr->funcs->enable_pme_wa(clk_mgr);1135 1136 /* TODO: notify audio driver for if audio modes list changed1137 * add audio mode list change flag */1138 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,1139 * stream->stream_engine_id);1140 */1141 }1142}1143 1144void dce110_disable_stream(struct pipe_ctx *pipe_ctx)1145{1146 struct dc_stream_state *stream = pipe_ctx->stream;1147 struct dc_link *link = stream->link;1148 struct dc *dc = pipe_ctx->stream->ctx->dc;1149 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);1150 struct dccg *dccg = dc->res_pool->dccg;1151 struct timing_generator *tg = pipe_ctx->stream_res.tg;1152 struct dtbclk_dto_params dto_params = {0};1153 int dp_hpo_inst;1154 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);1155 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;1156 1157 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {1158 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(1159 pipe_ctx->stream_res.stream_enc);1160 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(1161 pipe_ctx->stream_res.stream_enc);1162 }1163 1164 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {1165 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(1166 pipe_ctx->stream_res.hpo_dp_stream_enc);1167 } else if (dc_is_dp_signal(pipe_ctx->stream->signal))1168 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(1169 pipe_ctx->stream_res.stream_enc);1170 1171 dc->hwss.disable_audio_stream(pipe_ctx);1172 1173 link_hwss->reset_stream_encoder(pipe_ctx);1174 1175 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {1176 dto_params.otg_inst = tg->inst;1177 dto_params.timing = &pipe_ctx->stream->timing;1178 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;1179 if (dccg) {1180 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);1181 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);1182 if (dccg && dccg->funcs->set_dtbclk_dto)1183 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);1184 }1185 } else if (dccg && dccg->funcs->disable_symclk_se) {1186 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,1187 link_enc->transmitter - TRANSMITTER_UNIPHY_A);1188 }1189}1190 1191void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,1192 struct dc_link_settings *link_settings)1193{1194 struct encoder_unblank_param params = { { 0 } };1195 struct dc_stream_state *stream = pipe_ctx->stream;1196 struct dc_link *link = stream->link;1197 struct dce_hwseq *hws = link->dc->hwseq;1198 1199 /* only 3 items below are used by unblank */1200 params.timing = pipe_ctx->stream->timing;1201 params.link_settings.link_rate = link_settings->link_rate;1202 1203 if (dc_is_dp_signal(pipe_ctx->stream->signal))1204 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);1205 1206 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {1207 hws->funcs.edp_backlight_control(link, true);1208 }1209}1210 1211void dce110_blank_stream(struct pipe_ctx *pipe_ctx)1212{1213 struct dc_stream_state *stream = pipe_ctx->stream;1214 struct dc_link *link = stream->link;1215 struct dce_hwseq *hws = link->dc->hwseq;1216 1217 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {1218 if (!link->skip_implict_edp_power_control)1219 hws->funcs.edp_backlight_control(link, false);1220 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);1221 }1222 1223 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {1224 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */1225 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(1226 pipe_ctx->stream_res.hpo_dp_stream_enc);1227 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {1228 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);1229 1230 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {1231 /*1232 * After output is idle pattern some sinks need time to recognize the stream1233 * has changed or they enter protection state and hang.1234 */1235 msleep(60);1236 }1237 }1238 1239 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&1240 !link->dc->config.edp_no_power_sequencing) {1241 /*1242 * Sometimes, DP receiver chip power-controlled externally by an1243 * Embedded Controller could be treated and used as eDP,1244 * if it drives mobile display. In this case,1245 * we shouldn't be doing power-sequencing, hence we can skip1246 * waiting for T9-ready.1247 */1248 link->dc->link_srv->edp_receiver_ready_T9(link);1249 }1250 1251}1252 1253 1254void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)1255{1256 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)1257 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);1258}1259 1260static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)1261{1262 switch (crtc_id) {1263 case CONTROLLER_ID_D0:1264 return DTO_SOURCE_ID0;1265 case CONTROLLER_ID_D1:1266 return DTO_SOURCE_ID1;1267 case CONTROLLER_ID_D2:1268 return DTO_SOURCE_ID2;1269 case CONTROLLER_ID_D3:1270 return DTO_SOURCE_ID3;1271 case CONTROLLER_ID_D4:1272 return DTO_SOURCE_ID4;1273 case CONTROLLER_ID_D5:1274 return DTO_SOURCE_ID5;1275 default:1276 return DTO_SOURCE_UNKNOWN;1277 }1278}1279 1280static void populate_audio_dp_link_info(1281 const struct pipe_ctx *pipe_ctx,1282 struct audio_dp_link_info *dp_link_info)1283{1284 const struct dc_stream_state *stream = pipe_ctx->stream;1285 const struct dc_link *link = stream->link;1286 struct fixed31_32 link_bw_kbps;1287 1288 dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format(1289 &pipe_ctx->link_config.dp_link_settings);1290 dp_link_info->is_mst = (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST);1291 dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;1292 dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;1293 1294 link_bw_kbps = dc_fixpt_from_int(dc_link_bandwidth_kbps(link,1295 &pipe_ctx->link_config.dp_link_settings));1296 1297 /* For audio stream calculations, the video stream should not include FEC or SSC1298 * in order to get the most pessimistic values.1299 */1300 if (dp_link_info->encoding == DP_8b_10b_ENCODING &&1301 link->dc->link_srv->dp_is_fec_supported(link)) {1302 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,1303 dc_fixpt_from_fraction(100, DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100));1304 } else if (dp_link_info->encoding == DP_128b_132b_ENCODING) {1305 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,1306 dc_fixpt_from_fraction(10000, 9975)); /* 99.75% SSC overhead*/1307 }1308 1309 dp_link_info->link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps);1310 1311 /* Calculates hblank_min_symbol_width for 128b/132b1312 * Corresponding HBLANK_MIN_SYMBOL_WIDTH register is calculated as:1313 * floor(h_blank * bits_per_pixel / 128)1314 */1315 if (dp_link_info->encoding == DP_128b_132b_ENCODING) {1316 struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;1317 1318 uint32_t h_active = crtc_timing->h_addressable + crtc_timing->h_border_left1319 + crtc_timing->h_border_right;1320 uint32_t h_blank = crtc_timing->h_total - h_active;1321 1322 uint32_t bpp;1323 1324 if (crtc_timing->flags.DSC) {1325 bpp = crtc_timing->dsc_cfg.bits_per_pixel;1326 } else {1327 /* When the timing is using DSC, dsc_cfg.bits_per_pixel is in 16th bits.1328 * The bpp in this path is scaled to 16th bits so the final calculation1329 * is correct for both cases.1330 */1331 bpp = 16;1332 switch (crtc_timing->display_color_depth) {1333 case COLOR_DEPTH_666:1334 bpp *= 18;1335 break;1336 case COLOR_DEPTH_888:1337 bpp *= 24;1338 break;1339 case COLOR_DEPTH_101010:1340 bpp *= 30;1341 break;1342 case COLOR_DEPTH_121212:1343 bpp *= 36;1344 break;1345 default:1346 bpp = 0;1347 break;1348 }1349 1350 switch (crtc_timing->pixel_encoding) {1351 case PIXEL_ENCODING_YCBCR422:1352 bpp = bpp * 2 / 3;1353 break;1354 case PIXEL_ENCODING_YCBCR420:1355 bpp /= 2;1356 break;1357 default:1358 break;1359 }1360 }1361 1362 /* Min symbol width = floor(h_blank * (bpp/16) / 128) */1363 dp_link_info->hblank_min_symbol_width = dc_fixpt_floor(1364 dc_fixpt_div(dc_fixpt_from_int(h_blank * bpp),1365 dc_fixpt_from_int(128 / 16)));1366 1367 } else {1368 dp_link_info->hblank_min_symbol_width = 0;1369 }1370}1371 1372static void build_audio_output(1373 struct dc_state *state,1374 const struct pipe_ctx *pipe_ctx,1375 struct audio_output *audio_output)1376{1377 const struct dc_stream_state *stream = pipe_ctx->stream;1378 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;1379 1380 audio_output->signal = pipe_ctx->stream->signal;1381 1382 /* audio_crtc_info */1383 1384 audio_output->crtc_info.h_total =1385 stream->timing.h_total;1386 1387 /*1388 * Audio packets are sent during actual CRTC blank physical signal, we1389 * need to specify actual active signal portion1390 */1391 audio_output->crtc_info.h_active =1392 stream->timing.h_addressable1393 + stream->timing.h_border_left1394 + stream->timing.h_border_right;1395 1396 audio_output->crtc_info.v_active =1397 stream->timing.v_addressable1398 + stream->timing.v_border_top1399 + stream->timing.v_border_bottom;1400 1401 audio_output->crtc_info.pixel_repetition = 1;1402 1403 audio_output->crtc_info.interlaced =1404 stream->timing.flags.INTERLACE;1405 1406 audio_output->crtc_info.refresh_rate =1407 (stream->timing.pix_clk_100hz*100)/1408 (stream->timing.h_total*stream->timing.v_total);1409 1410 audio_output->crtc_info.color_depth =1411 stream->timing.display_color_depth;1412 1413 audio_output->crtc_info.requested_pixel_clock_100Hz =1414 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;1415 1416 audio_output->crtc_info.calculated_pixel_clock_100Hz =1417 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;1418 1419 audio_output->crtc_info.pixel_encoding =1420 stream->timing.pixel_encoding;1421 1422 audio_output->crtc_info.dsc_bits_per_pixel =1423 stream->timing.dsc_cfg.bits_per_pixel;1424 1425 audio_output->crtc_info.dsc_num_slices =1426 stream->timing.dsc_cfg.num_slices_h;1427 1428/*for HDMI, audio ACR is with deep color ratio factor*/1429 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&1430 audio_output->crtc_info.requested_pixel_clock_100Hz ==1431 (stream->timing.pix_clk_100hz)) {1432 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {1433 audio_output->crtc_info.requested_pixel_clock_100Hz =1434 audio_output->crtc_info.requested_pixel_clock_100Hz/2;1435 audio_output->crtc_info.calculated_pixel_clock_100Hz =1436 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;1437 1438 }1439 }1440 1441 if (state->clk_mgr &&1442 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||1443 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {1444 audio_output->pll_info.audio_dto_source_clock_in_khz =1445 state->clk_mgr->funcs->get_dp_ref_clk_frequency(1446 state->clk_mgr);1447 }1448 1449 audio_output->pll_info.feed_back_divider =1450 pipe_ctx->pll_settings.feedback_divider;1451 1452 audio_output->pll_info.dto_source =1453 translate_to_dto_source(1454 pipe_ctx->stream_res.tg->inst + 1);1455 1456 /* TODO hard code to enable for now. Need get from stream */1457 audio_output->pll_info.ss_enabled = true;1458 1459 audio_output->pll_info.ss_percentage =1460 pipe_ctx->pll_settings.ss_percentage;1461 1462 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {1463 populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);1464 }1465}1466 1467static void program_scaler(const struct dc *dc,1468 const struct pipe_ctx *pipe_ctx)1469{1470 struct tg_color color = {0};1471 1472 /* TOFPGA */1473 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)1474 return;1475 1476 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)1477 get_surface_visual_confirm_color(pipe_ctx, &color);1478 else1479 color_space_to_black_color(dc,1480 pipe_ctx->stream->output_color_space,1481 &color);1482 1483 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(1484 pipe_ctx->plane_res.xfm,1485 pipe_ctx->plane_res.scl_data.lb_params.depth,1486 &pipe_ctx->stream->bit_depth_params);1487 1488 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {1489 /*1490 * The way 420 is packed, 2 channels carry Y component, 1 channel1491 * alternate between Cb and Cr, so both channels need the pixel1492 * value for Y1493 */1494 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)1495 color.color_r_cr = color.color_g_y;1496 1497 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(1498 pipe_ctx->stream_res.tg,1499 &color);1500 }1501 1502 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,1503 &pipe_ctx->plane_res.scl_data);1504}1505 1506static enum dc_status dce110_enable_stream_timing(1507 struct pipe_ctx *pipe_ctx,1508 struct dc_state *context,1509 struct dc *dc)1510{1511 struct dc_stream_state *stream = pipe_ctx->stream;1512 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.1513 pipe_ctx[pipe_ctx->pipe_idx];1514 struct tg_color black_color = {0};1515 1516 if (!pipe_ctx_old->stream) {1517 1518 /* program blank color */1519 color_space_to_black_color(dc,1520 stream->output_color_space, &black_color);1521 pipe_ctx->stream_res.tg->funcs->set_blank_color(1522 pipe_ctx->stream_res.tg,1523 &black_color);1524 1525 /*1526 * Must blank CRTC after disabling power gating and before any1527 * programming, otherwise CRTC will be hung in bad state1528 */1529 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);1530 1531 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(1532 pipe_ctx->clock_source,1533 &pipe_ctx->stream_res.pix_clk_params,1534 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),1535 &pipe_ctx->pll_settings)) {1536 BREAK_TO_DEBUGGER();1537 return DC_ERROR_UNEXPECTED;1538 }1539 1540 if (dc_is_hdmi_tmds_signal(stream->signal)) {1541 stream->link->phy_state.symclk_ref_cnts.otg = 1;1542 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)1543 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;1544 else1545 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;1546 }1547 1548 pipe_ctx->stream_res.tg->funcs->program_timing(1549 pipe_ctx->stream_res.tg,1550 &stream->timing,1551 0,1552 0,1553 0,1554 0,1555 0,1556 pipe_ctx->stream->signal,1557 true);1558 }1559 1560 if (!pipe_ctx_old->stream) {1561 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(1562 pipe_ctx->stream_res.tg)) {1563 BREAK_TO_DEBUGGER();1564 return DC_ERROR_UNEXPECTED;1565 }1566 }1567 1568 return DC_OK;1569}1570 1571enum dc_status dce110_apply_single_controller_ctx_to_hw(1572 struct pipe_ctx *pipe_ctx,1573 struct dc_state *context,1574 struct dc *dc)1575{1576 struct dc_stream_state *stream = pipe_ctx->stream;1577 struct dc_link *link = stream->link;1578 struct drr_params params = {0};1579 unsigned int event_triggers = 0;1580 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;1581 struct dce_hwseq *hws = dc->hwseq;1582 const struct link_hwss *link_hwss = get_link_hwss(1583 link, &pipe_ctx->link_res);1584 1585 1586 if (hws->funcs.disable_stream_gating) {1587 hws->funcs.disable_stream_gating(dc, pipe_ctx);1588 }1589 1590 if (pipe_ctx->stream_res.audio != NULL) {1591 struct audio_output audio_output = {0};1592 1593 build_audio_output(context, pipe_ctx, &audio_output);1594 1595 link_hwss->setup_audio_output(pipe_ctx, &audio_output,1596 pipe_ctx->stream_res.audio->inst);1597 1598 pipe_ctx->stream_res.audio->funcs->az_configure(1599 pipe_ctx->stream_res.audio,1600 pipe_ctx->stream->signal,1601 &audio_output.crtc_info,1602 &pipe_ctx->stream->audio_info,1603 &audio_output.dp_link_info);1604 1605 if (dc->config.disable_hbr_audio_dp2)1606 if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&1607 dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))1608 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);1609 }1610 1611 /* make sure no pipes syncd to the pipe being enabled */1612 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)1613 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);1614 1615 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(1616 pipe_ctx->stream_res.opp,1617 &stream->bit_depth_params,1618 &stream->clamping);1619 1620 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(1621 pipe_ctx->stream_res.opp,1622 COLOR_SPACE_YCBCR601,1623 stream->timing.display_color_depth,1624 stream->signal);1625 1626 while (odm_pipe) {1627 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(1628 odm_pipe->stream_res.opp,1629 COLOR_SPACE_YCBCR601,1630 stream->timing.display_color_depth,1631 stream->signal);1632 1633 odm_pipe->stream_res.opp->funcs->opp_program_fmt(1634 odm_pipe->stream_res.opp,1635 &stream->bit_depth_params,1636 &stream->clamping);1637 odm_pipe = odm_pipe->next_odm_pipe;1638 }1639 1640 /* DCN3.1 FPGA Workaround1641 * Need to enable HPO DP Stream Encoder before setting OTG master enable.1642 * To do so, move calling function enable_stream_timing to only be done AFTER calling1643 * function core_link_enable_stream1644 */1645 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))1646 /* */1647 /* Do not touch stream timing on seamless boot optimization. */1648 if (!pipe_ctx->stream->apply_seamless_boot_optimization)1649 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);1650 1651 if (hws->funcs.setup_vupdate_interrupt)1652 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);1653 1654 params.vertical_total_min = stream->adjust.v_total_min;1655 params.vertical_total_max = stream->adjust.v_total_max;1656 if (pipe_ctx->stream_res.tg->funcs->set_drr)1657 pipe_ctx->stream_res.tg->funcs->set_drr(1658 pipe_ctx->stream_res.tg, ¶ms);1659 1660 // DRR should set trigger event to monitor surface update event1661 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)1662 event_triggers = 0x80;1663 /* Event triggers and num frames initialized for DRR, but can be1664 * later updated for PSR use. Note DRR trigger events are generated1665 * regardless of whether num frames met.1666 */1667 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)1668 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(1669 pipe_ctx->stream_res.tg, event_triggers, 2);1670 1671 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))1672 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(1673 pipe_ctx->stream_res.stream_enc,1674 pipe_ctx->stream_res.tg->inst);1675 1676 if (dc_is_dp_signal(pipe_ctx->stream->signal))1677 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);1678 1679 if (!stream->dpms_off)1680 dc->link_srv->set_dpms_on(context, pipe_ctx);1681 1682 /* DCN3.1 FPGA Workaround1683 * Need to enable HPO DP Stream Encoder before setting OTG master enable.1684 * To do so, move calling function enable_stream_timing to only be done AFTER calling1685 * function core_link_enable_stream1686 */1687 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {1688 if (!pipe_ctx->stream->apply_seamless_boot_optimization)1689 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);1690 }1691 1692 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;1693 1694 /* Phantom and main stream share the same link (because the stream1695 * is constructed with the same sink). Make sure not to override1696 * and link programming on the main.1697 */1698 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {1699 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;1700 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;1701 }1702 return DC_OK;1703}1704 1705/******************************************************************************/1706 1707static void power_down_encoders(struct dc *dc)1708{1709 int i;1710 1711 for (i = 0; i < dc->link_count; i++) {1712 enum signal_type signal = dc->links[i]->connector_signal;1713 1714 dc->link_srv->blank_dp_stream(dc->links[i], false);1715 1716 if (signal != SIGNAL_TYPE_EDP)1717 signal = SIGNAL_TYPE_NONE;1718 1719 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)1720 dc->links[i]->link_enc->funcs->disable_output(1721 dc->links[i]->link_enc, signal);1722 1723 dc->links[i]->link_status.link_active = false;1724 memset(&dc->links[i]->cur_link_settings, 0,1725 sizeof(dc->links[i]->cur_link_settings));1726 }1727}1728 1729static void power_down_controllers(struct dc *dc)1730{1731 int i;1732 1733 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {1734 dc->res_pool->timing_generators[i]->funcs->disable_crtc(1735 dc->res_pool->timing_generators[i]);1736 }1737}1738 1739static void power_down_clock_sources(struct dc *dc)1740{1741 int i;1742 1743 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(1744 dc->res_pool->dp_clock_source) == false)1745 dm_error("Failed to power down pll! (dp clk src)\n");1746 1747 for (i = 0; i < dc->res_pool->clk_src_count; i++) {1748 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(1749 dc->res_pool->clock_sources[i]) == false)1750 dm_error("Failed to power down pll! (clk src index=%d)\n", i);1751 }1752}1753 1754static void power_down_all_hw_blocks(struct dc *dc)1755{1756 power_down_encoders(dc);1757 1758 power_down_controllers(dc);1759 1760 power_down_clock_sources(dc);1761 1762 if (dc->fbc_compressor)1763 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);1764}1765 1766static void disable_vga_and_power_gate_all_controllers(1767 struct dc *dc)1768{1769 int i;1770 struct timing_generator *tg;1771 struct dc_context *ctx = dc->ctx;1772 1773 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {1774 tg = dc->res_pool->timing_generators[i];1775 1776 if (tg->funcs->disable_vga)1777 tg->funcs->disable_vga(tg);1778 }1779 for (i = 0; i < dc->res_pool->pipe_count; i++) {1780 /* Enable CLOCK gating for each pipe BEFORE controller1781 * powergating. */1782 enable_display_pipe_clock_gating(ctx,1783 true);1784 1785 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;1786 dc->hwss.disable_plane(dc, dc->current_state,1787 &dc->current_state->res_ctx.pipe_ctx[i]);1788 }1789}1790 1791 1792static void get_edp_streams(struct dc_state *context,1793 struct dc_stream_state **edp_streams,1794 int *edp_stream_num)1795{1796 int i;1797 1798 *edp_stream_num = 0;1799 for (i = 0; i < context->stream_count; i++) {1800 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {1801 edp_streams[*edp_stream_num] = context->streams[i];1802 if (++(*edp_stream_num) == MAX_NUM_EDP)1803 return;1804 }1805 }1806}1807 1808static void get_edp_links_with_sink(1809 struct dc *dc,1810 struct dc_link **edp_links_with_sink,1811 int *edp_with_sink_num)1812{1813 int i;1814 1815 /* check if there is an eDP panel not in use */1816 *edp_with_sink_num = 0;1817 for (i = 0; i < dc->link_count; i++) {1818 if (dc->links[i]->local_sink &&1819 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {1820 edp_links_with_sink[*edp_with_sink_num] = dc->links[i];1821 if (++(*edp_with_sink_num) == MAX_NUM_EDP)1822 return;1823 }1824 }1825}1826 1827static void clean_up_dsc_blocks(struct dc *dc)1828{1829 struct display_stream_compressor *dsc = NULL;1830 struct timing_generator *tg = NULL;1831 struct stream_encoder *se = NULL;1832 struct dccg *dccg = dc->res_pool->dccg;1833 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;1834 int i;1835 1836 if (dc->ctx->dce_version != DCN_VERSION_3_5 &&1837 dc->ctx->dce_version != DCN_VERSION_3_51)1838 return;1839 1840 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {1841 struct dcn_dsc_state s = {0};1842 1843 dsc = dc->res_pool->dscs[i];1844 dsc->funcs->dsc_read_state(dsc, &s);1845 if (s.dsc_fw_en) {1846 /* disable DSC in OPTC */1847 if (i < dc->res_pool->timing_generator_count) {1848 tg = dc->res_pool->timing_generators[i];1849 tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);1850 }1851 /* disable DSC in stream encoder */1852 if (i < dc->res_pool->stream_enc_count) {1853 se = dc->res_pool->stream_enc[i];1854 se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);1855 se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);1856 }1857 /* disable DSC block */1858 if (dccg->funcs->set_ref_dscclk)1859 dccg->funcs->set_ref_dscclk(dccg, dsc->inst);1860 dsc->funcs->dsc_disable(dsc);1861 1862 /* power down DSC */1863 if (pg_cntl != NULL)1864 pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);1865 }1866 }1867}1868 1869/*1870 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:1871 * 1. Power down all DC HW blocks1872 * 2. Disable VGA engine on all controllers1873 * 3. Enable power gating for controller1874 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)1875 */1876void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)1877{1878 struct dc_link *edp_links_with_sink[MAX_NUM_EDP];1879 struct dc_link *edp_links[MAX_NUM_EDP];1880 struct dc_stream_state *edp_streams[MAX_NUM_EDP];1881 struct dc_link *edp_link_with_sink = NULL;1882 struct dc_link *edp_link = NULL;1883 struct pipe_ctx *pipe_ctx = NULL;1884 struct dce_hwseq *hws = dc->hwseq;1885 int edp_with_sink_num;1886 int edp_num;1887 int edp_stream_num;1888 int i;1889 bool can_apply_edp_fast_boot = false;1890 bool can_apply_seamless_boot = false;1891 bool keep_edp_vdd_on = false;1892 struct dc_bios *dcb = dc->ctx->dc_bios;1893 DC_LOGGER_INIT();1894 1895 1896 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);1897 dc_get_edp_links(dc, edp_links, &edp_num);1898 1899 if (hws->funcs.init_pipes)1900 hws->funcs.init_pipes(dc, context);1901 1902 get_edp_streams(context, edp_streams, &edp_stream_num);1903 1904 // Check fastboot support, disable on DCE8 because of blank screens1905 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&1906 dc->ctx->dce_version != DCE_VERSION_8_1 &&1907 dc->ctx->dce_version != DCE_VERSION_8_3) {1908 for (i = 0; i < edp_num; i++) {1909 edp_link = edp_links[i];1910 if (edp_link != edp_streams[0]->link)1911 continue;1912 // enable fastboot if backend is enabled on eDP1913 if (edp_link->link_enc->funcs->is_dig_enabled &&1914 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&1915 edp_link->link_status.link_active) {1916 struct dc_stream_state *edp_stream = edp_streams[0];1917 1918 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,1919 edp_stream->sink, &edp_stream->timing);1920 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;1921 if (can_apply_edp_fast_boot) {1922 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot Enable\n");1923 1924 // Vbios & Driver support different pixel rate div policy.1925 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);1926 if (pipe_ctx &&1927 hws->funcs.is_dp_dig_pixel_rate_div_policy &&1928 hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {1929 // Get Vbios div factor from register1930 dc->res_pool->dccg->funcs->get_pixel_rate_div(1931 dc->res_pool->dccg,1932 pipe_ctx->stream_res.tg->inst,1933 &pipe_ctx->pixel_rate_divider.div_factor1,1934 &pipe_ctx->pixel_rate_divider.div_factor2);1935 1936 // VBios doesn't support pixel rate div, so force it.1937 // If VBios supports it, we check it from reigster or other flags.1938 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;1939 }1940 }1941 break;1942 }1943 }1944 // We are trying to enable eDP, don't power down VDD1945 if (can_apply_edp_fast_boot)1946 keep_edp_vdd_on = true;1947 }1948 1949 // Check seamless boot support1950 for (i = 0; i < context->stream_count; i++) {1951 if (context->streams[i]->apply_seamless_boot_optimization) {1952 can_apply_seamless_boot = true;1953 break;1954 }1955 }1956 1957 /* eDP should not have stream in resume from S4 and so even with VBios post1958 * it should get turned off1959 */1960 if (edp_with_sink_num)1961 edp_link_with_sink = edp_links_with_sink[0];1962 1963 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {1964 if (edp_link_with_sink && !keep_edp_vdd_on) {1965 /*turn off backlight before DP_blank and encoder powered down*/1966 hws->funcs.edp_backlight_control(edp_link_with_sink, false);1967 }1968 /*resume from S3, no vbios posting, no need to power down again*/1969 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))1970 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);1971 1972 power_down_all_hw_blocks(dc);1973 1974 /* DSC could be enabled on eDP during VBIOS post.1975 * To clean up dsc blocks if eDP is in link but not active.1976 */1977 if (edp_link_with_sink && (edp_stream_num == 0))1978 clean_up_dsc_blocks(dc);1979 1980 disable_vga_and_power_gate_all_controllers(dc);1981 if (edp_link_with_sink && !keep_edp_vdd_on)1982 dc->hwss.edp_power_control(edp_link_with_sink, false);1983 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))1984 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);1985 }1986 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);1987}1988 1989static uint32_t compute_pstate_blackout_duration(1990 struct bw_fixed blackout_duration,1991 const struct dc_stream_state *stream)1992{1993 uint32_t total_dest_line_time_ns;1994 uint32_t pstate_blackout_duration_ns;1995 1996 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;1997 1998 total_dest_line_time_ns = 1000000UL *1999 (stream->timing.h_total * 10) /2000 stream->timing.pix_clk_100hz +2001 pstate_blackout_duration_ns;2002 2003 return total_dest_line_time_ns;2004}2005 2006static void dce110_set_displaymarks(2007 const struct dc *dc,2008 struct dc_state *context)2009{2010 uint8_t i, num_pipes;2011 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;2012 2013 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {2014 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2015 uint32_t total_dest_line_time_ns;2016 2017 if (pipe_ctx->stream == NULL)2018 continue;2019 2020 total_dest_line_time_ns = compute_pstate_blackout_duration(2021 dc->bw_vbios->blackout_duration, pipe_ctx->stream);2022 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(2023 pipe_ctx->plane_res.mi,2024 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],2025 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],2026 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],2027 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],2028 total_dest_line_time_ns);2029 if (i == underlay_idx) {2030 num_pipes++;2031 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(2032 pipe_ctx->plane_res.mi,2033 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],2034 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],2035 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],2036 total_dest_line_time_ns);2037 }2038 num_pipes++;2039 }2040}2041 2042void dce110_set_safe_displaymarks(2043 struct resource_context *res_ctx,2044 const struct resource_pool *pool)2045{2046 int i;2047 int underlay_idx = pool->underlay_pipe_index;2048 struct dce_watermarks max_marks = {2049 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };2050 struct dce_watermarks nbp_marks = {2051 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };2052 struct dce_watermarks min_marks = { 0, 0, 0, 0};2053 2054 for (i = 0; i < MAX_PIPES; i++) {2055 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)2056 continue;2057 2058 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(2059 res_ctx->pipe_ctx[i].plane_res.mi,2060 nbp_marks,2061 max_marks,2062 min_marks,2063 max_marks,2064 MAX_WATERMARK);2065 2066 if (i == underlay_idx)2067 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(2068 res_ctx->pipe_ctx[i].plane_res.mi,2069 nbp_marks,2070 max_marks,2071 max_marks,2072 MAX_WATERMARK);2073 2074 }2075}2076 2077/*******************************************************************************2078 * Public functions2079 ******************************************************************************/2080 2081static void set_drr(struct pipe_ctx **pipe_ctx,2082 int num_pipes, struct dc_crtc_timing_adjust adjust)2083{2084 int i = 0;2085 struct drr_params params = {0};2086 // DRR should set trigger event to monitor surface update event2087 unsigned int event_triggers = 0x80;2088 // Note DRR trigger events are generated regardless of whether num frames met.2089 unsigned int num_frames = 2;2090 2091 params.vertical_total_max = adjust.v_total_max;2092 params.vertical_total_min = adjust.v_total_min;2093 2094 /* TODO: If multiple pipes are to be supported, you need2095 * some GSL stuff. Static screen triggers may be programmed differently2096 * as well.2097 */2098 for (i = 0; i < num_pipes; i++) {2099 /* dc_state_destruct() might null the stream resources, so fetch tg2100 * here first to avoid a race condition. The lifetime of the pointee2101 * itself (the timing_generator object) is not a problem here.2102 */2103 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;2104 2105 if ((tg != NULL) && tg->funcs) {2106 if (tg->funcs->set_drr)2107 tg->funcs->set_drr(tg, ¶ms);2108 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)2109 if (tg->funcs->set_static_screen_control)2110 tg->funcs->set_static_screen_control(2111 tg, event_triggers, num_frames);2112 }2113 }2114}2115 2116static void get_position(struct pipe_ctx **pipe_ctx,2117 int num_pipes,2118 struct crtc_position *position)2119{2120 int i = 0;2121 2122 /* TODO: handle pipes > 12123 */2124 for (i = 0; i < num_pipes; i++)2125 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);2126}2127 2128static void set_static_screen_control(struct pipe_ctx **pipe_ctx,2129 int num_pipes, const struct dc_static_screen_params *params)2130{2131 unsigned int i;2132 unsigned int triggers = 0;2133 2134 if (params->triggers.overlay_update)2135 triggers |= 0x100;2136 if (params->triggers.surface_update)2137 triggers |= 0x80;2138 if (params->triggers.cursor_update)2139 triggers |= 0x2;2140 if (params->triggers.force_trigger)2141 triggers |= 0x1;2142 2143 if (num_pipes) {2144 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;2145 2146 if (dc->fbc_compressor)2147 triggers |= 0x84;2148 }2149 2150 for (i = 0; i < num_pipes; i++)2151 pipe_ctx[i]->stream_res.tg->funcs->2152 set_static_screen_control(pipe_ctx[i]->stream_res.tg,2153 triggers, params->num_frames);2154}2155 2156/*2157 * Check if FBC can be enabled2158 */2159static bool should_enable_fbc(struct dc *dc,2160 struct dc_state *context,2161 uint32_t *pipe_idx)2162{2163 uint32_t i;2164 struct pipe_ctx *pipe_ctx = NULL;2165 struct resource_context *res_ctx = &context->res_ctx;2166 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;2167 2168 2169 ASSERT(dc->fbc_compressor);2170 2171 /* FBC memory should be allocated */2172 if (!dc->ctx->fbc_gpu_addr)2173 return false;2174 2175 /* Only supports single display */2176 if (context->stream_count != 1)2177 return false;2178 2179 for (i = 0; i < dc->res_pool->pipe_count; i++) {2180 if (res_ctx->pipe_ctx[i].stream) {2181 2182 pipe_ctx = &res_ctx->pipe_ctx[i];2183 2184 /* fbc not applicable on underlay pipe */2185 if (pipe_ctx->pipe_idx != underlay_idx) {2186 *pipe_idx = i;2187 break;2188 }2189 }2190 }2191 2192 if (i == dc->res_pool->pipe_count)2193 return false;2194 2195 if (!pipe_ctx->stream->link)2196 return false;2197 2198 /* Only supports eDP */2199 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)2200 return false;2201 2202 /* PSR should not be enabled */2203 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)2204 return false;2205 2206 /* Replay should not be enabled */2207 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)2208 return false;2209 2210 /* Nothing to compress */2211 if (!pipe_ctx->plane_state)2212 return false;2213 2214 /* Only for non-linear tiling */2215 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)2216 return false;2217 2218 return true;2219}2220 2221/*2222 * Enable FBC2223 */2224static void enable_fbc(2225 struct dc *dc,2226 struct dc_state *context)2227{2228 uint32_t pipe_idx = 0;2229 2230 if (should_enable_fbc(dc, context, &pipe_idx)) {2231 /* Program GRPH COMPRESSED ADDRESS and PITCH */2232 struct compr_addr_and_pitch_params params = {0, 0, 0};2233 struct compressor *compr = dc->fbc_compressor;2234 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];2235 2236 params.source_view_width = pipe_ctx->stream->timing.h_addressable;2237 params.source_view_height = pipe_ctx->stream->timing.v_addressable;2238 params.inst = pipe_ctx->stream_res.tg->inst;2239 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;2240 2241 compr->funcs->surface_address_and_pitch(compr, ¶ms);2242 compr->funcs->set_fbc_invalidation_triggers(compr, 1);2243 2244 compr->funcs->enable_fbc(compr, ¶ms);2245 }2246}2247 2248static void dce110_reset_hw_ctx_wrap(2249 struct dc *dc,2250 struct dc_state *context)2251{2252 int i;2253 2254 /* Reset old context */2255 /* look up the targets that have been removed since last commit */2256 for (i = 0; i < MAX_PIPES; i++) {2257 struct pipe_ctx *pipe_ctx_old =2258 &dc->current_state->res_ctx.pipe_ctx[i];2259 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2260 2261 /* Note: We need to disable output if clock sources change,2262 * since bios does optimization and doesn't apply if changing2263 * PHY when not already disabled.2264 */2265 2266 /* Skip underlay pipe since it will be handled in commit surface*/2267 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)2268 continue;2269 2270 if (!pipe_ctx->stream ||2271 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {2272 struct clock_source *old_clk = pipe_ctx_old->clock_source;2273 2274 /* Disable if new stream is null. O/w, if stream is2275 * disabled already, no need to disable again.2276 */2277 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {2278 dc->link_srv->set_dpms_off(pipe_ctx_old);2279 2280 /* free acquired resources*/2281 if (pipe_ctx_old->stream_res.audio) {2282 /*disable az_endpoint*/2283 pipe_ctx_old->stream_res.audio->funcs->2284 az_disable(pipe_ctx_old->stream_res.audio);2285 2286 /*free audio*/2287 if (dc->caps.dynamic_audio == true) {2288 /*we have to dynamic arbitrate the audio endpoints*/2289 /*we free the resource, need reset is_audio_acquired*/2290 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,2291 pipe_ctx_old->stream_res.audio, false);2292 pipe_ctx_old->stream_res.audio = NULL;2293 }2294 }2295 }2296 2297 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);2298 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {2299 dm_error("DC: failed to blank crtc!\n");2300 BREAK_TO_DEBUGGER();2301 }2302 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);2303 if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))2304 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;2305 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(2306 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);2307 2308 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,2309 dc->res_pool,2310 old_clk))2311 old_clk->funcs->cs_power_down(old_clk);2312 2313 dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old);2314 2315 pipe_ctx_old->stream = NULL;2316 }2317 }2318}2319 2320static void dce110_setup_audio_dto(2321 struct dc *dc,2322 struct dc_state *context)2323{2324 unsigned int i;2325 2326 /* program audio wall clock. use HDMI as clock source if HDMI2327 * audio active. Otherwise, use DP as clock source2328 * first, loop to find any HDMI audio, if not, loop find DP audio2329 */2330 /* Setup audio rate clock source */2331 /* Issue:2332 * Audio lag happened on DP monitor when unplug a HDMI monitor2333 *2334 * Cause:2335 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL2336 * is set to either dto0 or dto1, audio should work fine.2337 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,2338 * set to dto0 will cause audio lag.2339 *2340 * Solution:2341 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,2342 * find first available pipe with audio, setup audio wall DTO per topology2343 * instead of per pipe.2344 */2345 for (i = 0; i < dc->res_pool->pipe_count; i++) {2346 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2347 2348 if (pipe_ctx->stream == NULL)2349 continue;2350 2351 if (pipe_ctx->top_pipe)2352 continue;2353 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)2354 continue;2355 if (pipe_ctx->stream_res.audio != NULL) {2356 struct audio_output audio_output;2357 2358 build_audio_output(context, pipe_ctx, &audio_output);2359 2360 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {2361 struct dtbclk_dto_params dto_params = {0};2362 2363 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(2364 dc->res_pool->dccg, &dto_params);2365 2366 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(2367 pipe_ctx->stream_res.audio,2368 pipe_ctx->stream->signal,2369 &audio_output.crtc_info,2370 &audio_output.pll_info);2371 } else2372 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(2373 pipe_ctx->stream_res.audio,2374 pipe_ctx->stream->signal,2375 &audio_output.crtc_info,2376 &audio_output.pll_info);2377 break;2378 }2379 }2380 2381 /* no HDMI audio is found, try DP audio */2382 if (i == dc->res_pool->pipe_count) {2383 for (i = 0; i < dc->res_pool->pipe_count; i++) {2384 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2385 2386 if (pipe_ctx->stream == NULL)2387 continue;2388 2389 if (pipe_ctx->top_pipe)2390 continue;2391 2392 if (!dc_is_dp_signal(pipe_ctx->stream->signal))2393 continue;2394 2395 if (pipe_ctx->stream_res.audio != NULL) {2396 struct audio_output audio_output = {0};2397 2398 build_audio_output(context, pipe_ctx, &audio_output);2399 2400 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(2401 pipe_ctx->stream_res.audio,2402 pipe_ctx->stream->signal,2403 &audio_output.crtc_info,2404 &audio_output.pll_info);2405 break;2406 }2407 }2408 }2409}2410 2411enum dc_status dce110_apply_ctx_to_hw(2412 struct dc *dc,2413 struct dc_state *context)2414{2415 struct dce_hwseq *hws = dc->hwseq;2416 struct dc_bios *dcb = dc->ctx->dc_bios;2417 enum dc_status status;2418 int i;2419 bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);2420 bool is_hpo_acquired = resource_is_hpo_acquired(context);2421 2422 /* reset syncd pipes from disabled pipes */2423 if (dc->config.use_pipe_ctx_sync_logic)2424 reset_syncd_pipes_from_disabled_pipes(dc, context);2425 2426 /* Reset old context */2427 /* look up the targets that have been removed since last commit */2428 hws->funcs.reset_hw_ctx_wrap(dc, context);2429 2430 /* Skip applying if no targets */2431 if (context->stream_count <= 0)2432 return DC_OK;2433 2434 /* Apply new context */2435 dcb->funcs->set_scratch_critical_state(dcb, true);2436 2437 /* below is for real asic only */2438 for (i = 0; i < dc->res_pool->pipe_count; i++) {2439 struct pipe_ctx *pipe_ctx_old =2440 &dc->current_state->res_ctx.pipe_ctx[i];2441 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2442 2443 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)2444 continue;2445 2446 if (pipe_ctx->stream == pipe_ctx_old->stream) {2447 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)2448 dce_crtc_switch_to_clk_src(dc->hwseq,2449 pipe_ctx->clock_source, i);2450 continue;2451 }2452 2453 hws->funcs.enable_display_power_gating(2454 dc, i, dc->ctx->dc_bios,2455 PIPE_GATING_CONTROL_DISABLE);2456 }2457 2458 if (dc->fbc_compressor)2459 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);2460 2461 dce110_setup_audio_dto(dc, context);2462 2463 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {2464 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);2465 }2466 2467 for (i = 0; i < dc->res_pool->pipe_count; i++) {2468 struct pipe_ctx *pipe_ctx_old =2469 &dc->current_state->res_ctx.pipe_ctx[i];2470 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];2471 2472 if (pipe_ctx->stream == NULL)2473 continue;2474 2475 if (pipe_ctx->stream == pipe_ctx_old->stream &&2476 pipe_ctx->stream->link->link_state_valid) {2477 continue;2478 }2479 2480 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))2481 continue;2482 2483 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)2484 continue;2485 2486 status = dce110_apply_single_controller_ctx_to_hw(2487 pipe_ctx,2488 context,2489 dc);2490 2491 if (DC_OK != status)2492 return status;2493 2494#ifdef CONFIG_DRM_AMD_DC_FP2495 if (hws->funcs.resync_fifo_dccg_dio)2496 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);2497#endif2498 }2499 2500 if (dc->fbc_compressor)2501 enable_fbc(dc, dc->current_state);2502 2503 dcb->funcs->set_scratch_critical_state(dcb, false);2504 2505 return DC_OK;2506}2507 2508/*******************************************************************************2509 * Front End programming2510 ******************************************************************************/2511static void set_default_colors(struct pipe_ctx *pipe_ctx)2512{2513 struct default_adjustment default_adjust = { 0 };2514 2515 default_adjust.force_hw_default = false;2516 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;2517 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;2518 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;2519 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;2520 2521 /* display color depth */2522 default_adjust.color_depth =2523 pipe_ctx->stream->timing.display_color_depth;2524 2525 /* Lb color depth */2526 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;2527 2528 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(2529 pipe_ctx->plane_res.xfm, &default_adjust);2530}2531 2532 2533/*******************************************************************************2534 * In order to turn on/off specific surface we will program2535 * Blender + CRTC2536 *2537 * In case that we have two surfaces and they have a different visibility2538 * we can't turn off the CRTC since it will turn off the entire display2539 *2540 * |----------------------------------------------- |2541 * |bottom pipe|curr pipe | | |2542 * |Surface |Surface | Blender | CRCT |2543 * |visibility |visibility | Configuration| |2544 * |------------------------------------------------|2545 * | off | off | CURRENT_PIPE | blank |2546 * | off | on | CURRENT_PIPE | unblank |2547 * | on | off | OTHER_PIPE | unblank |2548 * | on | on | BLENDING | unblank |2549 * -------------------------------------------------|2550 *2551 ******************************************************************************/2552static void program_surface_visibility(const struct dc *dc,2553 struct pipe_ctx *pipe_ctx)2554{2555 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;2556 bool blank_target = false;2557 2558 if (pipe_ctx->bottom_pipe) {2559 2560 /* For now we are supporting only two pipes */2561 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);2562 2563 if (pipe_ctx->bottom_pipe->plane_state->visible) {2564 if (pipe_ctx->plane_state->visible)2565 blender_mode = BLND_MODE_BLENDING;2566 else2567 blender_mode = BLND_MODE_OTHER_PIPE;2568 2569 } else if (!pipe_ctx->plane_state->visible)2570 blank_target = true;2571 2572 } else if (!pipe_ctx->plane_state->visible)2573 blank_target = true;2574 2575 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);2576 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);2577 2578}2579 2580static void program_gamut_remap(struct pipe_ctx *pipe_ctx)2581{2582 int i = 0;2583 struct xfm_grph_csc_adjustment adjust;2584 memset(&adjust, 0, sizeof(adjust));2585 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;2586 2587 2588 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {2589 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;2590 2591 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)2592 adjust.temperature_matrix[i] =2593 pipe_ctx->stream->gamut_remap_matrix.matrix[i];2594 }2595 2596 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);2597}2598static void update_plane_addr(const struct dc *dc,2599 struct pipe_ctx *pipe_ctx)2600{2601 struct dc_plane_state *plane_state = pipe_ctx->plane_state;2602 2603 if (plane_state == NULL)2604 return;2605 2606 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(2607 pipe_ctx->plane_res.mi,2608 &plane_state->address,2609 plane_state->flip_immediate);2610 2611 plane_state->status.requested_address = plane_state->address;2612}2613 2614static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)2615{2616 struct dc_plane_state *plane_state = pipe_ctx->plane_state;2617 2618 if (plane_state == NULL)2619 return;2620 2621 plane_state->status.is_flip_pending =2622 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(2623 pipe_ctx->plane_res.mi);2624 2625 if (plane_state->status.is_flip_pending && !plane_state->visible)2626 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;2627 2628 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;2629 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&2630 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {2631 plane_state->status.is_right_eye =\2632 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);2633 }2634}2635 2636void dce110_power_down(struct dc *dc)2637{2638 power_down_all_hw_blocks(dc);2639 disable_vga_and_power_gate_all_controllers(dc);2640}2641 2642static bool wait_for_reset_trigger_to_occur(2643 struct dc_context *dc_ctx,2644 struct timing_generator *tg)2645{2646 struct dc_context *ctx = dc_ctx;2647 bool rc = false;2648 2649 /* To avoid endless loop we wait at most2650 * frames_to_wait_on_triggered_reset frames for the reset to occur. */2651 const uint32_t frames_to_wait_on_triggered_reset = 10;2652 uint32_t i;2653 2654 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {2655 2656 if (!tg->funcs->is_counter_moving(tg)) {2657 DC_ERROR("TG counter is not moving!\n");2658 break;2659 }2660 2661 if (tg->funcs->did_triggered_reset_occur(tg)) {2662 rc = true;2663 /* usually occurs at i=1 */2664 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",2665 i);2666 break;2667 }2668 2669 /* Wait for one frame. */2670 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);2671 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);2672 }2673 2674 if (false == rc)2675 DC_ERROR("GSL: Timeout on reset trigger!\n");2676 2677 return rc;2678}2679 2680/* Enable timing synchronization for a group of Timing Generators. */2681static void dce110_enable_timing_synchronization(2682 struct dc *dc,2683 struct dc_state *state,2684 int group_index,2685 int group_size,2686 struct pipe_ctx *grouped_pipes[])2687{2688 struct dc_context *dc_ctx = dc->ctx;2689 struct dcp_gsl_params gsl_params = { 0 };2690 int i;2691 DC_LOGGER_INIT();2692 2693 DC_SYNC_INFO("GSL: Setting-up...\n");2694 2695 /* Designate a single TG in the group as a master.2696 * Since HW doesn't care which one, we always assign2697 * the 1st one in the group. */2698 gsl_params.gsl_group = 0;2699 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;2700 2701 for (i = 0; i < group_size; i++)2702 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(2703 grouped_pipes[i]->stream_res.tg, &gsl_params);2704 2705 /* Reset slave controllers on master VSync */2706 DC_SYNC_INFO("GSL: enabling trigger-reset\n");2707 2708 for (i = 1 /* skip the master */; i < group_size; i++)2709 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(2710 grouped_pipes[i]->stream_res.tg,2711 gsl_params.gsl_group);2712 2713 for (i = 1 /* skip the master */; i < group_size; i++) {2714 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");2715 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);2716 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(2717 grouped_pipes[i]->stream_res.tg);2718 }2719 2720 /* GSL Vblank synchronization is a one time sync mechanism, assumption2721 * is that the sync'ed displays will not drift out of sync over time*/2722 DC_SYNC_INFO("GSL: Restoring register states.\n");2723 for (i = 0; i < group_size; i++)2724 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);2725 2726 DC_SYNC_INFO("GSL: Set-up complete.\n");2727}2728 2729static void dce110_enable_per_frame_crtc_position_reset(2730 struct dc *dc,2731 int group_size,2732 struct pipe_ctx *grouped_pipes[])2733{2734 struct dc_context *dc_ctx = dc->ctx;2735 struct dcp_gsl_params gsl_params = { 0 };2736 int i;2737 DC_LOGGER_INIT();2738 2739 gsl_params.gsl_group = 0;2740 gsl_params.gsl_master = 0;2741 2742 for (i = 0; i < group_size; i++)2743 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(2744 grouped_pipes[i]->stream_res.tg, &gsl_params);2745 2746 DC_SYNC_INFO("GSL: enabling trigger-reset\n");2747 2748 for (i = 1; i < group_size; i++)2749 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(2750 grouped_pipes[i]->stream_res.tg,2751 gsl_params.gsl_master,2752 &grouped_pipes[i]->stream->triggered_crtc_reset);2753 2754 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");2755 for (i = 1; i < group_size; i++)2756 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);2757 2758 for (i = 0; i < group_size; i++)2759 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);2760 2761}2762 2763static void init_pipes(struct dc *dc, struct dc_state *context)2764{2765 // Do nothing2766}2767 2768static void init_hw(struct dc *dc)2769{2770 int i;2771 struct dc_bios *bp;2772 struct transform *xfm;2773 struct abm *abm;2774 struct dmcu *dmcu;2775 struct dce_hwseq *hws = dc->hwseq;2776 uint32_t backlight = MAX_BACKLIGHT_LEVEL;2777 uint32_t user_level = MAX_BACKLIGHT_LEVEL;2778 2779 bp = dc->ctx->dc_bios;2780 for (i = 0; i < dc->res_pool->pipe_count; i++) {2781 xfm = dc->res_pool->transforms[i];2782 xfm->funcs->transform_reset(xfm);2783 2784 hws->funcs.enable_display_power_gating(2785 dc, i, bp,2786 PIPE_GATING_CONTROL_INIT);2787 hws->funcs.enable_display_power_gating(2788 dc, i, bp,2789 PIPE_GATING_CONTROL_DISABLE);2790 hws->funcs.enable_display_pipe_clock_gating(2791 dc->ctx,2792 true);2793 }2794 2795 dce_clock_gating_power_up(dc->hwseq, false);2796 /***************************************/2797 2798 for (i = 0; i < dc->link_count; i++) {2799 /****************************************/2800 /* Power up AND update implementation according to the2801 * required signal (which may be different from the2802 * default signal on connector). */2803 struct dc_link *link = dc->links[i];2804 2805 link->link_enc->funcs->hw_init(link->link_enc);2806 }2807 2808 for (i = 0; i < dc->res_pool->pipe_count; i++) {2809 struct timing_generator *tg = dc->res_pool->timing_generators[i];2810 2811 tg->funcs->disable_vga(tg);2812 2813 /* Blank controller using driver code instead of2814 * command table. */2815 tg->funcs->set_blank(tg, true);2816 hwss_wait_for_blank_complete(tg);2817 }2818 2819 for (i = 0; i < dc->res_pool->audio_count; i++) {2820 struct audio *audio = dc->res_pool->audios[i];2821 audio->funcs->hw_init(audio);2822 }2823 2824 for (i = 0; i < dc->link_count; i++) {2825 struct dc_link *link = dc->links[i];2826 2827 if (link->panel_cntl) {2828 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);2829 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;2830 }2831 }2832 2833 abm = dc->res_pool->abm;2834 if (abm != NULL)2835 abm->funcs->abm_init(abm, backlight, user_level);2836 2837 dmcu = dc->res_pool->dmcu;2838 if (dmcu != NULL && abm != NULL)2839 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);2840 2841 if (dc->fbc_compressor)2842 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);2843 2844}2845 2846 2847void dce110_prepare_bandwidth(2848 struct dc *dc,2849 struct dc_state *context)2850{2851 struct clk_mgr *dccg = dc->clk_mgr;2852 2853 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);2854 if (dccg)2855 dccg->funcs->update_clocks(2856 dccg,2857 context,2858 false);2859}2860 2861void dce110_optimize_bandwidth(2862 struct dc *dc,2863 struct dc_state *context)2864{2865 struct clk_mgr *dccg = dc->clk_mgr;2866 2867 dce110_set_displaymarks(dc, context);2868 2869 if (dccg)2870 dccg->funcs->update_clocks(2871 dccg,2872 context,2873 true);2874}2875 2876static void dce110_program_front_end_for_pipe(2877 struct dc *dc, struct pipe_ctx *pipe_ctx)2878{2879 struct mem_input *mi = pipe_ctx->plane_res.mi;2880 struct dc_plane_state *plane_state = pipe_ctx->plane_state;2881 struct xfm_grph_csc_adjustment adjust;2882 struct out_csc_color_matrix tbl_entry;2883 unsigned int i;2884 struct dce_hwseq *hws = dc->hwseq;2885 2886 memset(&tbl_entry, 0, sizeof(tbl_entry));2887 2888 memset(&adjust, 0, sizeof(adjust));2889 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;2890 2891 dce_enable_fe_clock(dc->hwseq, mi->inst, true);2892 2893 set_default_colors(pipe_ctx);2894 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment2895 == true) {2896 tbl_entry.color_space =2897 pipe_ctx->stream->output_color_space;2898 2899 for (i = 0; i < 12; i++)2900 tbl_entry.regval[i] =2901 pipe_ctx->stream->csc_color_matrix.matrix[i];2902 2903 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment2904 (pipe_ctx->plane_res.xfm, &tbl_entry);2905 }2906 2907 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {2908 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;2909 2910 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)2911 adjust.temperature_matrix[i] =2912 pipe_ctx->stream->gamut_remap_matrix.matrix[i];2913 }2914 2915 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);2916 2917 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;2918 2919 program_scaler(dc, pipe_ctx);2920 2921 mi->funcs->mem_input_program_surface_config(2922 mi,2923 plane_state->format,2924 &plane_state->tiling_info,2925 &plane_state->plane_size,2926 plane_state->rotation,2927 NULL,2928 false);2929 if (mi->funcs->set_blank)2930 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);2931 2932 if (dc->config.gpu_vm_support)2933 mi->funcs->mem_input_program_pte_vm(2934 pipe_ctx->plane_res.mi,2935 plane_state->format,2936 &plane_state->tiling_info,2937 plane_state->rotation);2938 2939 /* Moved programming gamma from dc to hwss */2940 if (pipe_ctx->plane_state->update_flags.bits.full_update ||2941 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||2942 pipe_ctx->plane_state->update_flags.bits.gamma_change)2943 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);2944 2945 if (pipe_ctx->plane_state->update_flags.bits.full_update)2946 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);2947 2948 DC_LOG_SURFACE(2949 "Pipe:%d %p: addr hi:0x%x, "2950 "addr low:0x%x, "2951 "src: %d, %d, %d,"2952 " %d; dst: %d, %d, %d, %d;"2953 "clip: %d, %d, %d, %d\n",2954 pipe_ctx->pipe_idx,2955 (void *) pipe_ctx->plane_state,2956 pipe_ctx->plane_state->address.grph.addr.high_part,2957 pipe_ctx->plane_state->address.grph.addr.low_part,2958 pipe_ctx->plane_state->src_rect.x,2959 pipe_ctx->plane_state->src_rect.y,2960 pipe_ctx->plane_state->src_rect.width,2961 pipe_ctx->plane_state->src_rect.height,2962 pipe_ctx->plane_state->dst_rect.x,2963 pipe_ctx->plane_state->dst_rect.y,2964 pipe_ctx->plane_state->dst_rect.width,2965 pipe_ctx->plane_state->dst_rect.height,2966 pipe_ctx->plane_state->clip_rect.x,2967 pipe_ctx->plane_state->clip_rect.y,2968 pipe_ctx->plane_state->clip_rect.width,2969 pipe_ctx->plane_state->clip_rect.height);2970 2971 DC_LOG_SURFACE(2972 "Pipe %d: width, height, x, y\n"2973 "viewport:%d, %d, %d, %d\n"2974 "recout: %d, %d, %d, %d\n",2975 pipe_ctx->pipe_idx,2976 pipe_ctx->plane_res.scl_data.viewport.width,2977 pipe_ctx->plane_res.scl_data.viewport.height,2978 pipe_ctx->plane_res.scl_data.viewport.x,2979 pipe_ctx->plane_res.scl_data.viewport.y,2980 pipe_ctx->plane_res.scl_data.recout.width,2981 pipe_ctx->plane_res.scl_data.recout.height,2982 pipe_ctx->plane_res.scl_data.recout.x,2983 pipe_ctx->plane_res.scl_data.recout.y);2984}2985 2986static void dce110_apply_ctx_for_surface(2987 struct dc *dc,2988 const struct dc_stream_state *stream,2989 int num_planes,2990 struct dc_state *context)2991{2992 int i;2993 2994 if (num_planes == 0)2995 return;2996 2997 if (dc->fbc_compressor)2998 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);2999 3000 for (i = 0; i < dc->res_pool->pipe_count; i++) {3001 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];3002 3003 if (pipe_ctx->stream != stream)3004 continue;3005 3006 /* Need to allocate mem before program front end for Fiji */3007 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(3008 pipe_ctx->plane_res.mi,3009 pipe_ctx->stream->timing.h_total,3010 pipe_ctx->stream->timing.v_total,3011 pipe_ctx->stream->timing.pix_clk_100hz / 10,3012 context->stream_count);3013 3014 dce110_program_front_end_for_pipe(dc, pipe_ctx);3015 3016 dc->hwss.update_plane_addr(dc, pipe_ctx);3017 3018 program_surface_visibility(dc, pipe_ctx);3019 3020 }3021 3022 if (dc->fbc_compressor)3023 enable_fbc(dc, context);3024}3025 3026static void dce110_post_unlock_program_front_end(3027 struct dc *dc,3028 struct dc_state *context)3029{3030}3031 3032static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)3033{3034 struct dce_hwseq *hws = dc->hwseq;3035 int fe_idx = pipe_ctx->plane_res.mi ?3036 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;3037 3038 /* Do not power down fe when stream is active on dce*/3039 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)3040 return;3041 3042 hws->funcs.enable_display_power_gating(3043 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);3044 3045 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(3046 dc->res_pool->transforms[fe_idx]);3047}3048 3049static void dce110_wait_for_mpcc_disconnect(3050 struct dc *dc,3051 struct resource_pool *res_pool,3052 struct pipe_ctx *pipe_ctx)3053{3054 /* do nothing*/3055}3056 3057static void program_output_csc(struct dc *dc,3058 struct pipe_ctx *pipe_ctx,3059 enum dc_color_space colorspace,3060 uint16_t *matrix,3061 int opp_id)3062{3063 int i;3064 struct out_csc_color_matrix tbl_entry;3065 3066 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {3067 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;3068 3069 for (i = 0; i < 12; i++)3070 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];3071 3072 tbl_entry.color_space = color_space;3073 3074 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(3075 pipe_ctx->plane_res.xfm, &tbl_entry);3076 }3077}3078 3079static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)3080{3081 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;3082 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;3083 struct mem_input *mi = pipe_ctx->plane_res.mi;3084 struct dc_cursor_mi_param param = {3085 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,3086 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,3087 .viewport = pipe_ctx->plane_res.scl_data.viewport,3088 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,3089 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,3090 .rotation = pipe_ctx->plane_state->rotation,3091 .mirror = pipe_ctx->plane_state->horizontal_mirror3092 };3093 3094 /**3095 * If the cursor's source viewport is clipped then we need to3096 * translate the cursor to appear in the correct position on3097 * the screen.3098 *3099 * This translation isn't affected by scaling so it needs to be3100 * done *after* we adjust the position for the scale factor.3101 *3102 * This is only done by opt-in for now since there are still3103 * some usecases like tiled display that might enable the3104 * cursor on both streams while expecting dc to clip it.3105 */3106 if (pos_cpy.translate_by_source) {3107 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;3108 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;3109 }3110 3111 if (pipe_ctx->plane_state->address.type3112 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)3113 pos_cpy.enable = false;3114 3115 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)3116 pos_cpy.enable = false;3117 3118 if (ipp->funcs->ipp_cursor_set_position)3119 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);3120 if (mi->funcs->set_cursor_position)3121 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);3122}3123 3124static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)3125{3126 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;3127 3128 if (pipe_ctx->plane_res.ipp &&3129 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)3130 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(3131 pipe_ctx->plane_res.ipp, attributes);3132 3133 if (pipe_ctx->plane_res.mi &&3134 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)3135 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(3136 pipe_ctx->plane_res.mi, attributes);3137 3138 if (pipe_ctx->plane_res.xfm &&3139 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)3140 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(3141 pipe_ctx->plane_res.xfm, attributes);3142}3143 3144bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,3145 uint32_t backlight_pwm_u16_16,3146 uint32_t frame_ramp)3147{3148 struct dc_link *link = pipe_ctx->stream->link;3149 struct dc *dc = link->ctx->dc;3150 struct abm *abm = pipe_ctx->stream_res.abm;3151 struct panel_cntl *panel_cntl = link->panel_cntl;3152 struct dmcu *dmcu = dc->res_pool->dmcu;3153 bool fw_set_brightness = true;3154 /* DMCU -1 for all controller id values,3155 * therefore +1 here3156 */3157 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;3158 3159 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))3160 return false;3161 3162 if (dmcu)3163 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);3164 3165 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)3166 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);3167 else3168 abm->funcs->set_backlight_level_pwm(3169 abm,3170 backlight_pwm_u16_16,3171 frame_ramp,3172 controller_id,3173 link->panel_cntl->inst);3174 3175 return true;3176}3177 3178void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)3179{3180 struct abm *abm = pipe_ctx->stream_res.abm;3181 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;3182 3183 if (abm)3184 abm->funcs->set_abm_immediate_disable(abm,3185 pipe_ctx->stream->link->panel_cntl->inst);3186 3187 if (panel_cntl)3188 panel_cntl->funcs->store_backlight_level(panel_cntl);3189}3190 3191void dce110_set_pipe(struct pipe_ctx *pipe_ctx)3192{3193 struct abm *abm = pipe_ctx->stream_res.abm;3194 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;3195 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;3196 3197 if (abm && panel_cntl)3198 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);3199}3200 3201void dce110_enable_lvds_link_output(struct dc_link *link,3202 const struct link_resource *link_res,3203 enum clock_source_id clock_source,3204 uint32_t pixel_clock)3205{3206 link->link_enc->funcs->enable_lvds_output(3207 link->link_enc,3208 clock_source,3209 pixel_clock);3210 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;3211}3212 3213void dce110_enable_tmds_link_output(struct dc_link *link,3214 const struct link_resource *link_res,3215 enum signal_type signal,3216 enum clock_source_id clock_source,3217 enum dc_color_depth color_depth,3218 uint32_t pixel_clock)3219{3220 link->link_enc->funcs->enable_tmds_output(3221 link->link_enc,3222 clock_source,3223 color_depth,3224 signal,3225 pixel_clock);3226 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;3227}3228 3229void dce110_enable_dp_link_output(3230 struct dc_link *link,3231 const struct link_resource *link_res,3232 enum signal_type signal,3233 enum clock_source_id clock_source,3234 const struct dc_link_settings *link_settings)3235{3236 struct dc *dc = link->ctx->dc;3237 struct dmcu *dmcu = dc->res_pool->dmcu;3238 struct pipe_ctx *pipes =3239 link->dc->current_state->res_ctx.pipe_ctx;3240 struct clock_source *dp_cs =3241 link->dc->res_pool->dp_clock_source;3242 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);3243 unsigned int i;3244 3245 /*3246 * Add the logic to extract BOTH power up and power down sequences3247 * from enable/disable link output and only call edp panel control3248 * in enable_link_dp and disable_link_dp once.3249 */3250 if (link->connector_signal == SIGNAL_TYPE_EDP) {3251 link->dc->hwss.edp_wait_for_hpd_ready(link, true);3252 }3253 3254 /* If the current pixel clock source is not DTO(happens after3255 * switching from HDMI passive dongle to DP on the same connector),3256 * switch the pixel clock source to DTO.3257 */3258 3259 for (i = 0; i < MAX_PIPES; i++) {3260 if (pipes[i].stream != NULL &&3261 pipes[i].stream->link == link) {3262 if (pipes[i].clock_source != NULL &&3263 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {3264 pipes[i].clock_source = dp_cs;3265 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =3266 pipes[i].stream->timing.pix_clk_100hz;3267 pipes[i].clock_source->funcs->program_pix_clk(3268 pipes[i].clock_source,3269 &pipes[i].stream_res.pix_clk_params,3270 dc->link_srv->dp_get_encoding_format(link_settings),3271 &pipes[i].pll_settings);3272 }3273 }3274 }3275 3276 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {3277 if (dc->clk_mgr->funcs->notify_link_rate_change)3278 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);3279 }3280 3281 if (dmcu != NULL && dmcu->funcs->lock_phy)3282 dmcu->funcs->lock_phy(dmcu);3283 3284 if (link_hwss->ext.enable_dp_link_output)3285 link_hwss->ext.enable_dp_link_output(link, link_res, signal,3286 clock_source, link_settings);3287 3288 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;3289 3290 if (dmcu != NULL && dmcu->funcs->unlock_phy)3291 dmcu->funcs->unlock_phy(dmcu);3292 3293 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);3294}3295 3296void dce110_disable_link_output(struct dc_link *link,3297 const struct link_resource *link_res,3298 enum signal_type signal)3299{3300 struct dc *dc = link->ctx->dc;3301 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);3302 struct dmcu *dmcu = dc->res_pool->dmcu;3303 3304 if (signal == SIGNAL_TYPE_EDP &&3305 link->dc->hwss.edp_backlight_control &&3306 !link->skip_implict_edp_power_control)3307 link->dc->hwss.edp_backlight_control(link, false);3308 else if (dmcu != NULL && dmcu->funcs->lock_phy)3309 dmcu->funcs->lock_phy(dmcu);3310 3311 link_hwss->disable_link_output(link, link_res, signal);3312 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;3313 /*3314 * Add the logic to extract BOTH power up and power down sequences3315 * from enable/disable link output and only call edp panel control3316 * in enable_link_dp and disable_link_dp once.3317 */3318 if (dmcu != NULL && dmcu->funcs->lock_phy)3319 dmcu->funcs->unlock_phy(dmcu);3320 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);3321}3322 3323static const struct hw_sequencer_funcs dce110_funcs = {3324 .program_gamut_remap = program_gamut_remap,3325 .program_output_csc = program_output_csc,3326 .init_hw = init_hw,3327 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,3328 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,3329 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,3330 .update_plane_addr = update_plane_addr,3331 .update_pending_status = dce110_update_pending_status,3332 .enable_accelerated_mode = dce110_enable_accelerated_mode,3333 .enable_timing_synchronization = dce110_enable_timing_synchronization,3334 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,3335 .update_info_frame = dce110_update_info_frame,3336 .enable_stream = dce110_enable_stream,3337 .disable_stream = dce110_disable_stream,3338 .unblank_stream = dce110_unblank_stream,3339 .blank_stream = dce110_blank_stream,3340 .enable_audio_stream = dce110_enable_audio_stream,3341 .disable_audio_stream = dce110_disable_audio_stream,3342 .disable_plane = dce110_power_down_fe,3343 .pipe_control_lock = dce_pipe_control_lock,3344 .interdependent_update_lock = NULL,3345 .cursor_lock = dce_pipe_control_lock,3346 .prepare_bandwidth = dce110_prepare_bandwidth,3347 .optimize_bandwidth = dce110_optimize_bandwidth,3348 .set_drr = set_drr,3349 .get_position = get_position,3350 .set_static_screen_control = set_static_screen_control,3351 .setup_stereo = NULL,3352 .set_avmute = dce110_set_avmute,3353 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,3354 .edp_backlight_control = dce110_edp_backlight_control,3355 .edp_power_control = dce110_edp_power_control,3356 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,3357 .set_cursor_position = dce110_set_cursor_position,3358 .set_cursor_attribute = dce110_set_cursor_attribute,3359 .set_backlight_level = dce110_set_backlight_level,3360 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,3361 .set_pipe = dce110_set_pipe,3362 .enable_lvds_link_output = dce110_enable_lvds_link_output,3363 .enable_tmds_link_output = dce110_enable_tmds_link_output,3364 .enable_dp_link_output = dce110_enable_dp_link_output,3365 .disable_link_output = dce110_disable_link_output,3366};3367 3368static const struct hwseq_private_funcs dce110_private_funcs = {3369 .init_pipes = init_pipes,3370 .set_input_transfer_func = dce110_set_input_transfer_func,3371 .set_output_transfer_func = dce110_set_output_transfer_func,3372 .power_down = dce110_power_down,3373 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,3374 .enable_display_power_gating = dce110_enable_display_power_gating,3375 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,3376 .enable_stream_timing = dce110_enable_stream_timing,3377 .disable_stream_gating = NULL,3378 .enable_stream_gating = NULL,3379 .edp_backlight_control = dce110_edp_backlight_control,3380};3381 3382void dce110_hw_sequencer_construct(struct dc *dc)3383{3384 dc->hwss = dce110_funcs;3385 dc->hwseq->funcs = dce110_private_funcs;3386}3387 3388