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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "dm_services.h"27#include "dc.h"28#include "core_types.h"29#include "dce120_hwseq.h"30#include "dce/dce_hwseq.h"31 32#include "dce110/dce110_hwseq.h"33 34#include "dce/dce_12_0_offset.h"35#include "dce/dce_12_0_sh_mask.h"36#include "soc15_hw_ip.h"37#include "vega10_ip_offset.h"38#include "reg_helper.h"39 40#define CTX \41 hws->ctx42#define REG(reg)\43 hws->regs->reg44 45#undef FN46#define FN(reg_name, field_name) \47 hws->shifts->field_name, hws->masks->field_name48 49struct dce120_hw_seq_reg_offsets {50 uint32_t crtc;51};52 53#if 054static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {55{56 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),57},58{59 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),60},61{62 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),63},64{65 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),66},67{68 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),69},70{71 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),72}73};74 75#define HW_REG_CRTC(reg, id)\76 (reg + reg_offsets[id].crtc)77 78#define CNTL_ID(controller_id)\79 controller_id80/*******************************************************************************81 * Private definitions82 ******************************************************************************/83static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)84{85 uint32_t addr;86 uint32_t value = 0;87 uint32_t chunk_int = 0;88 uint32_t chunk_mul = 0;89/*90 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *91 (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);92 93 value = dm_read_reg(ctx, addr);94 95 set_reg_field_value(96 value, 0, DCP, controller_id,97 DVMM_PTE_CONTROL,98 DVMM_USE_SINGLE_PTE);99 100 set_reg_field_value_soc15(101 value, 1, DCP, controller_id,102 DVMM_PTE_CONTROL,103 DVMM_PTE_BUFFER_MODE0);104 105 set_reg_field_value_soc15(106 value, 1, DCP, controller_id,107 DVMM_PTE_CONTROL,108 DVMM_PTE_BUFFER_MODE1);109 110 dm_write_reg(ctx, addr, value);*/111 112 addr = mmDVMM_PTE_REQ;113 value = dm_read_reg(ctx, addr);114 115 chunk_int = get_reg_field_value(116 value,117 DVMM_PTE_REQ,118 HFLIP_PTEREQ_PER_CHUNK_INT);119 120 chunk_mul = get_reg_field_value(121 value,122 DVMM_PTE_REQ,123 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);124 125 if (chunk_int != 0x4 || chunk_mul != 0x4) {126 127 set_reg_field_value(128 value,129 255,130 DVMM_PTE_REQ,131 MAX_PTEREQ_TO_ISSUE);132 133 set_reg_field_value(134 value,135 4,136 DVMM_PTE_REQ,137 HFLIP_PTEREQ_PER_CHUNK_INT);138 139 set_reg_field_value(140 value,141 4,142 DVMM_PTE_REQ,143 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);144 145 dm_write_reg(ctx, addr, value);146 }147}148#endif149 150static bool dce120_enable_display_power_gating(151 struct dc *dc,152 uint8_t controller_id,153 struct dc_bios *dcb,154 enum pipe_gating_control power_gating)155{156 /* disable for bringup */157#if 0158 enum bp_result bp_result = BP_RESULT_OK;159 enum bp_pipe_control_action cntl;160 struct dc_context *ctx = dc->ctx;161 162 if (power_gating == PIPE_GATING_CONTROL_INIT)163 cntl = ASIC_PIPE_INIT;164 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)165 cntl = ASIC_PIPE_ENABLE;166 else167 cntl = ASIC_PIPE_DISABLE;168 169 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {170 171 bp_result = dcb->funcs->enable_disp_power_gating(172 dcb, controller_id + 1, cntl);173 174 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2175 * by default when command table is called176 */177 dm_write_reg(ctx,178 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),179 0);180 }181 182 if (power_gating != PIPE_GATING_CONTROL_ENABLE)183 dce120_init_pte(ctx, controller_id);184 185 if (bp_result == BP_RESULT_OK)186 return true;187 else188 return false;189#endif190 return false;191}192 193static void dce120_update_dchub(194 struct dce_hwseq *hws,195 struct dchub_init_data *dh_data)196{197 /* TODO: port code from dal2 */198 switch (dh_data->fb_mode) {199 case FRAME_BUFFER_MODE_ZFB_ONLY:200 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/201 REG_UPDATE_2(DCHUB_FB_LOCATION,202 FB_TOP, 0,203 FB_BASE, 0x0FFFF);204 205 REG_UPDATE(DCHUB_AGP_BASE,206 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);207 208 REG_UPDATE(DCHUB_AGP_BOT,209 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);210 211 REG_UPDATE(DCHUB_AGP_TOP,212 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);213 break;214 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:215 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/216 REG_UPDATE(DCHUB_AGP_BASE,217 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);218 219 REG_UPDATE(DCHUB_AGP_BOT,220 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);221 222 REG_UPDATE(DCHUB_AGP_TOP,223 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);224 break;225 case FRAME_BUFFER_MODE_LOCAL_ONLY:226 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/227 REG_UPDATE(DCHUB_AGP_BASE,228 AGP_BASE, 0);229 230 REG_UPDATE(DCHUB_AGP_BOT,231 AGP_BOT, 0x03FFFF);232 233 REG_UPDATE(DCHUB_AGP_TOP,234 AGP_TOP, 0);235 break;236 default:237 break;238 }239 240 dh_data->dchub_initialzied = true;241 dh_data->dchub_info_valid = false;242}243 244/**245 * dce121_xgmi_enabled() - Check if xGMI is enabled246 * @hws: DCE hardware sequencer object247 *248 * Return true if xGMI is enabled. False otherwise.249 */250bool dce121_xgmi_enabled(struct dce_hwseq *hws)251{252 uint32_t pf_max_region;253 254 REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);255 /* PF_MAX_REGION == 0 means xgmi is disabled */256 return !!pf_max_region;257}258 259void dce120_hw_sequencer_construct(struct dc *dc)260{261 /* All registers used by dce11.2 match those in dce11 in offset and262 * structure263 */264 dce110_hw_sequencer_construct(dc);265 dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;266 dc->hwss.update_dchub = dce120_update_dchub;267}268 269