211 lines · c
1/*2* Copyright 2016-2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DC_HWSS_DCN10_H__27#define __DC_HWSS_DCN10_H__28 29#include "core_types.h"30#include "hw_sequencer_private.h"31 32struct dc;33 34void dcn10_hw_sequencer_construct(struct dc *dc);35 36int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);37void dcn10_calc_vupdate_position(38 struct dc *dc,39 struct pipe_ctx *pipe_ctx,40 uint32_t *start_line,41 uint32_t *end_line);42void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);43enum dc_status dcn10_enable_stream_timing(44 struct pipe_ctx *pipe_ctx,45 struct dc_state *context,46 struct dc *dc);47void dcn10_optimize_bandwidth(48 struct dc *dc,49 struct dc_state *context);50void dcn10_prepare_bandwidth(51 struct dc *dc,52 struct dc_state *context);53void dcn10_pipe_control_lock(54 struct dc *dc,55 struct pipe_ctx *pipe,56 bool lock);57void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);58void dcn10_blank_pixel_data(59 struct dc *dc,60 struct pipe_ctx *pipe_ctx,61 bool blank);62void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,63 struct dc_link_settings *link_settings);64void dcn10_program_output_csc(struct dc *dc,65 struct pipe_ctx *pipe_ctx,66 enum dc_color_space colorspace,67 uint16_t *matrix,68 int opp_id);69bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,70 const struct dc_stream_state *stream);71bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,72 const struct dc_plane_state *plane_state);73void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);74void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);75void dcn10_reset_hw_ctx_wrap(76 struct dc *dc,77 struct dc_state *context);78void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);79void dcn10_lock_all_pipes(80 struct dc *dc,81 struct dc_state *context,82 bool lock);83void dcn10_post_unlock_program_front_end(84 struct dc *dc,85 struct dc_state *context);86void dcn10_hubp_pg_control(87 struct dce_hwseq *hws,88 unsigned int hubp_inst,89 bool power_on);90void dcn10_dpp_pg_control(91 struct dce_hwseq *hws,92 unsigned int dpp_inst,93 bool power_on);94void dcn10_enable_power_gating_plane(95 struct dce_hwseq *hws,96 bool enable);97void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);98void dcn10_disable_vga(99 struct dce_hwseq *hws);100void dcn10_program_pipe(101 struct dc *dc,102 struct pipe_ctx *pipe_ctx,103 struct dc_state *context);104void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);105void dcn10_init_hw(struct dc *dc);106void dcn10_init_pipes(struct dc *dc, struct dc_state *context);107void dcn10_power_down_on_boot(struct dc *dc);108enum dc_status dce110_apply_ctx_to_hw(109 struct dc *dc,110 struct dc_state *context);111void dcn10_plane_atomic_disconnect(struct dc *dc,112 struct dc_state *state,113 struct pipe_ctx *pipe_ctx);114void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);115void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);116void dce110_power_down(struct dc *dc);117void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);118void dcn10_enable_timing_synchronization(119 struct dc *dc,120 struct dc_state *state,121 int group_index,122 int group_size,123 struct pipe_ctx *grouped_pipes[]);124void dcn10_enable_vblanks_synchronization(125 struct dc *dc,126 int group_index,127 int group_size,128 struct pipe_ctx *grouped_pipes[]);129void dcn10_enable_per_frame_crtc_position_reset(130 struct dc *dc,131 int group_size,132 struct pipe_ctx *grouped_pipes[]);133void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);134void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,135 const uint8_t *custom_sdp_message,136 unsigned int sdp_message_size);137void dce110_blank_stream(struct pipe_ctx *pipe_ctx);138void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);139void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);140bool dcn10_dummy_display_power_gating(141 struct dc *dc,142 uint8_t controller_id,143 struct dc_bios *dcb,144 enum pipe_gating_control power_gating);145void dcn10_set_drr(struct pipe_ctx **pipe_ctx,146 int num_pipes, struct dc_crtc_timing_adjust adjust);147void dcn10_get_position(struct pipe_ctx **pipe_ctx,148 int num_pipes,149 struct crtc_position *position);150void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,151 int num_pipes, const struct dc_static_screen_params *params);152void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);153void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);154void dcn10_log_hw_state(struct dc *dc,155 struct dc_log_buffer_ctx *log_ctx);156void dcn10_get_hw_state(struct dc *dc,157 char *pBuf,158 unsigned int bufSize,159 unsigned int mask);160void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);161void dcn10_wait_for_mpcc_disconnect(162 struct dc *dc,163 struct resource_pool *res_pool,164 struct pipe_ctx *pipe_ctx);165void dce110_edp_backlight_control(166 struct dc_link *link,167 bool enable);168void dce110_edp_wait_for_T12(169 struct dc_link *link);170void dce110_edp_power_control(171 struct dc_link *link,172 bool power_up);173void dce110_edp_wait_for_hpd_ready(174 struct dc_link *link,175 bool power_up);176void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);177void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);178void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);179void dcn10_setup_periodic_interrupt(180 struct dc *dc,181 struct pipe_ctx *pipe_ctx);182enum dc_status dcn10_set_clock(struct dc *dc,183 enum dc_clock_type clock_type,184 uint32_t clk_khz,185 uint32_t stepping);186void dcn10_get_clock(struct dc *dc,187 enum dc_clock_type clock_type,188 struct dc_clock_config *clock_cfg);189bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);190void dcn10_bios_golden_init(struct dc *dc);191void dcn10_plane_atomic_power_down(struct dc *dc,192 struct dpp *dpp,193 struct hubp *hubp);194bool dcn10_disconnect_pipes(195 struct dc *dc,196 struct dc_state *context);197 198void dcn10_wait_for_pending_cleared(struct dc *dc,199 struct dc_state *context);200void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);201void dcn10_verify_allow_pstate_change_high(struct dc *dc);202 203void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);204 205void dcn10_update_visual_confirm_color(206 struct dc *dc,207 struct pipe_ctx *pipe_ctx,208 int mpcc_id);209 210#endif /* __DC_HWSS_DCN10_H__ */211