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1/*2* Copyright 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DC_HWSS_DCN20_H__27#define __DC_HWSS_DCN20_H__28 29#include "hw_sequencer_private.h"30 31void dcn20_log_color_state(struct dc *dc,32 struct dc_log_buffer_ctx *log_ctx);33bool dcn20_set_blend_lut(34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);35bool dcn20_set_shaper_3dlut(36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);37void dcn20_program_front_end_for_ctx(38 struct dc *dc,39 struct dc_state *context);40void dcn20_post_unlock_program_front_end(41 struct dc *dc,42 struct dc_state *context);43void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);44void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);45bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,46 const struct dc_plane_state *plane_state);47bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,48 const struct dc_stream_state *stream);49void dcn20_program_output_csc(struct dc *dc,50 struct pipe_ctx *pipe_ctx,51 enum dc_color_space colorspace,52 uint16_t *matrix,53 int opp_id);54void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);55void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,56 struct dc_link_settings *link_settings);57void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);58void dcn20_disable_pixel_data(59 struct dc *dc,60 struct pipe_ctx *pipe_ctx,61 bool blank);62void dcn20_blank_pixel_data(63 struct dc *dc,64 struct pipe_ctx *pipe_ctx,65 bool blank);66void dcn20_pipe_control_lock(67 struct dc *dc,68 struct pipe_ctx *pipe,69 bool lock);70void dcn20_prepare_bandwidth(71 struct dc *dc,72 struct dc_state *context);73void dcn20_optimize_bandwidth(74 struct dc *dc,75 struct dc_state *context);76bool dcn20_update_bandwidth(77 struct dc *dc,78 struct dc_state *context);79void dcn20_reset_hw_ctx_wrap(80 struct dc *dc,81 struct dc_state *context);82enum dc_status dcn20_enable_stream_timing(83 struct pipe_ctx *pipe_ctx,84 struct dc_state *context,85 struct dc *dc);86void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);87void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);88void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);89void dcn20_reset_back_end_for_pipe(90 struct dc *dc,91 struct pipe_ctx *pipe_ctx,92 struct dc_state *context);93void dcn20_init_blank(94 struct dc *dc,95 struct timing_generator *tg);96void dcn20_disable_vga(97 struct dce_hwseq *hws);98void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);99void dcn20_enable_power_gating_plane(100 struct dce_hwseq *hws,101 bool enable);102void dcn20_dpp_pg_control(103 struct dce_hwseq *hws,104 unsigned int dpp_inst,105 bool power_on);106void dcn20_hubp_pg_control(107 struct dce_hwseq *hws,108 unsigned int hubp_inst,109 bool power_on);110void dcn20_program_triple_buffer(111 const struct dc *dc,112 struct pipe_ctx *pipe_ctx,113 bool enable_triple_buffer);114void dcn20_enable_writeback(115 struct dc *dc,116 struct dc_writeback_info *wb_info,117 struct dc_state *context);118void dcn20_disable_writeback(119 struct dc *dc,120 unsigned int dwb_pipe_inst);121void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);122bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);123void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);124void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);125void dcn20_init_vm_ctx(126 struct dce_hwseq *hws,127 struct dc *dc,128 struct dc_virtual_addr_space_config *va_config,129 int vmid);130void dcn20_set_flip_control_gsl(131 struct pipe_ctx *pipe_ctx,132 bool flip_immediate);133void dcn20_dsc_pg_control(134 struct dce_hwseq *hws,135 unsigned int dsc_inst,136 bool power_on);137void dcn20_fpga_init_hw(struct dc *dc);138bool dcn20_wait_for_blank_complete(139 struct output_pixel_processor *opp);140void dcn20_dccg_init(struct dce_hwseq *hws);141int dcn20_init_sys_ctx(struct dce_hwseq *hws,142 struct dc *dc,143 struct dc_phy_addr_space_config *pa_config);144 145void dcn20_set_disp_pattern_generator(const struct dc *dc,146 struct pipe_ctx *pipe_ctx,147 enum controller_dp_test_pattern test_pattern,148 enum controller_dp_color_space color_space,149 enum dc_color_depth color_depth,150 const struct tg_color *solid_color,151 int width, int height, int offset);152 153void dcn20_setup_gsl_group_as_lock(154 const struct dc *dc,155 struct pipe_ctx *pipe_ctx,156 bool enable);157 158#endif /* __DC_HWSS_DCN20_H__ */159 160