1188 lines · c
1/*2 * Copyright 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26 27#include "dm_services.h"28#include "dm_helpers.h"29#include "core_types.h"30#include "resource.h"31#include "dcn30_hwseq.h"32#include "dccg.h"33#include "dce/dce_hwseq.h"34#include "dcn30/dcn30_mpc.h"35#include "dcn30/dcn30_dpp.h"36#include "dcn10/dcn10_cm_common.h"37#include "dcn30/dcn30_cm_common.h"38#include "reg_helper.h"39#include "abm.h"40#include "clk_mgr.h"41#include "hubp.h"42#include "dchubbub.h"43#include "timing_generator.h"44#include "opp.h"45#include "ipp.h"46#include "mpc.h"47#include "mcif_wb.h"48#include "dc_dmub_srv.h"49#include "link_hwss.h"50#include "dpcd_defs.h"51#include "dcn20/dcn20_hwseq.h"52#include "dcn30/dcn30_resource.h"53#include "link.h"54#include "dc_state_priv.h"55 56 57 58#define DC_LOGGER_INIT(logger)59 60#define CTX \61 hws->ctx62#define REG(reg)\63 hws->regs->reg64#define DC_LOGGER \65 dc->ctx->logger66 67 68#undef FN69#define FN(reg_name, field_name) \70 hws->shifts->field_name, hws->masks->field_name71 72void dcn30_log_color_state(struct dc *dc,73 struct dc_log_buffer_ctx *log_ctx)74{75 struct dc_context *dc_ctx = dc->ctx;76 struct resource_pool *pool = dc->res_pool;77 int i;78 79 DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode"80 " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode"81 " GAMUT adjust "82 "C11 C12 C13 C14 "83 "C21 C22 C23 C24 "84 "C31 C32 C33 C34 \n");85 86 for (i = 0; i < pool->pipe_count; i++) {87 struct dpp *dpp = pool->dpps[i];88 struct dcn_dpp_state s = {0};89 90 dpp->funcs->dpp_read_state(dpp, &s);91 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);92 93 if (!s.is_enabled)94 continue;95 96 DTN_INFO("[%2d]: %7x %13s %8s %11s %10s %15s %10s %9s"97 " %12s "98 "%010lld %010lld %010lld %010lld "99 "%010lld %010lld %010lld %010lld "100 "%010lld %010lld %010lld %010lld",101 dpp->inst,102 s.pre_dgam_mode,103 (s.pre_dgam_select == 0) ? "sRGB" :104 ((s.pre_dgam_select == 1) ? "Gamma 2.2" :105 ((s.pre_dgam_select == 2) ? "Gamma 2.4" :106 ((s.pre_dgam_select == 3) ? "Gamma 2.6" :107 ((s.pre_dgam_select == 4) ? "BT.709" :108 ((s.pre_dgam_select == 5) ? "PQ" :109 ((s.pre_dgam_select == 6) ? "HLG" :110 "Unknown")))))),111 (s.gamcor_mode == 0) ? "Bypass" :112 ((s.gamcor_mode == 1) ? "RAM A" :113 "RAM B"),114 (s.shaper_lut_mode == 1) ? "RAM A" :115 ((s.shaper_lut_mode == 2) ? "RAM B" :116 "Bypass"),117 (s.lut3d_mode == 1) ? "RAM A" :118 ((s.lut3d_mode == 2) ? "RAM B" :119 "Bypass"),120 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",121 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",122 (s.rgam_lut_mode == 0) ? "Bypass" :123 ((s.rgam_lut_mode == 1) ? "RAM A" :124 "RAM B"),125 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :126 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :127 "SW"),128 s.gamut_remap.temperature_matrix[0].value,129 s.gamut_remap.temperature_matrix[1].value,130 s.gamut_remap.temperature_matrix[2].value,131 s.gamut_remap.temperature_matrix[3].value,132 s.gamut_remap.temperature_matrix[4].value,133 s.gamut_remap.temperature_matrix[5].value,134 s.gamut_remap.temperature_matrix[6].value,135 s.gamut_remap.temperature_matrix[7].value,136 s.gamut_remap.temperature_matrix[8].value,137 s.gamut_remap.temperature_matrix[9].value,138 s.gamut_remap.temperature_matrix[10].value,139 s.gamut_remap.temperature_matrix[11].value);140 DTN_INFO("\n");141 }142 DTN_INFO("\n");143 DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"144 " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"145 " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"146 " blnd_lut:%d oscs:%d\n\n",147 dc->caps.color.dpp.input_lut_shared,148 dc->caps.color.dpp.icsc,149 dc->caps.color.dpp.dgam_ram,150 dc->caps.color.dpp.dgam_rom_caps.srgb,151 dc->caps.color.dpp.dgam_rom_caps.bt2020,152 dc->caps.color.dpp.dgam_rom_caps.gamma2_2,153 dc->caps.color.dpp.dgam_rom_caps.pq,154 dc->caps.color.dpp.dgam_rom_caps.hlg,155 dc->caps.color.dpp.post_csc,156 dc->caps.color.dpp.gamma_corr,157 dc->caps.color.dpp.dgam_rom_for_yuv,158 dc->caps.color.dpp.hw_3d_lut,159 dc->caps.color.dpp.ogam_ram,160 dc->caps.color.dpp.ocsc);161 162 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"163 " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT"164 " GAMUT adjust "165 "C11 C12 C13 C14 "166 "C21 C22 C23 C24 "167 "C31 C32 C33 C34 \n");168 169 for (i = 0; i < pool->mpcc_count; i++) {170 struct mpcc_state s = {0};171 172 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);173 mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);174 175 if (s.opp_id != 0xf)176 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %11s %11s %16s %11s %10s %9s"177 " %-12s "178 "%010lld %010lld %010lld %010lld "179 "%010lld %010lld %010lld %010lld "180 "%010lld %010lld %010lld %010lld\n",181 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,182 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,183 s.idle,184 (s.shaper_lut_mode == 1) ? "RAM A" :185 ((s.shaper_lut_mode == 2) ? "RAM B" :186 "Bypass"),187 (s.lut3d_mode == 1) ? "RAM A" :188 ((s.lut3d_mode == 2) ? "RAM B" :189 "Bypass"),190 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",191 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",192 (s.rgam_mode == 0) ? "Bypass" :193 ((s.rgam_mode == 2) ? "RAM" :194 "Unknown"),195 (s.rgam_mode == 1) ? "B" : "A",196 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :197 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :198 "SW"),199 s.gamut_remap.temperature_matrix[0].value,200 s.gamut_remap.temperature_matrix[1].value,201 s.gamut_remap.temperature_matrix[2].value,202 s.gamut_remap.temperature_matrix[3].value,203 s.gamut_remap.temperature_matrix[4].value,204 s.gamut_remap.temperature_matrix[5].value,205 s.gamut_remap.temperature_matrix[6].value,206 s.gamut_remap.temperature_matrix[7].value,207 s.gamut_remap.temperature_matrix[8].value,208 s.gamut_remap.temperature_matrix[9].value,209 s.gamut_remap.temperature_matrix[10].value,210 s.gamut_remap.temperature_matrix[11].value);211 212 }213 DTN_INFO("\n");214 DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",215 dc->caps.color.mpc.gamut_remap,216 dc->caps.color.mpc.num_3dluts,217 dc->caps.color.mpc.ogam_ram,218 dc->caps.color.mpc.ocsc);219}220 221bool dcn30_set_blend_lut(222 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)223{224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;225 bool result = true;226 const struct pwl_params *blend_lut = NULL;227 228 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)229 blend_lut = &plane_state->blend_tf.pwl;230 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {231 result = cm3_helper_translate_curve_to_hw_format(232 &plane_state->blend_tf, &dpp_base->regamma_params, false);233 if (!result)234 return result;235 236 blend_lut = &dpp_base->regamma_params;237 }238 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);239 240 return result;241}242 243static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,244 const struct dc_stream_state *stream)245{246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;247 int mpcc_id = pipe_ctx->plane_res.hubp->inst;248 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;249 bool result = false;250 int acquired_rmu = 0;251 int mpcc_id_projected = 0;252 253 const struct pwl_params *shaper_lut = NULL;254 //get the shaper lut params255 if (stream->func_shaper) {256 if (stream->func_shaper->type == TF_TYPE_HWPWL) {257 shaper_lut = &stream->func_shaper->pwl;258 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {259 cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,260 &dpp_base->shaper_params, true);261 shaper_lut = &dpp_base->shaper_params;262 }263 }264 265 if (stream->lut3d_func &&266 stream->lut3d_func->state.bits.initialized == 1 &&267 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {268 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)269 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;270 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)271 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;272 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)273 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;274 if (mpcc_id_projected != mpcc_id)275 BREAK_TO_DEBUGGER();276 /* find the reason why logical layer assigned a different277 * mpcc_id into acquire_post_bldn_3dlut278 */279 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,280 stream->lut3d_func->state.bits.rmu_mux_num);281 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)282 BREAK_TO_DEBUGGER();283 284 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,285 stream->lut3d_func->state.bits.rmu_mux_num);286 result = mpc->funcs->program_shaper(mpc, shaper_lut,287 stream->lut3d_func->state.bits.rmu_mux_num);288 } else {289 // loop through the available mux and release the requested mpcc_id290 mpc->funcs->release_rmu(mpc, mpcc_id);291 }292 293 return result;294}295 296bool dcn30_set_input_transfer_func(struct dc *dc,297 struct pipe_ctx *pipe_ctx,298 const struct dc_plane_state *plane_state)299{300 struct dce_hwseq *hws = dc->hwseq;301 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;302 enum dc_transfer_func_predefined tf;303 bool result = true;304 const struct pwl_params *params = NULL;305 306 if (dpp_base == NULL || plane_state == NULL)307 return false;308 309 tf = TRANSFER_FUNCTION_UNITY;310 311 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)312 tf = plane_state->in_transfer_func.tf;313 314 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);315 316 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)317 params = &plane_state->in_transfer_func.pwl;318 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&319 cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,320 &dpp_base->degamma_params, false))321 params = &dpp_base->degamma_params;322 323 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);324 325 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {326 if (dpp_base->funcs->dpp_program_blnd_lut)327 hws->funcs.set_blend_lut(pipe_ctx, plane_state);328 if (dpp_base->funcs->dpp_program_shaper_lut &&329 dpp_base->funcs->dpp_program_3dlut)330 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);331 }332 333 return result;334}335 336void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)337{338 int i = 0;339 struct dpp_grph_csc_adjustment dpp_adjust;340 struct mpc_grph_gamut_adjustment mpc_adjust;341 int mpcc_id = pipe_ctx->plane_res.hubp->inst;342 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;343 344 memset(&dpp_adjust, 0, sizeof(dpp_adjust));345 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;346 347 if (pipe_ctx->plane_state &&348 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {349 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;350 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)351 dpp_adjust.temperature_matrix[i] =352 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];353 }354 355 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,356 &dpp_adjust);357 358 memset(&mpc_adjust, 0, sizeof(mpc_adjust));359 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;360 361 if (pipe_ctx->top_pipe == NULL) {362 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {363 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;364 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)365 mpc_adjust.temperature_matrix[i] =366 pipe_ctx->stream->gamut_remap_matrix.matrix[i];367 }368 }369 370 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);371}372 373bool dcn30_set_output_transfer_func(struct dc *dc,374 struct pipe_ctx *pipe_ctx,375 const struct dc_stream_state *stream)376{377 int mpcc_id = pipe_ctx->plane_res.hubp->inst;378 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;379 const struct pwl_params *params = NULL;380 bool ret = false;381 382 /* program OGAM or 3DLUT only for the top pipe*/383 if (pipe_ctx->top_pipe == NULL) {384 /*program rmu shaper and 3dlut in MPC*/385 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);386 if (ret == false && mpc->funcs->set_output_gamma) {387 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)388 params = &stream->out_transfer_func.pwl;389 else if (pipe_ctx->stream->out_transfer_func.type ==390 TF_TYPE_DISTRIBUTED_POINTS &&391 cm3_helper_translate_curve_to_hw_format(392 &stream->out_transfer_func,393 &mpc->blender_params, false))394 params = &mpc->blender_params;395 /* there are no ROM LUTs in OUTGAM */396 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)397 BREAK_TO_DEBUGGER();398 }399 }400 401 if (mpc->funcs->set_output_gamma)402 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);403 else404 DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);405 406 return ret;407}408 409static void dcn30_set_writeback(410 struct dc *dc,411 struct dc_writeback_info *wb_info,412 struct dc_state *context)413{414 struct mcif_wb *mcif_wb;415 struct mcif_buf_params *mcif_buf_params;416 417 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);418 ASSERT(wb_info->wb_enabled);419 ASSERT(wb_info->mpcc_inst >= 0);420 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);421 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];422 mcif_buf_params = &wb_info->mcif_buf_params;423 424 /* set DWB MPC mux */425 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,426 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);427 /* set MCIF_WB buffer and arbitration configuration */428 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);429 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);430}431 432void dcn30_update_writeback(433 struct dc *dc,434 struct dc_writeback_info *wb_info,435 struct dc_state *context)436{437 struct dwbc *dwb;438 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];439 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\440 __func__, wb_info->dwb_pipe_inst,\441 wb_info->mpcc_inst);442 443 dcn30_set_writeback(dc, wb_info, context);444 445 /* update DWB */446 dwb->funcs->update(dwb, &wb_info->dwb_params);447}448 449bool dcn30_mmhubbub_warmup(450 struct dc *dc,451 unsigned int num_dwb,452 struct dc_writeback_info *wb_info)453{454 struct dwbc *dwb;455 struct mcif_wb *mcif_wb;456 struct mcif_warmup_params warmup_params = {0};457 unsigned int i, i_buf;458 /* make sure there is no active DWB enabled */459 for (i = 0; i < num_dwb; i++) {460 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];461 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {462 /*can not do warmup while any dwb enabled*/463 return false;464 }465 }466 467 if (wb_info->mcif_warmup_params.p_vmid == 0)468 return false;469 470 /*check whether this is new interface: warmup big buffer once*/471 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&472 wb_info->mcif_warmup_params.region_size != 0) {473 /*mmhubbub is shared, so it does not matter which MCIF*/474 mcif_wb = dc->res_pool->mcif_wb[0];475 /*warmup a big chunk of VM buffer at once*/476 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;477 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;478 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;479 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;480 481 if (warmup_params.address_increment == 0)482 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;483 484 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);485 return true;486 }487 /*following is the original: warmup each DWB's mcif buffer*/488 for (i = 0; i < num_dwb; i++) {489 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];490 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];491 /*warmup is for VM mode only*/492 if (wb_info[i].mcif_buf_params.p_vmid == 0)493 return false;494 495 /* Warmup MCIF_WB */496 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {497 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];498 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;499 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;500 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;501 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);502 }503 }504 return true;505}506 507void dcn30_enable_writeback(508 struct dc *dc,509 struct dc_writeback_info *wb_info,510 struct dc_state *context)511{512 struct dwbc *dwb;513 struct mcif_wb *mcif_wb;514 515 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];516 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];517 518 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\519 __func__, wb_info->dwb_pipe_inst,\520 wb_info->mpcc_inst);521 522 /* Warmup interface */523 dcn30_mmhubbub_warmup(dc, 1, wb_info);524 525 /* Update writeback pipe */526 dcn30_set_writeback(dc, wb_info, context);527 528 /* Enable MCIF_WB */529 mcif_wb->funcs->enable_mcif(mcif_wb);530 /* Enable DWB */531 dwb->funcs->enable(dwb, &wb_info->dwb_params);532}533 534void dcn30_disable_writeback(535 struct dc *dc,536 unsigned int dwb_pipe_inst)537{538 struct dwbc *dwb;539 struct mcif_wb *mcif_wb;540 541 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);542 dwb = dc->res_pool->dwbc[dwb_pipe_inst];543 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];544 DC_LOG_DWB("%s dwb_pipe_inst = %d",\545 __func__, dwb_pipe_inst);546 547 /* disable DWB */548 dwb->funcs->disable(dwb);549 /* disable MCIF */550 mcif_wb->funcs->disable_mcif(mcif_wb);551 /* disable MPC DWB mux */552 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);553}554 555void dcn30_program_all_writeback_pipes_in_tree(556 struct dc *dc,557 const struct dc_stream_state *stream,558 struct dc_state *context)559{560 struct dc_writeback_info wb_info;561 struct dwbc *dwb;562 struct dc_stream_status *stream_status = NULL;563 int i_wb, i_pipe, i_stream;564 DC_LOG_DWB("%s", __func__);565 566 ASSERT(stream);567 for (i_stream = 0; i_stream < context->stream_count; i_stream++) {568 if (context->streams[i_stream] == stream) {569 stream_status = &context->stream_status[i_stream];570 break;571 }572 }573 ASSERT(stream_status);574 575 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);576 /* For each writeback pipe */577 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {578 579 /* copy writeback info to local non-const so mpcc_inst can be set */580 wb_info = stream->writeback_info[i_wb];581 if (wb_info.wb_enabled) {582 583 /* get the MPCC instance for writeback_source_plane */584 wb_info.mpcc_inst = -1;585 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {586 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];587 588 if (!pipe_ctx->plane_state)589 continue;590 591 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {592 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;593 break;594 }595 }596 597 if (wb_info.mpcc_inst == -1) {598 /* Disable writeback pipe and disconnect from MPCC599 * if source plane has been removed600 */601 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);602 continue;603 }604 605 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);606 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];607 if (dwb->funcs->is_enabled(dwb)) {608 /* writeback pipe already enabled, only need to update */609 dc->hwss.update_writeback(dc, &wb_info, context);610 } else {611 /* Enable writeback pipe and connect to MPCC */612 dc->hwss.enable_writeback(dc, &wb_info, context);613 }614 } else {615 /* Disable writeback pipe and disconnect from MPCC */616 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);617 }618 }619}620 621void dcn30_init_hw(struct dc *dc)622{623 struct abm **abms = dc->res_pool->multiple_abms;624 struct dce_hwseq *hws = dc->hwseq;625 struct dc_bios *dcb = dc->ctx->dc_bios;626 struct resource_pool *res_pool = dc->res_pool;627 int i;628 int edp_num;629 uint32_t backlight = MAX_BACKLIGHT_LEVEL;630 uint32_t user_level = MAX_BACKLIGHT_LEVEL;631 632 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)633 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);634 635 // Initialize the dccg636 if (res_pool->dccg->funcs->dccg_init)637 res_pool->dccg->funcs->dccg_init(res_pool->dccg);638 639 if (!dcb->funcs->is_accelerated_mode(dcb)) {640 hws->funcs.bios_golden_init(dc);641 hws->funcs.disable_vga(dc->hwseq);642 }643 644 if (dc->debug.enable_mem_low_power.bits.dmcu) {645 // Force ERAM to shutdown if DMCU is not enabled646 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {647 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);648 }649 }650 651 // Set default OPTC memory power states652 if (dc->debug.enable_mem_low_power.bits.optc) {653 // Shutdown when unassigned and light sleep in VBLANK654 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);655 }656 657 if (dc->debug.enable_mem_low_power.bits.vga) {658 // Power down VGA memory659 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);660 }661 662 if (dc->ctx->dc_bios->fw_info_valid) {663 res_pool->ref_clocks.xtalin_clock_inKhz =664 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;665 666 if (res_pool->hubbub) {667 668 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,669 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,670 &res_pool->ref_clocks.dccg_ref_clock_inKhz);671 672 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,673 res_pool->ref_clocks.dccg_ref_clock_inKhz,674 &res_pool->ref_clocks.dchub_ref_clock_inKhz);675 } else {676 // Not all ASICs have DCCG sw component677 res_pool->ref_clocks.dccg_ref_clock_inKhz =678 res_pool->ref_clocks.xtalin_clock_inKhz;679 res_pool->ref_clocks.dchub_ref_clock_inKhz =680 res_pool->ref_clocks.xtalin_clock_inKhz;681 }682 } else683 ASSERT_CRITICAL(false);684 685 for (i = 0; i < dc->link_count; i++) {686 /* Power up AND update implementation according to the687 * required signal (which may be different from the688 * default signal on connector).689 */690 struct dc_link *link = dc->links[i];691 692 link->link_enc->funcs->hw_init(link->link_enc);693 694 /* Check for enabled DIG to identify enabled display */695 if (link->link_enc->funcs->is_dig_enabled &&696 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {697 link->link_status.link_active = true;698 if (link->link_enc->funcs->fec_is_active &&699 link->link_enc->funcs->fec_is_active(link->link_enc))700 link->fec_state = dc_link_fec_enabled;701 }702 }703 704 /* we want to turn off all dp displays before doing detection */705 dc->link_srv->blank_all_dp_displays(dc);706 707 if (hws->funcs.enable_power_gating_plane)708 hws->funcs.enable_power_gating_plane(dc->hwseq, true);709 710 /* If taking control over from VBIOS, we may want to optimize our first711 * mode set, so we need to skip powering down pipes until we know which712 * pipes we want to use.713 * Otherwise, if taking control is not possible, we need to power714 * everything down.715 */716 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {717 hws->funcs.init_pipes(dc, dc->current_state);718 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)719 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,720 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);721 }722 723 /* In headless boot cases, DIG may be turned724 * on which causes HW/SW discrepancies.725 * To avoid this, power down hardware on boot726 * if DIG is turned on and seamless boot not enabled727 */728 if (!dc->config.seamless_boot_edp_requested) {729 struct dc_link *edp_links[MAX_NUM_EDP];730 struct dc_link *edp_link = NULL;731 732 dc_get_edp_links(dc, edp_links, &edp_num);733 if (edp_num)734 edp_link = edp_links[0];735 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&736 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&737 dc->hwss.edp_backlight_control &&738 hws->funcs.power_down &&739 dc->hwss.edp_power_control) {740 dc->hwss.edp_backlight_control(edp_link, false);741 hws->funcs.power_down(dc);742 dc->hwss.edp_power_control(edp_link, false);743 } else {744 for (i = 0; i < dc->link_count; i++) {745 struct dc_link *link = dc->links[i];746 747 if (link->link_enc->funcs->is_dig_enabled &&748 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&749 hws->funcs.power_down) {750 hws->funcs.power_down(dc);751 break;752 }753 754 }755 }756 }757 758 for (i = 0; i < res_pool->audio_count; i++) {759 struct audio *audio = res_pool->audios[i];760 761 audio->funcs->hw_init(audio);762 }763 764 for (i = 0; i < dc->link_count; i++) {765 struct dc_link *link = dc->links[i];766 767 if (link->panel_cntl) {768 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);769 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;770 }771 }772 773 for (i = 0; i < dc->res_pool->pipe_count; i++) {774 if (abms[i] != NULL)775 abms[i]->funcs->abm_init(abms[i], backlight, user_level);776 }777 778 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/779 REG_WRITE(DIO_MEM_PWR_CTRL, 0);780 781 if (!dc->debug.disable_clock_gate) {782 /* enable all DCN clock gating */783 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);784 785 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);786 787 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);788 }789 790 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)791 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);792 793 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)794 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);795 796 //if softmax is enabled then hardmax will be set by a different call797 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&798 !dc->clk_mgr->dc_mode_softmax_enabled)799 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);800 801 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)802 dc->res_pool->hubbub->funcs->force_pstate_change_control(803 dc->res_pool->hubbub, false, false);804 if (dc->res_pool->hubbub->funcs->init_crb)805 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);806 807 // Get DMCUB capabilities808 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);809 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;810 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;811}812 813void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)814{815 if (pipe_ctx == NULL)816 return;817 818 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {819 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(820 pipe_ctx->stream_res.stream_enc,821 enable);822 823 /* Wait for two frame to make sure AV mute is sent out */824 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {825 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);826 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);827 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);828 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);829 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);830 }831 }832}833 834void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)835{836 bool is_hdmi_tmds;837 bool is_dp;838 839 ASSERT(pipe_ctx->stream);840 841 if (pipe_ctx->stream_res.stream_enc == NULL)842 return; /* this is not root pipe */843 844 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);845 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);846 847 if (!is_hdmi_tmds && !is_dp)848 return;849 850 if (is_hdmi_tmds)851 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(852 pipe_ctx->stream_res.stream_enc,853 &pipe_ctx->stream_res.encoder_info_frame);854 else {855 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)856 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(857 pipe_ctx->stream_res.stream_enc,858 &pipe_ctx->stream_res.encoder_info_frame);859 860 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(861 pipe_ctx->stream_res.stream_enc,862 &pipe_ctx->stream_res.encoder_info_frame);863 }864}865 866void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)867{868 struct dc_stream_state *stream = pipe_ctx->stream;869 struct hubp *hubp = pipe_ctx->plane_res.hubp;870 bool enable = false;871 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;872 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)873 ? dmdata_dp874 : dmdata_hdmi;875 876 /* if using dynamic meta, don't set up generic infopackets */877 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {878 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;879 enable = true;880 }881 882 if (!hubp)883 return;884 885 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)886 return;887 888 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,889 hubp->inst, mode);890}891 892bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)893{894 union dmub_rb_cmd cmd;895 uint32_t tmr_delay = 0, tmr_scale = 0;896 struct dc_cursor_attributes cursor_attr = {0};897 bool cursor_cache_enable = false;898 struct dc_stream_state *stream = NULL;899 struct dc_plane_state *plane = NULL;900 901 if (!dc->ctx->dmub_srv)902 return false;903 904 if (enable) {905 if (dc->current_state) {906 int i;907 908 /* First, check no-memory-requests case */909 for (i = 0; i < dc->current_state->stream_count; i++) {910 if (dc->current_state->stream_status[i].plane_count)911 /* Fail eligibility on a visible stream */912 break;913 }914 915 if (i == dc->current_state->stream_count) {916 /* Enable no-memory-requests case */917 memset(&cmd, 0, sizeof(cmd));918 cmd.mall.header.type = DMUB_CMD__MALL;919 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;920 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);921 922 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);923 924 return true;925 }926 927 stream = dc->current_state->streams[0];928 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);929 930 if (!stream || !plane)931 return false;932 933 if (stream && plane) {934 cursor_cache_enable = stream->cursor_position.enable &&935 plane->address.grph.cursor_cache_addr.quad_part;936 cursor_attr = stream->cursor_attributes;937 }938 939 /*940 * Second, check MALL eligibility941 *942 * single display only, single surface only, 8 and 16 bit formats only, no VM,943 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW944 *945 * TODO: When we implement multi-display, PSR displays will be allowed if there is946 * a non-PSR display present, since in that case we can't do D0i3.2947 */948 if (dc->current_state->stream_count == 1 &&949 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&950 dc->current_state->stream_status[0].plane_count == 1 &&951 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&952 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&953 plane->address.page_table_base.quad_part == 0 &&954 dc->hwss.does_plane_fit_in_mall &&955 dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,956 plane->plane_size.surface_size.height, plane->format,957 cursor_cache_enable ? &cursor_attr : NULL)) {958 unsigned int v_total = stream->adjust.v_total_max ?959 stream->adjust.v_total_max : stream->timing.v_total;960 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *961 100LL, (v_total * stream->timing.h_total));962 963 /*964 * one frame time in microsec:965 * Delay_Us = 1000000 / refresh966 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period967 *968 * one frame time modified by 'additional timer percent' (p):969 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100970 * = dynamic_delay_us * (1 + p / 100)971 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100972 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)973 *974 * formula for timer duration based on parameters, from regspec:975 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale976 *977 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale978 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly979 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64980 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64981 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64982 *983 * need to round up the result of the division before the subtraction984 */985 unsigned int denom = refresh_hz * 6528;986 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;987 988 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *989 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),990 denom) - 64LL;991 992 /* In some cases the stutter period is really big (tiny modes) in these993 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()994 *995 * We can check if stutter_period is more than 1/10th the frame time to996 * consider if we can actually meet the range of hysteresis timer997 */998 if (stutter_period > 100000/refresh_hz)999 return false;1000 1001 /* scale should be increased until it fits into 6 bits */1002 while (tmr_delay & ~0x3F) {1003 tmr_scale++;1004 1005 if (tmr_scale > 3) {1006 /* Delay exceeds range of hysteresis timer */1007 ASSERT(false);1008 return false;1009 }1010 1011 denom *= 2;1012 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *1013 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),1014 denom) - 64LL;1015 }1016 1017 /* Copy HW cursor */1018 if (cursor_cache_enable) {1019 memset(&cmd, 0, sizeof(cmd));1020 cmd.mall.header.type = DMUB_CMD__MALL;1021 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;1022 cmd.mall.header.payload_bytes =1023 sizeof(cmd.mall) - sizeof(cmd.mall.header);1024 1025 switch (cursor_attr.color_format) {1026 case CURSOR_MODE_MONO:1027 cmd.mall.cursor_bpp = 2;1028 break;1029 case CURSOR_MODE_COLOR_1BIT_AND:1030 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:1031 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:1032 cmd.mall.cursor_bpp = 32;1033 break;1034 1035 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:1036 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:1037 cmd.mall.cursor_bpp = 64;1038 break;1039 }1040 1041 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;1042 cmd.mall.cursor_copy_dst.quad_part =1043 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;1044 cmd.mall.cursor_width = cursor_attr.width;1045 cmd.mall.cursor_height = cursor_attr.height;1046 cmd.mall.cursor_pitch = cursor_attr.pitch;1047 1048 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);1049 1050 /* Use copied cursor, and it's okay to not switch back */1051 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;1052 dc_stream_program_cursor_attributes(stream, &cursor_attr);1053 }1054 1055 /* Enable MALL */1056 memset(&cmd, 0, sizeof(cmd));1057 cmd.mall.header.type = DMUB_CMD__MALL;1058 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;1059 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);1060 cmd.mall.tmr_delay = tmr_delay;1061 cmd.mall.tmr_scale = tmr_scale;1062 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;1063 1064 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);1065 1066 return true;1067 }1068 }1069 1070 /* No applicable optimizations */1071 return false;1072 }1073 1074 /* Disable MALL */1075 memset(&cmd, 0, sizeof(cmd));1076 cmd.mall.header.type = DMUB_CMD__MALL;1077 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;1078 cmd.mall.header.payload_bytes =1079 sizeof(cmd.mall) - sizeof(cmd.mall.header);1080 1081 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);1082 1083 return true;1084}1085 1086bool dcn30_does_plane_fit_in_mall(struct dc *dc,1087 unsigned int pitch,1088 unsigned int height,1089 enum surface_pixel_format format,1090 struct dc_cursor_attributes *cursor_attr)1091{1092 // add meta size?1093 unsigned int surface_size = pitch * height *1094 (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);1095 unsigned int mall_size = dc->caps.mall_size_total;1096 unsigned int cursor_size = 0;1097 1098 if (dc->debug.mall_size_override)1099 mall_size = 1024 * 1024 * dc->debug.mall_size_override;1100 1101 if (cursor_attr) {1102 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;1103 1104 switch (cursor_attr->color_format) {1105 case CURSOR_MODE_MONO:1106 cursor_size /= 2;1107 break;1108 case CURSOR_MODE_COLOR_1BIT_AND:1109 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:1110 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:1111 cursor_size *= 4;1112 break;1113 1114 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:1115 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:1116 cursor_size *= 8;1117 break;1118 }1119 }1120 1121 return (surface_size + cursor_size) < mall_size;1122}1123 1124void dcn30_hardware_release(struct dc *dc)1125{1126 bool subvp_in_use = false;1127 uint32_t i;1128 1129 dc_dmub_srv_p_state_delegate(dc, false, NULL);1130 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);1131 1132 /* SubVP treated the same way as FPO. If driver disable and1133 * we are using a SubVP config, disable and force on DCN side1134 * to prevent P-State hang on driver enable.1135 */1136 for (i = 0; i < dc->res_pool->pipe_count; i++) {1137 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];1138 1139 if (!pipe->stream)1140 continue;1141 1142 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {1143 subvp_in_use = true;1144 break;1145 }1146 }1147 /* If pstate unsupported, or still supported1148 * by firmware, force it supported by dcn1149 */1150 if (dc->current_state)1151 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||1152 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&1153 dc->res_pool->hubbub->funcs->force_pstate_change_control)1154 dc->res_pool->hubbub->funcs->force_pstate_change_control(1155 dc->res_pool->hubbub, true, true);1156}1157 1158void dcn30_set_disp_pattern_generator(const struct dc *dc,1159 struct pipe_ctx *pipe_ctx,1160 enum controller_dp_test_pattern test_pattern,1161 enum controller_dp_color_space color_space,1162 enum dc_color_depth color_depth,1163 const struct tg_color *solid_color,1164 int width, int height, int offset)1165{1166 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,1167 color_space, color_depth, solid_color, width, height, offset);1168}1169 1170void dcn30_prepare_bandwidth(struct dc *dc,1171 struct dc_state *context)1172{1173 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {1174 dc->optimized_required = true;1175 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;1176 }1177 1178 if (dc->clk_mgr->dc_mode_softmax_enabled)1179 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&1180 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)1181 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);1182 1183 dcn20_prepare_bandwidth(dc, context);1184 1185 if (!dc->clk_mgr->clks.fw_based_mclk_switching)1186 dc_dmub_srv_p_state_delegate(dc, false, context);1187}1188