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1/*2 * Copyright 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26 27#include "dm_services.h"28#include "dm_helpers.h"29#include "core_types.h"30#include "resource.h"31#include "dccg.h"32#include "dce/dce_hwseq.h"33#include "dcn30/dcn30_cm_common.h"34#include "reg_helper.h"35#include "abm.h"36#include "hubp.h"37#include "dchubbub.h"38#include "timing_generator.h"39#include "opp.h"40#include "ipp.h"41#include "mpc.h"42#include "mcif_wb.h"43#include "dc_dmub_srv.h"44#include "link_hwss.h"45#include "dpcd_defs.h"46#include "dcn32_hwseq.h"47#include "clk_mgr.h"48#include "dsc.h"49#include "dcn20/dcn20_optc.h"50#include "dce/dmub_hw_lock_mgr.h"51#include "dcn32/dcn32_resource.h"52#include "link.h"53#include "../dcn20/dcn20_hwseq.h"54#include "dc_state_priv.h"55 56#define DC_LOGGER_INIT(logger)57 58#define CTX \59 hws->ctx60#define REG(reg)\61 hws->regs->reg62#define DC_LOGGER \63 dc->ctx->logger64 65#undef FN66#define FN(reg_name, field_name) \67 hws->shifts->field_name, hws->masks->field_name68 69void dcn32_dsc_pg_control(70 struct dce_hwseq *hws,71 unsigned int dsc_inst,72 bool power_on)73{74 uint32_t power_gate = power_on ? 0 : 1;75 uint32_t pwr_status = power_on ? 0 : 2;76 uint32_t org_ip_request_cntl = 0;77 struct dc *dc = hws->ctx->dc;78 79 if (dc->debug.disable_dsc_power_gate)80 return;81 82 if (!dc->debug.enable_double_buffered_dsc_pg_support)83 return;84 85 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);86 if (org_ip_request_cntl == 0)87 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);88 89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);90 switch (dsc_inst) {91 case 0: /* DSC0 */92 REG_UPDATE(DOMAIN16_PG_CONFIG,93 DOMAIN_POWER_GATE, power_gate);94 95 REG_WAIT(DOMAIN16_PG_STATUS,96 DOMAIN_PGFSM_PWR_STATUS, pwr_status,97 1, 1000);98 break;99 case 1: /* DSC1 */100 REG_UPDATE(DOMAIN17_PG_CONFIG,101 DOMAIN_POWER_GATE, power_gate);102 103 REG_WAIT(DOMAIN17_PG_STATUS,104 DOMAIN_PGFSM_PWR_STATUS, pwr_status,105 1, 1000);106 break;107 case 2: /* DSC2 */108 REG_UPDATE(DOMAIN18_PG_CONFIG,109 DOMAIN_POWER_GATE, power_gate);110 111 REG_WAIT(DOMAIN18_PG_STATUS,112 DOMAIN_PGFSM_PWR_STATUS, pwr_status,113 1, 1000);114 break;115 case 3: /* DSC3 */116 REG_UPDATE(DOMAIN19_PG_CONFIG,117 DOMAIN_POWER_GATE, power_gate);118 119 REG_WAIT(DOMAIN19_PG_STATUS,120 DOMAIN_PGFSM_PWR_STATUS, pwr_status,121 1, 1000);122 break;123 default:124 BREAK_TO_DEBUGGER();125 break;126 }127 128 if (org_ip_request_cntl == 0)129 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);130}131 132 133void dcn32_enable_power_gating_plane(134 struct dce_hwseq *hws,135 bool enable)136{137 bool force_on = true; /* disable power gating */138 uint32_t org_ip_request_cntl = 0;139 140 if (enable)141 force_on = false;142 143 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);144 if (org_ip_request_cntl == 0)145 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);146 147 /* DCHUBP0/1/2/3 */148 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);149 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);150 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);151 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);152 153 /* DCS0/1/2/3 */154 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);155 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);156 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);157 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);158 159 if (org_ip_request_cntl == 0)160 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);161}162 163void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)164{165 uint32_t power_gate = power_on ? 0 : 1;166 uint32_t pwr_status = power_on ? 0 : 2;167 168 if (hws->ctx->dc->debug.disable_hubp_power_gate)169 return;170 171 if (REG(DOMAIN0_PG_CONFIG) == 0)172 return;173 174 switch (hubp_inst) {175 case 0:176 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);177 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);178 break;179 case 1:180 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);181 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);182 break;183 case 2:184 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);185 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);186 break;187 case 3:188 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);189 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);190 break;191 default:192 BREAK_TO_DEBUGGER();193 break;194 }195}196 197static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)198{199 int i;200 201 /* First, check no-memory-request case */202 for (i = 0; i < dc->current_state->stream_count; i++) {203 if ((dc->current_state->stream_status[i].plane_count) &&204 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))205 /* Fail eligibility on a visible stream */206 break;207 }208 209 if (i == dc->current_state->stream_count)210 return true;211 212 return false;213}214 215 216/* This function loops through every surface that needs to be cached in CAB for SS,217 * and calculates the total number of ways required to store all surfaces (primary,218 * meta, cursor).219 */220static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)221{222 int i;223 uint32_t num_ways = 0;224 uint32_t mall_ss_size_bytes = 0;225 226 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;227 // TODO add additional logic for PSR active stream exclusion optimization228 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;229 230 // Include cursor size for CAB allocation231 for (i = 0; i < dc->res_pool->pipe_count; i++) {232 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];233 234 if (!pipe->stream || !pipe->plane_state)235 continue;236 237 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);238 }239 240 // Convert number of cache lines required to number of ways241 if (dc->debug.force_mall_ss_num_ways > 0) {242 num_ways = dc->debug.force_mall_ss_num_ways;243 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {244 num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);245 } else {246 num_ways = 0;247 }248 249 return num_ways;250}251 252bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)253{254 union dmub_rb_cmd cmd;255 uint8_t i;256 uint32_t ways;257 int j;258 bool mall_ss_unsupported = false;259 struct dc_plane_state *plane = NULL;260 261 if (!dc->ctx->dmub_srv)262 return false;263 264 for (i = 0; i < dc->current_state->stream_count; i++) {265 /* MALL SS messaging is not supported with PSR at this time */266 if (dc->current_state->streams[i] != NULL &&267 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&268 (dc->current_state->stream_count > 1 || (!dc->current_state->streams[i]->dpms_off &&269 dc->current_state->stream_status[i].plane_count > 0)))270 return false;271 }272 273 if (enable) {274 /* 1. Check no memory request case for CAB.275 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message276 */277 if (dcn32_check_no_memory_request_for_cab(dc)) {278 /* Enable no-memory-requests case */279 memset(&cmd, 0, sizeof(cmd));280 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;281 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;282 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);283 284 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);285 286 return true;287 }288 289 /* 2. Check if all surfaces can fit in CAB.290 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message291 * and configure HUBP's to fetch from MALL292 */293 ways = dcn32_calculate_cab_allocation(dc, dc->current_state);294 295 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,296 * or TMZ surface, don't try to enter MALL.297 */298 for (i = 0; i < dc->current_state->stream_count; i++) {299 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {300 plane = dc->current_state->stream_status[i].plane_states[j];301 302 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||303 plane->address.tmz_surface) {304 mall_ss_unsupported = true;305 break;306 }307 }308 if (mall_ss_unsupported)309 break;310 }311 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {312 memset(&cmd, 0, sizeof(cmd));313 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;314 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;315 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);316 cmd.cab.cab_alloc_ways = (uint8_t)ways;317 318 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);319 320 return true;321 }322 323 return false;324 }325 326 /* Disable CAB */327 memset(&cmd, 0, sizeof(cmd));328 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;329 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;330 cmd.cab.header.payload_bytes =331 sizeof(cmd.cab) - sizeof(cmd.cab.header);332 333 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);334 335 return true;336}337 338/* Send DMCUB message with SubVP pipe info339 * - For each pipe in context, populate payload with required SubVP information340 * if the pipe is using SubVP for MCLK switch341 * - This function must be called while the DMUB HW lock is acquired by driver342 */343void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)344{345 int i;346 bool enable_subvp = false;347 348 if (!dc->ctx || !dc->ctx->dmub_srv)349 return;350 351 for (i = 0; i < dc->res_pool->pipe_count; i++) {352 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];353 354 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {355 // There is at least 1 SubVP pipe, so enable SubVP356 enable_subvp = true;357 break;358 }359 }360 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);361}362 363/* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:364 * 1. Any full update for any SubVP main pipe365 * 2. Any immediate flip for any SubVP pipe366 * 3. Any flip for DRR pipe367 * 4. If SubVP was previously in use (i.e. in old context)368 */369void dcn32_subvp_pipe_control_lock(struct dc *dc,370 struct dc_state *context,371 bool lock,372 bool should_lock_all_pipes,373 struct pipe_ctx *top_pipe_to_program,374 bool subvp_prev_use)375{376 unsigned int i = 0;377 bool subvp_immediate_flip = false;378 bool subvp_in_use = false;379 struct pipe_ctx *pipe;380 enum mall_stream_type pipe_mall_type = SUBVP_NONE;381 382 for (i = 0; i < dc->res_pool->pipe_count; i++) {383 pipe = &context->res_ctx.pipe_ctx[i];384 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);385 386 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {387 subvp_in_use = true;388 break;389 }390 }391 392 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {393 if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&394 top_pipe_to_program->plane_state->flip_immediate)395 subvp_immediate_flip = true;396 }397 398 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.399 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {400 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };401 402 if (!lock) {403 for (i = 0; i < dc->res_pool->pipe_count; i++) {404 pipe = &context->res_ctx.pipe_ctx[i];405 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&406 should_lock_all_pipes)407 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);408 }409 }410 411 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;412 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;413 hw_lock_cmd.bits.lock = lock;414 hw_lock_cmd.bits.should_release = !lock;415 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);416 }417}418 419void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)420{421 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;422 bool lock = params->subvp_pipe_control_lock_fast_params.lock;423 bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;424 425 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.426 if (subvp_immediate_flip) {427 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };428 429 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;430 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;431 hw_lock_cmd.bits.lock = lock;432 hw_lock_cmd.bits.should_release = !lock;433 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);434 }435}436 437bool dcn32_set_mpc_shaper_3dlut(438 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)439{440 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;441 int mpcc_id = pipe_ctx->plane_res.hubp->inst;442 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;443 bool result = false;444 445 const struct pwl_params *shaper_lut = NULL;446 //get the shaper lut params447 if (stream->func_shaper) {448 if (stream->func_shaper->type == TF_TYPE_HWPWL)449 shaper_lut = &stream->func_shaper->pwl;450 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {451 cm_helper_translate_curve_to_hw_format(stream->ctx,452 stream->func_shaper,453 &dpp_base->shaper_params, true);454 shaper_lut = &dpp_base->shaper_params;455 }456 }457 458 if (stream->lut3d_func &&459 stream->lut3d_func->state.bits.initialized == 1) {460 461 result = mpc->funcs->program_3dlut(mpc,462 &stream->lut3d_func->lut_3d,463 mpcc_id);464 465 result = mpc->funcs->program_shaper(mpc,466 shaper_lut,467 mpcc_id);468 }469 470 return result;471}472 473bool dcn32_set_mcm_luts(474 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)475{476 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;477 int mpcc_id = pipe_ctx->plane_res.hubp->inst;478 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;479 bool result = true;480 const struct pwl_params *lut_params = NULL;481 482 // 1D LUT483 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)484 lut_params = &plane_state->blend_tf.pwl;485 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {486 result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,487 &dpp_base->regamma_params, false);488 if (!result)489 return result;490 491 lut_params = &dpp_base->regamma_params;492 }493 mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);494 lut_params = NULL;495 496 // Shaper497 if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)498 lut_params = &plane_state->in_shaper_func.pwl;499 else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {500 // TODO: dpp_base replace501 ASSERT(false);502 cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,503 &dpp_base->shaper_params, true);504 lut_params = &dpp_base->shaper_params;505 }506 507 mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);508 509 // 3D510 if (plane_state->lut3d_func.state.bits.initialized == 1)511 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);512 else513 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);514 515 return result;516}517 518bool dcn32_set_input_transfer_func(struct dc *dc,519 struct pipe_ctx *pipe_ctx,520 const struct dc_plane_state *plane_state)521{522 struct dce_hwseq *hws = dc->hwseq;523 struct mpc *mpc = dc->res_pool->mpc;524 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;525 526 enum dc_transfer_func_predefined tf;527 bool result = true;528 const struct pwl_params *params = NULL;529 530 if (mpc == NULL || plane_state == NULL)531 return false;532 533 tf = TRANSFER_FUNCTION_UNITY;534 535 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)536 tf = plane_state->in_transfer_func.tf;537 538 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);539 540 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)541 params = &plane_state->in_transfer_func.pwl;542 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&543 cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,544 &dpp_base->degamma_params, false))545 params = &dpp_base->degamma_params;546 547 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);548 549 if (pipe_ctx->stream_res.opp &&550 pipe_ctx->stream_res.opp->ctx &&551 hws->funcs.set_mcm_luts)552 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);553 554 return result;555}556 557bool dcn32_set_output_transfer_func(struct dc *dc,558 struct pipe_ctx *pipe_ctx,559 const struct dc_stream_state *stream)560{561 int mpcc_id = pipe_ctx->plane_res.hubp->inst;562 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;563 const struct pwl_params *params = NULL;564 bool ret = false;565 566 /* program OGAM or 3DLUT only for the top pipe*/567 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {568 /*program shaper and 3dlut in MPC*/569 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);570 if (ret == false && mpc->funcs->set_output_gamma) {571 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)572 params = &stream->out_transfer_func.pwl;573 else if (pipe_ctx->stream->out_transfer_func.type ==574 TF_TYPE_DISTRIBUTED_POINTS &&575 cm3_helper_translate_curve_to_hw_format(576 &stream->out_transfer_func,577 &mpc->blender_params, false))578 params = &mpc->blender_params;579 /* there are no ROM LUTs in OUTGAM */580 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)581 BREAK_TO_DEBUGGER();582 }583 }584 585 if (mpc->funcs->set_output_gamma)586 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);587 588 return ret;589}590 591/* Program P-State force value according to if pipe is using SubVP / FPO or not:592 * 1. Reset P-State force on all pipes first593 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)594 */595void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)596{597 int i;598 599 /* Unforce p-state for each pipe if it is not FPO or SubVP.600 * For FPO and SubVP, if it's already forced disallow, leave601 * it as disallow.602 */603 for (i = 0; i < dc->res_pool->pipe_count; i++) {604 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];605 struct hubp *hubp = pipe->plane_res.hubp;606 struct dc_stream_status *stream_status = NULL;607 608 if (pipe->stream)609 stream_status = dc_state_get_stream_status(context, pipe->stream);610 611 if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||612 (stream_status && stream_status->fpo_in_use))) {613 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)614 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);615 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)616 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);617 }618 }619 620 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.621 */622 for (i = 0; i < dc->res_pool->pipe_count; i++) {623 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];624 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];625 struct hubp *hubp = pipe->plane_res.hubp;626 struct dc_stream_status *stream_status = NULL;627 struct dc_stream_status *old_stream_status = NULL;628 629 /* Today for MED update type we do not call update clocks. However, for FPO630 * the assumption is that update clocks should be called to disable P-State631 * switch before any HW programming since FPO in FW and driver are not632 * synchronized. This causes an issue where on a MED update, an FPO P-State633 * switch could be taking place, then driver forces P-State disallow in the below634 * code and prevents FPO from completing the sequence. In this case we add a check635 * to avoid re-programming (and thus re-setting) the P-State force register by636 * only reprogramming if the pipe was not previously Subvp or FPO. The assumption637 * is that the P-State force register should be programmed correctly the first638 * time SubVP / FPO was enabled, so there's no need to update / reset it if the639 * pipe config has never exited SubVP / FPO.640 */641 if (pipe->stream)642 stream_status = dc_state_get_stream_status(context, pipe->stream);643 if (old_pipe->stream)644 old_stream_status = dc_state_get_stream_status(dc->current_state, old_pipe->stream);645 646 if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||647 (stream_status && stream_status->fpo_in_use)) &&648 (!old_pipe->stream || (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_MAIN &&649 (old_stream_status && !old_stream_status->fpo_in_use)))) {650 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)651 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);652 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)653 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);654 }655 }656}657 658/* Update MALL_SEL register based on if pipe / plane659 * is a phantom pipe, main pipe, and if using MALL660 * for SS.661 */662void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)663{664 int i;665 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);666 bool cache_cursor = false;667 668 for (i = 0; i < dc->res_pool->pipe_count; i++) {669 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];670 struct hubp *hubp = pipe->plane_res.hubp;671 672 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {673 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;674 675 switch (hubp->curs_attr.color_format) {676 case CURSOR_MODE_MONO:677 cursor_size /= 2;678 break;679 case CURSOR_MODE_COLOR_1BIT_AND:680 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:681 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:682 cursor_size *= 4;683 break;684 685 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:686 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:687 default:688 cursor_size *= 8;689 break;690 }691 692 if (cursor_size > 16384)693 cache_cursor = true;694 695 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {696 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);697 } else {698 // MALL not supported with Stereo3D699 hubp->funcs->hubp_update_mall_sel(hubp,700 num_ways <= dc->caps.cache_num_ways &&701 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&702 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&703 !pipe->plane_state->address.tmz_surface ? 2 : 0,704 cache_cursor);705 }706 }707 }708}709 710/* Program the sub-viewport pipe configuration after the main / phantom pipes711 * have been programmed in hardware.712 * 1. Update force P-State for all the main pipes (disallow P-state)713 * 2. Update MALL_SEL register714 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes715 */716void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)717{718 int i;719 struct dce_hwseq *hws = dc->hwseq;720 721 // Don't force p-state disallow -- can't block dummy p-state722 723 // Update MALL_SEL register for each pipe724 if (hws && hws->funcs.update_mall_sel)725 hws->funcs.update_mall_sel(dc, context);726 727 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes728 for (i = 0; i < dc->res_pool->pipe_count; i++) {729 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];730 struct hubp *hubp = pipe->plane_res.hubp;731 732 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {733 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases734 * - need to investigate single pipe MPO + SubVP case to735 * see if CURSOR_REQ_MODE will be back to 1 for SubVP736 * when it should be 0 for MPO737 */738 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)739 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);740 }741 }742}743 744static void dcn32_initialize_min_clocks(struct dc *dc)745{746 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;747 748 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;749 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;750 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;751 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;752 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;753 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;754 clocks->fclk_p_state_change_support = true;755 clocks->p_state_change_support = true;756 if (dc->debug.disable_boot_optimizations) {757 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;758 } else {759 /* Even though DPG_EN = 1 for the connected display, it still requires the760 * correct timing so we cannot set DISPCLK to min freq or it could cause761 * audio corruption. Read current DISPCLK from DENTIST and request the same762 * freq to ensure that the timing is valid and unchanged.763 */764 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);765 }766 767 dc->clk_mgr->funcs->update_clocks(768 dc->clk_mgr,769 dc->current_state,770 true);771}772 773void dcn32_init_hw(struct dc *dc)774{775 struct abm **abms = dc->res_pool->multiple_abms;776 struct dce_hwseq *hws = dc->hwseq;777 struct dc_bios *dcb = dc->ctx->dc_bios;778 struct resource_pool *res_pool = dc->res_pool;779 int i;780 int edp_num;781 uint32_t backlight = MAX_BACKLIGHT_LEVEL;782 uint32_t user_level = MAX_BACKLIGHT_LEVEL;783 784 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)785 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);786 787 // Initialize the dccg788 if (res_pool->dccg->funcs->dccg_init)789 res_pool->dccg->funcs->dccg_init(res_pool->dccg);790 791 if (!dcb->funcs->is_accelerated_mode(dcb)) {792 hws->funcs.bios_golden_init(dc);793 hws->funcs.disable_vga(dc->hwseq);794 }795 796 // Set default OPTC memory power states797 if (dc->debug.enable_mem_low_power.bits.optc) {798 // Shutdown when unassigned and light sleep in VBLANK799 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);800 }801 802 if (dc->debug.enable_mem_low_power.bits.vga) {803 // Power down VGA memory804 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);805 }806 807 if (dc->ctx->dc_bios->fw_info_valid) {808 res_pool->ref_clocks.xtalin_clock_inKhz =809 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;810 811 if (res_pool->hubbub) {812 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,813 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,814 &res_pool->ref_clocks.dccg_ref_clock_inKhz);815 816 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,817 res_pool->ref_clocks.dccg_ref_clock_inKhz,818 &res_pool->ref_clocks.dchub_ref_clock_inKhz);819 } else {820 // Not all ASICs have DCCG sw component821 res_pool->ref_clocks.dccg_ref_clock_inKhz =822 res_pool->ref_clocks.xtalin_clock_inKhz;823 res_pool->ref_clocks.dchub_ref_clock_inKhz =824 res_pool->ref_clocks.xtalin_clock_inKhz;825 }826 } else827 ASSERT_CRITICAL(false);828 829 for (i = 0; i < dc->link_count; i++) {830 /* Power up AND update implementation according to the831 * required signal (which may be different from the832 * default signal on connector).833 */834 struct dc_link *link = dc->links[i];835 836 link->link_enc->funcs->hw_init(link->link_enc);837 838 /* Check for enabled DIG to identify enabled display */839 if (link->link_enc->funcs->is_dig_enabled &&840 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {841 link->link_status.link_active = true;842 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;843 if (link->link_enc->funcs->fec_is_active &&844 link->link_enc->funcs->fec_is_active(link->link_enc))845 link->fec_state = dc_link_fec_enabled;846 }847 }848 849 /* enable_power_gating_plane before dsc_pg_control because850 * FORCEON = 1 with hw default value on bootup, resume from s3851 */852 if (hws->funcs.enable_power_gating_plane)853 hws->funcs.enable_power_gating_plane(dc->hwseq, true);854 855 /* we want to turn off all dp displays before doing detection */856 dc->link_srv->blank_all_dp_displays(dc);857 858 /* If taking control over from VBIOS, we may want to optimize our first859 * mode set, so we need to skip powering down pipes until we know which860 * pipes we want to use.861 * Otherwise, if taking control is not possible, we need to power862 * everything down.863 */864 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {865 /* Disable boot optimizations means power down everything including PHY, DIG,866 * and OTG (i.e. the boot is not optimized because we do a full power down).867 */868 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)869 dc->hwss.enable_accelerated_mode(dc, dc->current_state);870 else871 hws->funcs.init_pipes(dc, dc->current_state);872 873 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)874 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,875 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);876 877 dcn32_initialize_min_clocks(dc);878 879 /* On HW init, allow idle optimizations after pipes have been turned off.880 *881 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state882 * is reset (i.e. not in idle at the time hw init is called), but software state883 * still has idle_optimizations = true, so we must disable idle optimizations first884 * (i.e. set false), then re-enable (set true).885 */886 dc_allow_idle_optimizations(dc, false);887 dc_allow_idle_optimizations(dc, true);888 }889 890 /* In headless boot cases, DIG may be turned891 * on which causes HW/SW discrepancies.892 * To avoid this, power down hardware on boot893 * if DIG is turned on and seamless boot not enabled894 */895 if (!dc->config.seamless_boot_edp_requested) {896 struct dc_link *edp_links[MAX_NUM_EDP];897 struct dc_link *edp_link;898 899 dc_get_edp_links(dc, edp_links, &edp_num);900 if (edp_num) {901 for (i = 0; i < edp_num; i++) {902 edp_link = edp_links[i];903 if (edp_link->link_enc->funcs->is_dig_enabled &&904 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&905 dc->hwss.edp_backlight_control &&906 hws->funcs.power_down &&907 dc->hwss.edp_power_control) {908 dc->hwss.edp_backlight_control(edp_link, false);909 hws->funcs.power_down(dc);910 dc->hwss.edp_power_control(edp_link, false);911 }912 }913 } else {914 for (i = 0; i < dc->link_count; i++) {915 struct dc_link *link = dc->links[i];916 917 if (link->link_enc->funcs->is_dig_enabled &&918 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&919 hws->funcs.power_down) {920 hws->funcs.power_down(dc);921 break;922 }923 924 }925 }926 }927 928 for (i = 0; i < res_pool->audio_count; i++) {929 struct audio *audio = res_pool->audios[i];930 931 audio->funcs->hw_init(audio);932 }933 934 for (i = 0; i < dc->link_count; i++) {935 struct dc_link *link = dc->links[i];936 937 if (link->panel_cntl) {938 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);939 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;940 }941 }942 943 for (i = 0; i < dc->res_pool->pipe_count; i++) {944 if (abms[i] != NULL && abms[i]->funcs != NULL)945 abms[i]->funcs->abm_init(abms[i], backlight, user_level);946 }947 948 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/949 REG_WRITE(DIO_MEM_PWR_CTRL, 0);950 951 if (!dc->debug.disable_clock_gate) {952 /* enable all DCN clock gating */953 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);954 955 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);956 957 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);958 }959 960 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)961 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);962 963 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)964 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);965 966 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&967 !dc->clk_mgr->dc_mode_softmax_enabled)968 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);969 970 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)971 dc->res_pool->hubbub->funcs->force_pstate_change_control(972 dc->res_pool->hubbub, false, false);973 974 if (dc->res_pool->hubbub->funcs->init_crb)975 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);976 977 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)978 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);979 980 // Get DMCUB capabilities981 if (dc->ctx->dmub_srv) {982 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);983 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;984 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;985 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;986 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;987 988 /* for DCN401 testing only */989 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;990 if (dc->caps.dmub_caps.fams_ver == 2) {991 /* FAMS2 is enabled */992 dc->debug.fams2_config.bits.enable &= true;993 } else if (dc->ctx->dmub_srv->dmub->fw_version <994 DMUB_FW_VERSION(7, 0, 35)) {995 /* FAMS2 is disabled */996 dc->debug.fams2_config.bits.enable = false;997 if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) {998 /* update bounding box if FAMS2 disabled */999 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);1000 }1001 dc->debug.force_disable_subvp = true;1002 dc->debug.disable_fpo_optimizations = true;1003 }1004 }1005}1006 1007void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)1008{1009 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;1010 struct dc *dc = pipe_ctx->stream->ctx->dc;1011 struct dc_stream_state *stream = pipe_ctx->stream;1012 struct pipe_ctx *odm_pipe;1013 int opp_cnt = 1;1014 struct dccg *dccg = dc->res_pool->dccg;1015 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN1016 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a1017 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is1018 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings1019 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger1020 * this problem. We are implementing a workaround here to keep using dscclk1021 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e1022 * 48Mhz) pixel clock to avoid hitting this problem.1023 */1024 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&1025 stream->timing.pix_clk_100hz > 480000;1026 1027 ASSERT(dsc);1028 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)1029 opp_cnt++;1030 1031 if (enable) {1032 struct dsc_config dsc_cfg;1033 struct dsc_optc_config dsc_optc_cfg = {0};1034 enum optc_dsc_mode optc_dsc_mode;1035 struct dcn_dsc_state dsc_state = {0};1036 1037 if (!dsc) {1038 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);1039 return;1040 }1041 1042 if (dsc->funcs->dsc_read_state) {1043 dsc->funcs->dsc_read_state(dsc, &dsc_state);1044 if (!dsc_state.dsc_fw_en) {1045 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);1046 return;1047 }1048 }1049 1050 /* Enable DSC hw block */1051 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;1052 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;1053 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;1054 dsc_cfg.color_depth = stream->timing.display_color_depth;1055 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;1056 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;1057 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);1058 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;1059 1060 if (should_use_dto_dscclk)1061 dccg->funcs->set_dto_dscclk(dccg, dsc->inst);1062 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);1063 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);1064 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {1065 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;1066 1067 ASSERT(odm_dsc);1068 if (should_use_dto_dscclk)1069 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);1070 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);1071 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);1072 }1073 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;1074 /* Enable DSC in OPTC */1075 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);1076 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,1077 optc_dsc_mode,1078 dsc_optc_cfg.bytes_per_pixel,1079 dsc_optc_cfg.slice_width);1080 } else {1081 /* disable DSC in OPTC */1082 pipe_ctx->stream_res.tg->funcs->set_dsc_config(1083 pipe_ctx->stream_res.tg,1084 OPTC_DSC_DISABLED, 0, 0);1085 1086 /* only disconnect DSC block, DSC is disabled when OPP head pipe is reset */1087 dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);1088 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {1089 ASSERT(odm_pipe->stream_res.dsc);1090 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);1091 }1092 }1093}1094 1095/*1096* Given any pipe_ctx, return the total ODM combine factor, and optionally return1097* the OPPids which are used1098* */1099static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)1100{1101 unsigned int opp_count = 1;1102 struct pipe_ctx *odm_pipe;1103 1104 /* First get to the top pipe */1105 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)1106 ;1107 1108 /* First pipe is always used */1109 if (opp_instances)1110 opp_instances[0] = odm_pipe->stream_res.opp->inst;1111 1112 /* Find and count odm pipes, if any */1113 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {1114 if (opp_instances)1115 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;1116 opp_count++;1117 }1118 1119 return opp_count;1120}1121 1122void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)1123{1124 struct pipe_ctx *odm_pipe;1125 int opp_cnt = 0;1126 int opp_inst[MAX_PIPES] = {0};1127 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);1128 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);1129 1130 opp_cnt = get_odm_config(pipe_ctx, opp_inst);1131 1132 if (opp_cnt > 1)1133 pipe_ctx->stream_res.tg->funcs->set_odm_combine(1134 pipe_ctx->stream_res.tg,1135 opp_inst, opp_cnt,1136 odm_slice_width, last_odm_slice_width);1137 else1138 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(1139 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);1140 1141 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {1142 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(1143 odm_pipe->stream_res.opp,1144 true);1145 odm_pipe->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(1146 odm_pipe->stream_res.opp,1147 pipe_ctx->stream->timing.pixel_encoding,1148 resource_is_pipe_type(odm_pipe, OTG_MASTER));1149 }1150 1151 if (pipe_ctx->stream_res.dsc) {1152 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];1153 1154 dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);1155 1156 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */1157 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&1158 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {1159 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;1160 1161 /* disconnect DSC block from stream */1162 dsc->funcs->dsc_disconnect(dsc);1163 }1164 }1165 1166 if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))1167 /*1168 * blank pattern is generated by OPP, reprogram blank pattern1169 * due to OPP count change1170 */1171 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);1172}1173 1174unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)1175{1176 struct dc_stream_state *stream = pipe_ctx->stream;1177 unsigned int odm_combine_factor = 0;1178 bool two_pix_per_container = false;1179 1180 two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);1181 odm_combine_factor = get_odm_config(pipe_ctx, NULL);1182 1183 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {1184 *k1_div = PIXEL_RATE_DIV_BY_1;1185 *k2_div = PIXEL_RATE_DIV_BY_1;1186 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {1187 *k1_div = PIXEL_RATE_DIV_BY_1;1188 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)1189 *k2_div = PIXEL_RATE_DIV_BY_2;1190 else1191 *k2_div = PIXEL_RATE_DIV_BY_4;1192 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {1193 if (two_pix_per_container) {1194 *k1_div = PIXEL_RATE_DIV_BY_1;1195 *k2_div = PIXEL_RATE_DIV_BY_2;1196 } else {1197 *k1_div = PIXEL_RATE_DIV_BY_1;1198 *k2_div = PIXEL_RATE_DIV_BY_4;1199 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))1200 *k2_div = PIXEL_RATE_DIV_BY_2;1201 }1202 }1203 1204 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))1205 ASSERT(false);1206 1207 return odm_combine_factor;1208}1209 1210void dcn32_calculate_pix_rate_divider(1211 struct dc *dc,1212 struct dc_state *context,1213 const struct dc_stream_state *stream)1214{1215 struct dce_hwseq *hws = dc->hwseq;1216 struct pipe_ctx *pipe_ctx = NULL;1217 unsigned int k1_div = PIXEL_RATE_DIV_NA;1218 unsigned int k2_div = PIXEL_RATE_DIV_NA;1219 1220 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);1221 1222 if (pipe_ctx) {1223 1224 if (hws->funcs.calculate_dccg_k1_k2_values)1225 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);1226 1227 pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;1228 pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;1229 }1230}1231 1232void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)1233{1234 unsigned int i;1235 struct pipe_ctx *pipe = NULL;1236 bool otg_disabled[MAX_PIPES] = {false};1237 struct dc_state *dc_state = NULL;1238 1239 for (i = 0; i < dc->res_pool->pipe_count; i++) {1240 if (i <= current_pipe_idx) {1241 pipe = &context->res_ctx.pipe_ctx[i];1242 dc_state = context;1243 } else {1244 pipe = &dc->current_state->res_ctx.pipe_ctx[i];1245 dc_state = dc->current_state;1246 }1247 1248 if (!resource_is_pipe_type(pipe, OTG_MASTER))1249 continue;1250 1251 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))1252 && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {1253 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);1254 reset_sync_context_for_pipe(dc, context, i);1255 otg_disabled[i] = true;1256 }1257 }1258 1259 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);1260 1261 for (i = 0; i < dc->res_pool->pipe_count; i++) {1262 if (i <= current_pipe_idx)1263 pipe = &context->res_ctx.pipe_ctx[i];1264 else1265 pipe = &dc->current_state->res_ctx.pipe_ctx[i];1266 1267 if (otg_disabled[i]) {1268 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };1269 int opp_cnt = 1;1270 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);1271 int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);1272 struct pipe_ctx *odm_pipe;1273 1274 for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {1275 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;1276 opp_cnt++;1277 }1278 if (opp_cnt > 1)1279 pipe->stream_res.tg->funcs->set_odm_combine(1280 pipe->stream_res.tg,1281 opp_inst, opp_cnt,1282 odm_slice_width,1283 last_odm_slice_width);1284 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);1285 }1286 }1287 1288 dc_trigger_sync(dc, dc->current_state);1289}1290 1291void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,1292 struct dc_link_settings *link_settings)1293{1294 struct encoder_unblank_param params = {0};1295 struct dc_stream_state *stream = pipe_ctx->stream;1296 struct dc_link *link = stream->link;1297 struct dce_hwseq *hws = link->dc->hwseq;1298 struct pipe_ctx *odm_pipe;1299 1300 params.opp_cnt = 1;1301 params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;1302 1303 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)1304 params.opp_cnt++;1305 1306 /* only 3 items below are used by unblank */1307 params.timing = pipe_ctx->stream->timing;1308 1309 params.link_settings.link_rate = link_settings->link_rate;1310 1311 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {1312 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */1313 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(1314 pipe_ctx->stream_res.hpo_dp_stream_enc,1315 pipe_ctx->stream_res.tg->inst);1316 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {1317 if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||1318 params.opp_cnt > 1) {1319 params.timing.pix_clk_100hz /= 2;1320 params.pix_per_cycle = 2;1321 }1322 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(1323 pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);1324 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);1325 }1326 1327 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)1328 hws->funcs.edp_backlight_control(link, true);1329}1330 1331bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)1332{1333 struct dc *dc = pipe_ctx->stream->ctx->dc;1334 1335 if (!is_h_timing_divisible_by_2(pipe_ctx->stream))1336 return false;1337 1338 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&1339 dc->debug.enable_dp_dig_pixel_rate_div_policy)1340 return true;1341 return false;1342}1343 1344static void apply_symclk_on_tx_off_wa(struct dc_link *link)1345{1346 /* There are use cases where SYMCLK is referenced by OTG. For instance1347 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.1348 * However current link interface will power off PHY when disabling link1349 * output. This will turn off SYMCLK generated by PHY. The workaround is1350 * to identify such case where SYMCLK is still in use by OTG when we1351 * power off PHY. When this is detected, we will temporarily power PHY1352 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling1353 * program_pix_clk interface. When OTG is disabled, we will then power1354 * off PHY by calling disable link output again.1355 *1356 * In future dcn generations, we plan to rework transmitter control1357 * interface so that we could have an option to set SYMCLK ON TX OFF1358 * state in one step without this workaround1359 */1360 1361 struct dc *dc = link->ctx->dc;1362 struct pipe_ctx *pipe_ctx = NULL;1363 uint8_t i;1364 1365 if (link->phy_state.symclk_ref_cnts.otg > 0) {1366 for (i = 0; i < MAX_PIPES; i++) {1367 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];1368 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {1369 pipe_ctx->clock_source->funcs->program_pix_clk(1370 pipe_ctx->clock_source,1371 &pipe_ctx->stream_res.pix_clk_params,1372 dc->link_srv->dp_get_encoding_format(1373 &pipe_ctx->link_config.dp_link_settings),1374 &pipe_ctx->pll_settings);1375 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;1376 break;1377 }1378 }1379 }1380}1381 1382void dcn32_disable_link_output(struct dc_link *link,1383 const struct link_resource *link_res,1384 enum signal_type signal)1385{1386 struct dc *dc = link->ctx->dc;1387 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);1388 struct dmcu *dmcu = dc->res_pool->dmcu;1389 1390 if (signal == SIGNAL_TYPE_EDP &&1391 link->dc->hwss.edp_backlight_control &&1392 !link->skip_implict_edp_power_control)1393 link->dc->hwss.edp_backlight_control(link, false);1394 else if (dmcu != NULL && dmcu->funcs->lock_phy)1395 dmcu->funcs->lock_phy(dmcu);1396 1397 link_hwss->disable_link_output(link, link_res, signal);1398 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;1399 1400 if (signal == SIGNAL_TYPE_EDP &&1401 link->dc->hwss.edp_backlight_control &&1402 !link->skip_implict_edp_power_control)1403 link->dc->hwss.edp_power_control(link, false);1404 else if (dmcu != NULL && dmcu->funcs->lock_phy)1405 dmcu->funcs->unlock_phy(dmcu);1406 1407 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);1408 1409 apply_symclk_on_tx_off_wa(link);1410}1411 1412/* For SubVP the main pipe can have a viewport position change1413 * without a full update. In this case we must also update the1414 * viewport positions for the phantom pipe accordingly.1415 */1416void dcn32_update_phantom_vp_position(struct dc *dc,1417 struct dc_state *context,1418 struct pipe_ctx *phantom_pipe)1419{1420 uint32_t i;1421 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;1422 1423 for (i = 0; i < dc->res_pool->pipe_count; i++) {1424 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1425 1426 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&1427 dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {1428 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {1429 1430 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;1431 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;1432 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;1433 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;1434 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;1435 1436 phantom_pipe->plane_state->update_flags.bits.position_change = 1;1437 resource_build_scaling_params(phantom_pipe);1438 return;1439 }1440 }1441 }1442}1443 1444/* Treat the phantom pipe as if it needs to be fully enabled.1445 * If the pipe was previously in use but not phantom, it would1446 * have been disabled earlier in the sequence so we need to run1447 * the full enable sequence.1448 */1449void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)1450{1451 phantom_pipe->update_flags.raw = 0;1452 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {1453 phantom_pipe->update_flags.bits.enable = 1;1454 phantom_pipe->update_flags.bits.mpcc = 1;1455 phantom_pipe->update_flags.bits.dppclk = 1;1456 phantom_pipe->update_flags.bits.hubp_interdependent = 1;1457 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;1458 phantom_pipe->update_flags.bits.gamut_remap = 1;1459 phantom_pipe->update_flags.bits.scaler = 1;1460 phantom_pipe->update_flags.bits.viewport = 1;1461 phantom_pipe->update_flags.bits.det_size = 1;1462 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {1463 phantom_pipe->update_flags.bits.odm = 1;1464 phantom_pipe->update_flags.bits.global_sync = 1;1465 }1466 }1467}1468 1469bool dcn32_dsc_pg_status(1470 struct dce_hwseq *hws,1471 unsigned int dsc_inst)1472{1473 uint32_t pwr_status = 0;1474 1475 switch (dsc_inst) {1476 case 0: /* DSC0 */1477 REG_GET(DOMAIN16_PG_STATUS,1478 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);1479 break;1480 case 1: /* DSC1 */1481 1482 REG_GET(DOMAIN17_PG_STATUS,1483 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);1484 break;1485 case 2: /* DSC2 */1486 REG_GET(DOMAIN18_PG_STATUS,1487 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);1488 break;1489 case 3: /* DSC3 */1490 REG_GET(DOMAIN19_PG_STATUS,1491 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);1492 break;1493 default:1494 BREAK_TO_DEBUGGER();1495 break;1496 }1497 1498 return pwr_status == 0;1499}1500 1501void dcn32_update_dsc_pg(struct dc *dc,1502 struct dc_state *context,1503 bool safe_to_disable)1504{1505 struct dce_hwseq *hws = dc->hwseq;1506 int i;1507 1508 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {1509 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];1510 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);1511 1512 if (context->res_ctx.is_dsc_acquired[i]) {1513 if (!is_dsc_ungated) {1514 hws->funcs.dsc_pg_control(hws, dsc->inst, true);1515 }1516 } else if (safe_to_disable) {1517 if (is_dsc_ungated) {1518 hws->funcs.dsc_pg_control(hws, dsc->inst, false);1519 }1520 }1521 }1522}1523 1524void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)1525{1526 struct dce_hwseq *hws = dc->hwseq;1527 int i;1528 1529 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {1530 struct pipe_ctx *pipe_ctx_old =1531 &dc->current_state->res_ctx.pipe_ctx[i];1532 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];1533 1534 if (!pipe_ctx_old->stream)1535 continue;1536 1537 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)1538 continue;1539 1540 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)1541 continue;1542 1543 if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||1544 (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {1545 struct clock_source *old_clk = pipe_ctx_old->clock_source;1546 1547 if (hws->funcs.reset_back_end_for_pipe)1548 hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);1549 if (hws->funcs.enable_stream_gating)1550 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);1551 if (old_clk)1552 old_clk->funcs->cs_power_down(old_clk);1553 }1554 }1555}1556 1557void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)1558{1559 unsigned int i;1560 enum dc_status status = DC_OK;1561 struct dce_hwseq *hws = dc->hwseq;1562 1563 for (i = 0; i < dc->res_pool->pipe_count; i++) {1564 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1565 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];1566 1567 /* If an active, non-phantom pipe is being transitioned into a phantom1568 * pipe, wait for the double buffer update to complete first before we do1569 * ANY phantom pipe programming.1570 */1571 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&1572 old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {1573 old_pipe->stream_res.tg->funcs->wait_for_state(1574 old_pipe->stream_res.tg,1575 CRTC_STATE_VBLANK);1576 old_pipe->stream_res.tg->funcs->wait_for_state(1577 old_pipe->stream_res.tg,1578 CRTC_STATE_VACTIVE);1579 }1580 }1581 for (i = 0; i < dc->res_pool->pipe_count; i++) {1582 struct pipe_ctx *pipe_ctx_old =1583 &dc->current_state->res_ctx.pipe_ctx[i];1584 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];1585 1586 if (pipe_ctx->stream == NULL)1587 continue;1588 1589 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)1590 continue;1591 1592 if (pipe_ctx->stream == pipe_ctx_old->stream &&1593 pipe_ctx->stream->link->link_state_valid) {1594 continue;1595 }1596 1597 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))1598 continue;1599 1600 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)1601 continue;1602 1603 if (hws->funcs.apply_single_controller_ctx_to_hw)1604 status = hws->funcs.apply_single_controller_ctx_to_hw(1605 pipe_ctx,1606 context,1607 dc);1608 1609 ASSERT(status == DC_OK);1610 1611#ifdef CONFIG_DRM_AMD_DC_FP1612 if (hws->funcs.resync_fifo_dccg_dio)1613 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);1614#endif1615 }1616}1617 1618/* Blank pixel data during initialization */1619void dcn32_init_blank(1620 struct dc *dc,1621 struct timing_generator *tg)1622{1623 struct dce_hwseq *hws = dc->hwseq;1624 enum dc_color_space color_space;1625 struct tg_color black_color = {0};1626 struct output_pixel_processor *opp = NULL;1627 struct output_pixel_processor *bottom_opp = NULL;1628 uint32_t num_opps, opp_id_src0, opp_id_src1;1629 uint32_t otg_active_width = 0, otg_active_height = 0;1630 uint32_t i;1631 1632 /* program opp dpg blank color */1633 color_space = COLOR_SPACE_SRGB;1634 color_space_to_black_color(dc, color_space, &black_color);1635 1636 /* get the OTG active size */1637 tg->funcs->get_otg_active_size(tg,1638 &otg_active_width,1639 &otg_active_height);1640 1641 /* get the OPTC source */1642 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);1643 1644 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {1645 ASSERT(false);1646 return;1647 }1648 1649 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {1650 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {1651 opp = dc->res_pool->opps[i];1652 break;1653 }1654 }1655 1656 if (num_opps == 2) {1657 otg_active_width = otg_active_width / 2;1658 1659 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {1660 ASSERT(false);1661 return;1662 }1663 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {1664 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {1665 bottom_opp = dc->res_pool->opps[i];1666 break;1667 }1668 }1669 }1670 1671 if (opp && opp->funcs->opp_set_disp_pattern_generator)1672 opp->funcs->opp_set_disp_pattern_generator(1673 opp,1674 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,1675 CONTROLLER_DP_COLOR_SPACE_UDEFINED,1676 COLOR_DEPTH_UNDEFINED,1677 &black_color,1678 otg_active_width,1679 otg_active_height,1680 0);1681 1682 if (num_opps == 2) {1683 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {1684 bottom_opp->funcs->opp_set_disp_pattern_generator(1685 bottom_opp,1686 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,1687 CONTROLLER_DP_COLOR_SPACE_UDEFINED,1688 COLOR_DEPTH_UNDEFINED,1689 &black_color,1690 otg_active_width,1691 otg_active_height,1692 0);1693 hws->funcs.wait_for_blank_complete(bottom_opp);1694 }1695 }1696 1697 if (opp)1698 hws->funcs.wait_for_blank_complete(opp);1699}1700 1701void dcn32_blank_phantom(struct dc *dc,1702 struct timing_generator *tg,1703 int width,1704 int height)1705{1706 struct dce_hwseq *hws = dc->hwseq;1707 enum dc_color_space color_space;1708 struct tg_color black_color = {0};1709 struct output_pixel_processor *opp = NULL;1710 uint32_t num_opps, opp_id_src0, opp_id_src1;1711 uint32_t otg_active_width, otg_active_height;1712 uint32_t i;1713 1714 /* program opp dpg blank color */1715 color_space = COLOR_SPACE_SRGB;1716 color_space_to_black_color(dc, color_space, &black_color);1717 1718 otg_active_width = width;1719 otg_active_height = height;1720 1721 /* get the OPTC source */1722 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);1723 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);1724 1725 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {1726 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {1727 opp = dc->res_pool->opps[i];1728 break;1729 }1730 }1731 1732 if (opp && opp->funcs->opp_set_disp_pattern_generator)1733 opp->funcs->opp_set_disp_pattern_generator(1734 opp,1735 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,1736 CONTROLLER_DP_COLOR_SPACE_UDEFINED,1737 COLOR_DEPTH_UNDEFINED,1738 &black_color,1739 otg_active_width,1740 otg_active_height,1741 0);1742 1743 if (tg->funcs->is_tg_enabled(tg))1744 hws->funcs.wait_for_blank_complete(opp);1745}1746 1747/* phantom stream id's can change often, but can be identical between contexts.1748* This function checks for the condition the streams are identical to avoid1749* redundant pipe transitions.1750*/1751static bool is_subvp_phantom_topology_transition_seamless(1752 const struct dc_state *cur_ctx,1753 const struct dc_state *new_ctx,1754 const struct pipe_ctx *cur_pipe,1755 const struct pipe_ctx *new_pipe)1756{1757 enum mall_stream_type cur_pipe_type = dc_state_get_pipe_subvp_type(cur_ctx, cur_pipe);1758 enum mall_stream_type new_pipe_type = dc_state_get_pipe_subvp_type(new_ctx, new_pipe);1759 1760 const struct dc_stream_state *cur_paired_stream = dc_state_get_paired_subvp_stream(cur_ctx, cur_pipe->stream);1761 const struct dc_stream_state *new_paired_stream = dc_state_get_paired_subvp_stream(new_ctx, new_pipe->stream);1762 1763 return cur_pipe_type == SUBVP_PHANTOM &&1764 cur_pipe_type == new_pipe_type &&1765 cur_paired_stream && new_paired_stream &&1766 cur_paired_stream->stream_id == new_paired_stream->stream_id;1767}1768 1769bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,1770 const struct dc_state *cur_ctx,1771 const struct dc_state *new_ctx)1772{1773 int i;1774 const struct pipe_ctx *cur_pipe, *new_pipe;1775 bool is_seamless = true;1776 1777 for (i = 0; i < dc->res_pool->pipe_count; i++) {1778 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];1779 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];1780 1781 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||1782 resource_is_pipe_type(new_pipe, FREE_PIPE))1783 /* adding or removing free pipes is always seamless */1784 continue;1785 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {1786 if (resource_is_pipe_type(new_pipe, OTG_MASTER))1787 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id ||1788 is_subvp_phantom_topology_transition_seamless(cur_ctx, new_ctx, cur_pipe, new_pipe))1789 /* OTG master with the same stream is seamless */1790 continue;1791 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {1792 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {1793 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg)1794 /*1795 * OPP heads sharing the same timing1796 * generator is seamless1797 */1798 continue;1799 }1800 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {1801 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {1802 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)1803 /*1804 * DPP pipes sharing the same OPP head is1805 * seamless1806 */1807 continue;1808 }1809 }1810 1811 /*1812 * This pipe's transition doesn't fall under any seamless1813 * conditions1814 */1815 is_seamless = false;1816 break;1817 }1818 1819 return is_seamless;1820}1821 1822void dcn32_prepare_bandwidth(struct dc *dc,1823 struct dc_state *context)1824{1825 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;1826 /* Any transition into an FPO config should disable MCLK switching first to avoid1827 * driver and FW P-State synchronization issues.1828 */1829 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {1830 dc->optimized_required = true;1831 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;1832 }1833 1834 if (dc->clk_mgr->dc_mode_softmax_enabled)1835 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&1836 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)1837 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);1838 1839 dcn20_prepare_bandwidth(dc, context);1840 1841 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)1842 dc_dmub_srv_p_state_delegate(dc, false, context);1843 1844 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {1845 /* After disabling P-State, restore the original value to ensure we get the correct P-State1846 * on the next optimize.1847 */1848 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;1849 }1850}1851 1852void dcn32_interdependent_update_lock(struct dc *dc,1853 struct dc_state *context, bool lock)1854{1855 unsigned int i;1856 struct pipe_ctx *pipe;1857 struct timing_generator *tg;1858 1859 for (i = 0; i < dc->res_pool->pipe_count; i++) {1860 pipe = &context->res_ctx.pipe_ctx[i];1861 tg = pipe->stream_res.tg;1862 1863 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||1864 !tg->funcs->is_tg_enabled(tg) ||1865 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)1866 continue;1867 1868 if (lock)1869 dc->hwss.pipe_control_lock(dc, pipe, true);1870 else1871 dc->hwss.pipe_control_lock(dc, pipe, false);1872 }1873}1874 1875void dcn32_program_outstanding_updates(struct dc *dc,1876 struct dc_state *context)1877{1878 struct hubbub *hubbub = dc->res_pool->hubbub;1879 1880 /* update compbuf if required */1881 if (hubbub->funcs->program_compbuf_size)1882 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);1883}1884