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1// SPDX-License-Identifier: MIT2//3// Copyright 2024 Advanced Micro Devices, Inc.4 5#ifndef __DC_HWSS_DCN401_H__6#define __DC_HWSS_DCN401_H__7 8#include "inc/core_types.h"9#include "dc.h"10#include "dc_stream.h"11#include "hw_sequencer_private.h"12#include "dcn401/dcn401_dccg.h"13 14struct dc;15 16enum ips_ono_state {17 ONO_ON = 0,18 ONO_ON_IN_PROGRESS = 1,19 ONO_OFF = 2,20 ONO_OFF_IN_PROGRESS = 321};22 23struct ips_ono_region_state {24 /**25 * @desire_pwr_state: desired power state based on configured value26 */27 uint32_t desire_pwr_state;28 /**29 * @current_pwr_state: current power gate status30 */31 uint32_t current_pwr_state;32};33 34void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);35 36void dcn401_init_hw(struct dc *dc);37 38bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,39 const struct dc_plane_state *plane_state);40bool dcn401_set_output_transfer_func(struct dc *dc,41 struct pipe_ctx *pipe_ctx,42 const struct dc_stream_state *stream);43void dcn401_trigger_3dlut_dma_load(struct dc *dc,44 struct pipe_ctx *pipe_ctx);45void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,46 unsigned int *tmds_div);47enum dc_status dcn401_enable_stream_timing(48 struct pipe_ctx *pipe_ctx,49 struct dc_state *context,50 struct dc *dc);51void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);52void dcn401_populate_mcm_luts(struct dc *dc,53 struct pipe_ctx *pipe_ctx,54 struct dc_cm2_func_luts mcm_luts,55 bool lut_bank_a);56void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);57 58void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);59 60bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);61 62struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc,63 uint8_t region);64void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,65 const struct pipe_ctx *top_pipe_to_program);66 67void dcn401_prepare_bandwidth(struct dc *dc,68 struct dc_state *context);69 70void dcn401_optimize_bandwidth(71 struct dc *dc,72 struct dc_state *context);73 74void dcn401_fams2_global_control_lock(struct dc *dc,75 struct dc_state *context,76 bool lock);77void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);78void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params);79void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);80void dcn401_hardware_release(struct dc *dc);81void dcn401_update_odm(struct dc *dc, struct dc_state *context,82 struct pipe_ctx *otg_master);83void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);84void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);85void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);86void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);87#endif /* __DC_HWSS_DCN401_H__ */88