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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DC_HW_SEQUENCER_PRIVATE_H__27#define __DC_HW_SEQUENCER_PRIVATE_H__28 29#include "dc_types.h"30 31enum pipe_gating_control {32 PIPE_GATING_CONTROL_DISABLE = 0,33 PIPE_GATING_CONTROL_ENABLE,34 PIPE_GATING_CONTROL_INIT35};36 37struct dce_hwseq_wa {38 bool blnd_crtc_trigger;39 bool DEGVIDCN10_253;40 bool false_optc_underflow;41 bool DEGVIDCN10_254;42 bool DEGVIDCN21;43 bool disallow_self_refresh_during_multi_plane_transition;44 bool dp_hpo_and_otg_sequence;45 bool wait_hubpret_read_start_during_mpo_transition;46};47 48struct hwseq_wa_state {49 bool DEGVIDCN10_253_applied;50 bool disallow_self_refresh_during_multi_plane_transition_applied;51 unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;52};53 54struct pipe_ctx;55struct dc_state;56struct dc_stream_status;57struct dc_writeback_info;58struct dchub_init_data;59struct dc_static_screen_params;60struct resource_pool;61struct resource_context;62struct stream_resource;63struct dc_phy_addr_space_config;64struct dc_virtual_addr_space_config;65struct hubp;66struct dpp;67struct dce_hwseq;68struct timing_generator;69struct tg_color;70struct output_pixel_processor;71struct mpcc_blnd_cfg;72 73struct hwseq_private_funcs {74 75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);77 void (*init_pipes)(struct dc *dc, struct dc_state *context);78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);79 void (*plane_atomic_disconnect)(struct dc *dc,80 struct dc_state *state,81 struct pipe_ctx *pipe_ctx);82 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);83 bool (*set_input_transfer_func)(struct dc *dc,84 struct pipe_ctx *pipe_ctx,85 const struct dc_plane_state *plane_state);86 bool (*set_output_transfer_func)(struct dc *dc,87 struct pipe_ctx *pipe_ctx,88 const struct dc_stream_state *stream);89 void (*power_down)(struct dc *dc);90 void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,91 bool clock_gating);92 bool (*enable_display_power_gating)(struct dc *dc,93 uint8_t controller_id,94 struct dc_bios *dcb,95 enum pipe_gating_control power_gating);96 void (*blank_pixel_data)(struct dc *dc,97 struct pipe_ctx *pipe_ctx,98 bool blank);99 enum dc_status (*enable_stream_timing)(100 struct pipe_ctx *pipe_ctx,101 struct dc_state *context,102 struct dc *dc);103 void (*edp_backlight_control)(struct dc_link *link,104 bool enable);105 void (*setup_vupdate_interrupt)(struct dc *dc,106 struct pipe_ctx *pipe_ctx);107 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);108 void (*init_blank)(struct dc *dc, struct timing_generator *tg);109 void (*disable_vga)(struct dce_hwseq *hws);110 void (*bios_golden_init)(struct dc *dc);111 void (*plane_atomic_power_down)(struct dc *dc,112 struct dpp *dpp,113 struct hubp *hubp);114 void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);115 void (*enable_power_gating_plane)(struct dce_hwseq *hws,116 bool enable);117 void (*dpp_root_clock_control)(118 struct dce_hwseq *hws,119 unsigned int dpp_inst,120 bool clock_on);121 void (*dpstream_root_clock_control)(122 struct dce_hwseq *hws,123 unsigned int dpp_inst,124 bool clock_on);125 void (*physymclk_root_clock_control)(126 struct dce_hwseq *hws,127 unsigned int phy_inst,128 bool clock_on);129 void (*dpp_pg_control)(struct dce_hwseq *hws,130 unsigned int dpp_inst,131 bool power_on);132 void (*hubp_pg_control)(struct dce_hwseq *hws,133 unsigned int hubp_inst,134 bool power_on);135 void (*dsc_pg_control)(struct dce_hwseq *hws,136 unsigned int dsc_inst,137 bool power_on);138 bool (*dsc_pg_status)(struct dce_hwseq *hws,139 unsigned int dsc_inst);140 void (*update_odm)(struct dc *dc, struct dc_state *context,141 struct pipe_ctx *pipe_ctx);142 void (*program_all_writeback_pipes_in_tree)(struct dc *dc,143 const struct dc_stream_state *stream,144 struct dc_state *context);145 bool (*s0i3_golden_init_wa)(struct dc *dc);146 void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);147 void (*verify_allow_pstate_change_high)(struct dc *dc);148 void (*program_pipe)(struct dc *dc,149 struct pipe_ctx *pipe_ctx,150 struct dc_state *context);151 bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);152 void (*dccg_init)(struct dce_hwseq *hws);153 bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,154 const struct dc_plane_state *plane_state);155 bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,156 const struct dc_plane_state *plane_state);157 bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,158 const struct dc_plane_state *plane_state);159 void (*PLAT_58856_wa)(struct dc_state *context,160 struct pipe_ctx *pipe_ctx);161 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);162 void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,163 struct dc_state *context);164 void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);165 void (*update_force_pstate)(struct dc *dc, struct dc_state *context);166 void (*update_mall_sel)(struct dc *dc, struct dc_state *context);167 unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,168 unsigned int *k1_div,169 unsigned int *k2_div);170 void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,171 struct dc_state *context,172 unsigned int current_pipe_idx);173 enum dc_status (*apply_single_controller_ctx_to_hw)(174 struct pipe_ctx *pipe_ctx,175 struct dc_state *context,176 struct dc *dc);177 bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);178 void (*reset_back_end_for_pipe)(struct dc *dc,179 struct pipe_ctx *pipe_ctx,180 struct dc_state *context);181 void (*populate_mcm_luts)(struct dc *dc,182 struct pipe_ctx *pipe_ctx,183 struct dc_cm2_func_luts mcm_luts,184 bool lut_bank_a);185};186 187struct dce_hwseq {188 struct dc_context *ctx;189 const struct dce_hwseq_registers *regs;190 const struct dce_hwseq_shift *shifts;191 const struct dce_hwseq_mask *masks;192 struct dce_hwseq_wa wa;193 struct hwseq_wa_state wa_state;194 struct hwseq_private_funcs funcs;195 196 PHYSICAL_ADDRESS_LOC fb_base;197 PHYSICAL_ADDRESS_LOC fb_top;198 PHYSICAL_ADDRESS_LOC fb_offset;199 PHYSICAL_ADDRESS_LOC uma_top;200};201 202#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */203