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1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DAL_DCCG_H__27#define __DAL_DCCG_H__28 29#include "dc_types.h"30#include "hw_shared.h"31 32enum phyd32clk_clock_source {33 PHYD32CLKA,34 PHYD32CLKB,35 PHYD32CLKC,36 PHYD32CLKD,37 PHYD32CLKE,38 PHYD32CLKF,39 PHYD32CLKG,40};41 42enum physymclk_clock_source {43 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO.44 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.45 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.46};47 48enum streamclk_source {49 REFCLK, // Selects REFCLK as source for hdmistreamclk.50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk52};53 54enum dentist_dispclk_change_mode {55 DISPCLK_CHANGE_MODE_IMMEDIATE,56 DISPCLK_CHANGE_MODE_RAMPING,57};58 59struct dp_dto_params {60 int otg_inst;61 enum signal_type signal;62 enum streamclk_source clk_src;63 uint64_t pixclk_hz;64 uint64_t refclk_hz;65};66 67enum pixel_rate_div {68 PIXEL_RATE_DIV_BY_1 = 0,69 PIXEL_RATE_DIV_BY_2 = 1,70 PIXEL_RATE_DIV_BY_4 = 3,71 PIXEL_RATE_DIV_NA = 0xF72};73 74struct dccg {75 struct dc_context *ctx;76 const struct dccg_funcs *funcs;77 int pipe_dppclk_khz[MAX_PIPES];78 int ref_dppclk;79 bool dpp_clock_gated[MAX_PIPES];80 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */81 //int audio_dtbclk_khz;/* TODO needs to be removed */82 //int ref_dtbclk_khz;/* TODO needs to be removed */83};84 85struct dtbclk_dto_params {86 const struct dc_crtc_timing *timing;87 int otg_inst;88 int pixclk_khz;89 int req_audio_dtbclk_khz;90 int num_odm_segments;91 int ref_dtbclk_khz;92 bool is_hdmi;93};94 95struct dccg_funcs {96 void (*update_dpp_dto)(struct dccg *dccg,97 int dpp_inst,98 int req_dppclk);99 void (*get_dccg_ref_freq)(struct dccg *dccg,100 unsigned int xtalin_freq_inKhz,101 unsigned int *dccg_ref_freq_inKhz);102 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,103 bool en);104 void (*otg_add_pixel)(struct dccg *dccg,105 uint32_t otg_inst);106 void (*otg_drop_pixel)(struct dccg *dccg,107 uint32_t otg_inst);108 void (*dccg_init)(struct dccg *dccg);109 void (*set_dpstreamclk_root_clock_gating)(110 struct dccg *dccg,111 int dp_hpo_inst,112 bool enable);113 114 void (*set_dpstreamclk)(115 struct dccg *dccg,116 enum streamclk_source src,117 int otg_inst,118 int dp_hpo_inst);119 120 void (*enable_symclk32_se)(121 struct dccg *dccg,122 int hpo_se_inst,123 enum phyd32clk_clock_source phyd32clk);124 125 void (*disable_symclk32_se)(126 struct dccg *dccg,127 int hpo_se_inst);128 129 void (*enable_symclk32_le)(130 struct dccg *dccg,131 int hpo_le_inst,132 enum phyd32clk_clock_source phyd32clk);133 134 void (*disable_symclk32_le)(135 struct dccg *dccg,136 int hpo_le_inst);137 138 void (*set_symclk32_le_root_clock_gating)(139 struct dccg *dccg,140 int hpo_le_inst,141 bool enable);142 143 void (*set_physymclk)(144 struct dccg *dccg,145 int phy_inst,146 enum physymclk_clock_source clk_src,147 bool force_enable);148 149 void (*set_physymclk_root_clock_gating)(150 struct dccg *dccg,151 int phy_inst,152 bool enable);153 154 void (*set_dtbclk_dto)(155 struct dccg *dccg,156 const struct dtbclk_dto_params *params);157 158 void (*set_audio_dtbclk_dto)(159 struct dccg *dccg,160 const struct dtbclk_dto_params *params);161 162 void (*set_dispclk_change_mode)(163 struct dccg *dccg,164 enum dentist_dispclk_change_mode change_mode);165 166 void (*disable_dsc)(167 struct dccg *dccg,168 int inst);169 170 void (*enable_dsc)(171 struct dccg *dccg,172 int inst);173 174 void (*set_pixel_rate_div)(struct dccg *dccg,175 uint32_t otg_inst,176 enum pixel_rate_div k1,177 enum pixel_rate_div k2);178 179 void (*get_pixel_rate_div)(struct dccg *dccg,180 uint32_t otg_inst,181 uint32_t *div_factor1,182 uint32_t *div_factor2);183 184 void (*set_valid_pixel_rate)(185 struct dccg *dccg,186 int ref_dtbclk_khz,187 int otg_inst,188 int pixclk_khz);189 190 void (*trigger_dio_fifo_resync)(191 struct dccg *dccg);192 193 void (*dpp_root_clock_control)(194 struct dccg *dccg,195 unsigned int dpp_inst,196 bool clock_on);197 198 void (*enable_symclk_se)(199 struct dccg *dccg,200 uint32_t stream_enc_inst,201 uint32_t link_enc_inst);202 203 void (*disable_symclk_se)(204 struct dccg *dccg,205 uint32_t stream_enc_inst,206 uint32_t link_enc_inst);207 void (*set_dp_dto)(208 struct dccg *dccg,209 const struct dp_dto_params *params);210 void (*set_dtbclk_p_src)(211 struct dccg *dccg,212 enum streamclk_source src,213 uint32_t otg_inst);214 void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst);215 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);216 void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);217};218 219#endif //__DAL_DCCG_H__220