365 lines · c
1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DAL_HW_SHARED_H__27#define __DAL_HW_SHARED_H__28 29#include "os_types.h"30#include "fixed31_32.h"31#include "dc_hw_types.h"32 33/******************************************************************************34 * Data types shared between different Virtual HW blocks35 ******************************************************************************/36 37#define MAX_AUDIOS 738 39/**40 * @MAX_PIPES:41 *42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number43 * to be used inside loops and for determining array sizes.44 */45#define MAX_PIPES 646#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)47#define MAX_LINKS (MAX_PIPES * 2 +2)48#define MAX_DIG_LINK_ENCODERS 749#define MAX_DWB_PIPES 150#define MAX_HPO_DP2_ENCODERS 451#define MAX_HPO_DP2_LINK_ENCODERS 452 53struct gamma_curve {54 uint32_t offset;55 uint32_t segments_num;56};57 58struct curve_points {59 struct fixed31_32 x;60 struct fixed31_32 y;61 struct fixed31_32 offset;62 struct fixed31_32 slope;63 64 uint32_t custom_float_x;65 uint32_t custom_float_y;66 uint32_t custom_float_offset;67 uint32_t custom_float_slope;68};69 70struct curve_points3 {71 struct curve_points red;72 struct curve_points green;73 struct curve_points blue;74};75 76struct pwl_result_data {77 struct fixed31_32 red;78 struct fixed31_32 green;79 struct fixed31_32 blue;80 81 struct fixed31_32 delta_red;82 struct fixed31_32 delta_green;83 struct fixed31_32 delta_blue;84 85 uint32_t red_reg;86 uint32_t green_reg;87 uint32_t blue_reg;88 89 uint32_t delta_red_reg;90 uint32_t delta_green_reg;91 uint32_t delta_blue_reg;92};93 94struct dc_rgb {95 uint32_t red;96 uint32_t green;97 uint32_t blue;98};99 100struct tetrahedral_17x17x17 {101 struct dc_rgb lut0[1229];102 struct dc_rgb lut1[1228];103 struct dc_rgb lut2[1228];104 struct dc_rgb lut3[1228];105};106struct tetrahedral_9x9x9 {107 struct dc_rgb lut0[183];108 struct dc_rgb lut1[182];109 struct dc_rgb lut2[182];110 struct dc_rgb lut3[182];111};112 113struct tetrahedral_params {114 union {115 struct tetrahedral_17x17x17 tetrahedral_17;116 struct tetrahedral_9x9x9 tetrahedral_9;117 };118 bool use_tetrahedral_9;119 bool use_12bits;120 121};122 123/* arr_curve_points - regamma regions/segments specification124 * arr_points - beginning and end point specified separately (only one on DCE)125 * corner_points - beginning and end point for all 3 colors (DCN)126 * rgb_resulted - final curve127 */128struct pwl_params {129 struct gamma_curve arr_curve_points[34];130 union {131 struct curve_points arr_points[2];132 struct curve_points3 corner_points[2];133 };134 struct pwl_result_data rgb_resulted[256 + 3];135 uint32_t hw_points_num;136};137 138/* move to dpp139 * while we are moving functionality out of opp to dpp to align140 * HW programming to HW IP, we define these struct in hw_shared141 * so we can still compile while refactoring142 */143 144enum lb_pixel_depth {145 /* do not change the values because it is used as bit vector */146 LB_PIXEL_DEPTH_18BPP = 1,147 LB_PIXEL_DEPTH_24BPP = 2,148 LB_PIXEL_DEPTH_30BPP = 4,149 LB_PIXEL_DEPTH_36BPP = 8150};151 152enum graphics_csc_adjust_type {153 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,154 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */155 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */156};157 158enum ipp_degamma_mode {159 IPP_DEGAMMA_MODE_BYPASS,160 IPP_DEGAMMA_MODE_HW_sRGB,161 IPP_DEGAMMA_MODE_HW_xvYCC,162 IPP_DEGAMMA_MODE_USER_PWL163};164 165enum gamcor_mode {166 GAMCOR_MODE_BYPASS,167 GAMCOR_MODE_RESERVED_1,168 GAMCOR_MODE_USER_PWL,169 GAMCOR_MODE_RESERVED_3170};171 172enum ipp_output_format {173 IPP_OUTPUT_FORMAT_12_BIT_FIX,174 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,175 IPP_OUTPUT_FORMAT_FLOAT176};177 178enum expansion_mode {179 EXPANSION_MODE_DYNAMIC,180 EXPANSION_MODE_ZERO181};182 183struct default_adjustment {184 enum lb_pixel_depth lb_color_depth;185 enum dc_color_space out_color_space;186 enum dc_color_space in_color_space;187 enum dc_color_depth color_depth;188 enum pixel_format surface_pixel_format;189 enum graphics_csc_adjust_type csc_adjust_type;190 bool force_hw_default;191};192 193 194struct out_csc_color_matrix {195 enum dc_color_space color_space;196 uint16_t regval[12];197};198 199enum gamut_remap_select {200 GAMUT_REMAP_BYPASS = 0,201 GAMUT_REMAP_COEFF,202 GAMUT_REMAP_COMA_COEFF,203 GAMUT_REMAP_COMB_COEFF204};205 206enum opp_regamma {207 OPP_REGAMMA_BYPASS = 0,208 OPP_REGAMMA_SRGB,209 OPP_REGAMMA_XVYCC,210 OPP_REGAMMA_USER211};212 213enum optc_dsc_mode {214 OPTC_DSC_DISABLED = 0,215 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */216 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */217};218 219struct dc_bias_and_scale {220 uint32_t scale_red;221 uint32_t bias_red;222 uint32_t scale_green;223 uint32_t bias_green;224 uint32_t scale_blue;225 uint32_t bias_blue;226 bool bias_and_scale_valid;227};228 229enum test_pattern_dyn_range {230 TEST_PATTERN_DYN_RANGE_VESA = 0,231 TEST_PATTERN_DYN_RANGE_CEA232};233 234enum test_pattern_mode {235 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,236 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,237 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,238 TEST_PATTERN_MODE_VERTICALBARS,239 TEST_PATTERN_MODE_HORIZONTALBARS,240 TEST_PATTERN_MODE_SINGLERAMP_RGB,241 TEST_PATTERN_MODE_DUALRAMP_RGB,242 TEST_PATTERN_MODE_XR_BIAS_RGB243};244 245enum test_pattern_color_format {246 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,247 TEST_PATTERN_COLOR_FORMAT_BPC_8,248 TEST_PATTERN_COLOR_FORMAT_BPC_10,249 TEST_PATTERN_COLOR_FORMAT_BPC_12250};251 252enum controller_dp_test_pattern {253 CONTROLLER_DP_TEST_PATTERN_D102 = 0,254 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,255 CONTROLLER_DP_TEST_PATTERN_PRBS7,256 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,257 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,258 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,259 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,260 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,261 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,262 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,263 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,264 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,265 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR266};267 268enum controller_dp_color_space {269 CONTROLLER_DP_COLOR_SPACE_RGB,270 CONTROLLER_DP_COLOR_SPACE_YCBCR601,271 CONTROLLER_DP_COLOR_SPACE_YCBCR709,272 CONTROLLER_DP_COLOR_SPACE_UDEFINED273};274 275enum dc_lut_mode {276 LUT_BYPASS,277 LUT_RAM_A,278 LUT_RAM_B279};280 281/**282 * speakersToChannels283 *284 * @brief285 * translate speakers to channels286 *287 * FL - Front Left288 * FR - Front Right289 * RL - Rear Left290 * RR - Rear Right291 * RC - Rear Center292 * FC - Front Center293 * FLC - Front Left Center294 * FRC - Front Right Center295 * RLC - Rear Left Center296 * RRC - Rear Right Center297 * LFE - Low Freq Effect298 *299 * FC300 * FLC FRC301 * FL FR302 *303 * LFE304 * ()305 *306 *307 * RL RR308 * RLC RRC309 * RC310 *311 * ch 8 7 6 5 4 3 2 1312 * 0b00000011 - - - - - - FR FL313 * 0b00000111 - - - - - LFE FR FL314 * 0b00001011 - - - - FC - FR FL315 * 0b00001111 - - - - FC LFE FR FL316 * 0b00010011 - - - RC - - FR FL317 * 0b00010111 - - - RC - LFE FR FL318 * 0b00011011 - - - RC FC - FR FL319 * 0b00011111 - - - RC FC LFE FR FL320 * 0b00110011 - - RR RL - - FR FL321 * 0b00110111 - - RR RL - LFE FR FL322 * 0b00111011 - - RR RL FC - FR FL323 * 0b00111111 - - RR RL FC LFE FR FL324 * 0b01110011 - RC RR RL - - FR FL325 * 0b01110111 - RC RR RL - LFE FR FL326 * 0b01111011 - RC RR RL FC - FR FL327 * 0b01111111 - RC RR RL FC LFE FR FL328 * 0b11110011 RRC RLC RR RL - - FR FL329 * 0b11110111 RRC RLC RR RL - LFE FR FL330 * 0b11111011 RRC RLC RR RL FC - FR FL331 * 0b11111111 RRC RLC RR RL FC LFE FR FL332 * 0b11000011 FRC FLC - - - - FR FL333 * 0b11000111 FRC FLC - - - LFE FR FL334 * 0b11001011 FRC FLC - - FC - FR FL335 * 0b11001111 FRC FLC - - FC LFE FR FL336 * 0b11010011 FRC FLC - RC - - FR FL337 * 0b11010111 FRC FLC - RC - LFE FR FL338 * 0b11011011 FRC FLC - RC FC - FR FL339 * 0b11011111 FRC FLC - RC FC LFE FR FL340 * 0b11110011 FRC FLC RR RL - - FR FL341 * 0b11110111 FRC FLC RR RL - LFE FR FL342 * 0b11111011 FRC FLC RR RL FC - FR FL343 * 0b11111111 FRC FLC RR RL FC LFE FR FL344 *345 * @param346 * speakers - speaker information as it comes from CEA audio block347 */348/* translate speakers to channels */349 350union audio_cea_channels {351 uint8_t all;352 struct audio_cea_channels_bits {353 uint32_t FL:1;354 uint32_t FR:1;355 uint32_t LFE:1;356 uint32_t FC:1;357 uint32_t RL_RC:1;358 uint32_t RR:1;359 uint32_t RC_RLC_FLC:1;360 uint32_t RRC_FRC:1;361 } channels;362};363 364#endif /* __DAL_HW_SHARED_H__ */365