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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27/**28 * DOC: overview29 *30 * Output Pipe Timing Combiner (OPTC) includes two major functional blocks:31 * Output Data Mapper (ODM) and Output Timing Generator (OTG).32 *33 * - ODM: It is Output Data Mapping block. It can combine input data from34 * multiple OPP data pipes into one single data stream or split data from one35 * OPP data pipe into multiple data streams or just bypass OPP data to DIO.36 * - OTG: It is Output Timing Generator. It generates display timing signals to37 * drive the display output.38 */39 40#ifndef __DC_OPTC_H__41#define __DC_OPTC_H__42 43#include "timing_generator.h"44 45struct optc {46 struct timing_generator base;47 48 const struct dcn_optc_registers *tg_regs;49 const struct dcn_optc_shift *tg_shift;50 const struct dcn_optc_mask *tg_mask;51 52 int opp_count;53 54 uint32_t max_h_total;55 uint32_t max_v_total;56 57 uint32_t min_h_blank;58 59 uint32_t min_h_sync_width;60 uint32_t min_v_sync_width;61 uint32_t min_v_blank;62 uint32_t min_v_blank_interlace;63 64 int vstartup_start;65 int vupdate_offset;66 int vupdate_width;67 int vready_offset;68 int pstate_keepout;69 struct dc_crtc_timing orginal_patched_timing;70 enum signal_type signal;71};72 73struct dcn_otg_state {74 uint32_t v_blank_start;75 uint32_t v_blank_end;76 uint32_t v_sync_a_pol;77 uint32_t v_total;78 uint32_t v_total_max;79 uint32_t v_total_min;80 uint32_t v_total_min_sel;81 uint32_t v_total_max_sel;82 uint32_t v_sync_a_start;83 uint32_t v_sync_a_end;84 uint32_t h_blank_start;85 uint32_t h_blank_end;86 uint32_t h_sync_a_start;87 uint32_t h_sync_a_end;88 uint32_t h_sync_a_pol;89 uint32_t h_total;90 uint32_t underflow_occurred_status;91 uint32_t otg_enabled;92 uint32_t blank_enabled;93 uint32_t vertical_interrupt1_en;94 uint32_t vertical_interrupt1_line;95 uint32_t vertical_interrupt2_en;96 uint32_t vertical_interrupt2_line;97 uint32_t otg_master_update_lock;98 uint32_t otg_double_buffer_control;99};100 101void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);102 103bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);104 105bool optc1_validate_timing(struct timing_generator *optc,106 const struct dc_crtc_timing *timing);107 108void optc1_program_timing(struct timing_generator *optc,109 const struct dc_crtc_timing *dc_crtc_timing,110 int vready_offset,111 int vstartup_start,112 int vupdate_offset,113 int vupdate_width,114 int pstate_keepout,115 const enum signal_type signal,116 bool use_vbios);117 118void optc1_setup_vertical_interrupt0(struct timing_generator *optc,119 uint32_t start_line,120 uint32_t end_line);121 122void optc1_setup_vertical_interrupt1(struct timing_generator *optc,123 uint32_t start_line);124 125void optc1_setup_vertical_interrupt2(struct timing_generator *optc,126 uint32_t start_line);127 128void optc1_program_global_sync(struct timing_generator *optc,129 int vready_offset,130 int vstartup_start,131 int vupdate_offset,132 int vupdate_width,133 int pstate_keepout);134 135bool optc1_disable_crtc(struct timing_generator *optc);136 137bool optc1_is_counter_moving(struct timing_generator *optc);138 139void optc1_get_position(struct timing_generator *optc,140 struct crtc_position *position);141 142uint32_t optc1_get_vblank_counter(struct timing_generator *optc);143 144void optc1_get_crtc_scanoutpos(struct timing_generator *optc,145 uint32_t *v_blank_start,146 uint32_t *v_blank_end,147 uint32_t *h_position,148 uint32_t *v_position);149 150void optc1_set_early_control(struct timing_generator *optc,151 uint32_t early_cntl);152 153void optc1_wait_for_state(struct timing_generator *optc,154 enum crtc_state state);155 156void optc1_set_blank(struct timing_generator *optc,157 bool enable_blanking);158 159bool optc1_is_blanked(struct timing_generator *optc);160 161void optc1_program_blank_color(struct timing_generator *optc,162 const struct tg_color *black_color);163 164bool optc1_did_triggered_reset_occur(struct timing_generator *optc);165 166void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);167 168void optc1_disable_reset_trigger(struct timing_generator *optc);169 170void optc1_lock(struct timing_generator *optc);171 172void optc1_unlock(struct timing_generator *optc);173 174void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);175 176void optc1_set_drr(struct timing_generator *optc,177 const struct drr_params *params);178 179void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);180 181void optc1_set_static_screen_control(struct timing_generator *optc,182 uint32_t event_triggers,183 uint32_t num_frames);184 185void optc1_program_stereo(struct timing_generator *optc,186 const struct dc_crtc_timing *timing,187 struct crtc_stereo_flags *flags);188 189bool optc1_is_stereo_left_eye(struct timing_generator *optc);190 191void optc1_clear_optc_underflow(struct timing_generator *optc);192 193void optc1_tg_init(struct timing_generator *optc);194 195bool optc1_is_tg_enabled(struct timing_generator *optc);196 197bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);198 199void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);200 201void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);202 203bool optc1_get_otg_active_size(struct timing_generator *optc,204 uint32_t *otg_active_width,205 uint32_t *otg_active_height);206 207void optc1_enable_crtc_reset(struct timing_generator *optc,208 int source_tg_inst,209 struct crtc_trigger_info *crtc_tp);210 211bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);212 213bool optc1_get_crc(struct timing_generator *optc,214 uint32_t *r_cr,215 uint32_t *g_y,216 uint32_t *b_cb);217 218void optc1_set_vtg_params(struct timing_generator *optc,219 const struct dc_crtc_timing *dc_crtc_timing,220 bool program_fp2);221 222bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing);223 224#endif225