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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26/* FILE POLICY AND INTENDED USAGE:27 *28 * This file implements generic display communication protocols such as i2c, aux29 * and scdc. The file should not contain any specific applications of these30 * protocols such as display capability query, detection, or handshaking such as31 * link training.32 */33#include "link_ddc.h"34#include "vector.h"35#include "dce/dce_aux.h"36#include "dal_asic_id.h"37#include "link_dpcd.h"38#include "dm_helpers.h"39#include "atomfirmware.h"40 41#define DC_LOGGER \42 ddc_service->ctx->logger43#define DC_LOGGER_INIT(logger)44 45static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";46/* DP to Dual link DVI converter */47static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";48static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";49 50struct i2c_payloads {51 struct vector payloads;52};53 54static bool i2c_payloads_create(55 struct dc_context *ctx,56 struct i2c_payloads *payloads,57 uint32_t count)58{59 if (dal_vector_construct(60 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))61 return true;62 63 return false;64}65 66static struct i2c_payload *i2c_payloads_get(struct i2c_payloads *p)67{68 return (struct i2c_payload *)p->payloads.container;69}70 71static uint32_t i2c_payloads_get_count(struct i2c_payloads *p)72{73 return p->payloads.count;74}75 76static void i2c_payloads_destroy(struct i2c_payloads *p)77{78 if (!p)79 return;80 81 dal_vector_destruct(&p->payloads);82}83 84#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))85 86static void i2c_payloads_add(87 struct i2c_payloads *payloads,88 uint32_t address,89 uint32_t len,90 uint8_t *data,91 bool write)92{93 uint32_t payload_size = EDID_SEGMENT_SIZE;94 uint32_t pos;95 96 for (pos = 0; pos < len; pos += payload_size) {97 struct i2c_payload payload = {98 .write = write,99 .address = address,100 .length = DDC_MIN(payload_size, len - pos),101 .data = data + pos };102 dal_vector_append(&payloads->payloads, &payload);103 }104 105}106 107static void ddc_service_construct(108 struct ddc_service *ddc_service,109 struct ddc_service_init_data *init_data)110{111 enum connector_id connector_id =112 dal_graphics_object_id_get_connector_id(init_data->id);113 114 struct gpio_service *gpio_service = init_data->ctx->gpio_service;115 struct graphics_object_i2c_info i2c_info;116 struct gpio_ddc_hw_info hw_info;117 struct dc_bios *dcb = init_data->ctx->dc_bios;118 119 ddc_service->link = init_data->link;120 ddc_service->ctx = init_data->ctx;121 122 if (init_data->is_dpia_link ||123 dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {124 ddc_service->ddc_pin = NULL;125 } else {126 DC_LOGGER_INIT(ddc_service->ctx->logger);127 DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);128 DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);129 130 hw_info.ddc_channel = i2c_info.i2c_line;131 if (ddc_service->link != NULL)132 hw_info.hw_supported = i2c_info.i2c_hw_assist;133 else134 hw_info.hw_supported = false;135 136 ddc_service->ddc_pin = dal_gpio_create_ddc(137 gpio_service,138 i2c_info.gpio_info.clk_a_register_index,139 1 << i2c_info.gpio_info.clk_a_shift,140 &hw_info);141 }142 143 ddc_service->flags.EDID_QUERY_DONE_ONCE = false;144 ddc_service->flags.FORCE_READ_REPEATED_START = false;145 ddc_service->flags.EDID_STRESS_READ = false;146 147 ddc_service->flags.IS_INTERNAL_DISPLAY =148 connector_id == CONNECTOR_ID_EDP ||149 connector_id == CONNECTOR_ID_LVDS;150 151 ddc_service->wa.raw = 0;152}153 154struct ddc_service *link_create_ddc_service(155 struct ddc_service_init_data *init_data)156{157 struct ddc_service *ddc_service;158 159 ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);160 161 if (!ddc_service)162 return NULL;163 164 ddc_service_construct(ddc_service, init_data);165 return ddc_service;166}167 168static void ddc_service_destruct(struct ddc_service *ddc)169{170 if (ddc->ddc_pin)171 dal_gpio_destroy_ddc(&ddc->ddc_pin);172}173 174void link_destroy_ddc_service(struct ddc_service **ddc)175{176 if (!ddc || !*ddc) {177 BREAK_TO_DEBUGGER();178 return;179 }180 ddc_service_destruct(*ddc);181 kfree(*ddc);182 *ddc = NULL;183}184 185void set_ddc_transaction_type(186 struct ddc_service *ddc,187 enum ddc_transaction_type type)188{189 ddc->transaction_type = type;190}191 192bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)193{194 switch (ddc->transaction_type) {195 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:196 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:197 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:198 return true;199 default:200 break;201 }202 return false;203}204 205void set_dongle_type(struct ddc_service *ddc,206 enum display_dongle_type dongle_type)207{208 ddc->dongle_type = dongle_type;209}210 211static uint32_t defer_delay_converter_wa(212 struct ddc_service *ddc,213 uint32_t defer_delay)214{215 struct dc_link *link = ddc->link;216 217 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&218 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&219 (link->dpcd_caps.branch_fw_revision[0] < 0x01 ||220 (link->dpcd_caps.branch_fw_revision[0] == 0x01 &&221 link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&222 !memcmp(link->dpcd_caps.branch_dev_name,223 DP_VGA_DONGLE_BRANCH_DEV_NAME,224 sizeof(link->dpcd_caps.branch_dev_name)))225 226 return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?227 defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;228 229 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&230 !memcmp(link->dpcd_caps.branch_dev_name,231 DP_DVI_CONVERTER_ID_4,232 sizeof(link->dpcd_caps.branch_dev_name)))233 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?234 defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;235 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&236 !memcmp(link->dpcd_caps.branch_dev_name,237 DP_DVI_CONVERTER_ID_5,238 sizeof(link->dpcd_caps.branch_dev_name)))239 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?240 I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;241 242 return defer_delay;243}244 245#define DP_TRANSLATOR_DELAY 5246 247uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)248{249 uint32_t defer_delay = 0;250 251 switch (ddc->transaction_type) {252 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:253 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||254 (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||255 (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==256 ddc->dongle_type)) {257 258 defer_delay = DP_TRANSLATOR_DELAY;259 260 defer_delay =261 defer_delay_converter_wa(ddc, defer_delay);262 263 } else /*sink has a delay different from an Active Converter*/264 defer_delay = 0;265 break;266 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:267 defer_delay = DP_TRANSLATOR_DELAY;268 break;269 default:270 break;271 }272 return defer_delay;273}274 275static bool submit_aux_command(struct ddc_service *ddc,276 struct aux_payload *payload)277{278 uint32_t retrieved = 0;279 bool ret = false;280 281 if (!ddc)282 return false;283 284 if (!payload)285 return false;286 287 do {288 struct aux_payload current_payload;289 bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=290 payload->length;291 uint32_t payload_length = is_end_of_payload ?292 payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;293 294 current_payload.address = payload->address;295 current_payload.data = &payload->data[retrieved];296 current_payload.defer_delay = payload->defer_delay;297 current_payload.i2c_over_aux = payload->i2c_over_aux;298 current_payload.length = payload_length;299 /* set mot (middle of transaction) to false if it is the last payload */300 current_payload.mot = is_end_of_payload ? payload->mot:true;301 current_payload.write_status_update = false;302 current_payload.reply = payload->reply;303 current_payload.write = payload->write;304 305 ret = link_aux_transfer_with_retries_no_mutex(ddc, ¤t_payload);306 307 retrieved += payload_length;308 } while (retrieved < payload->length && ret == true);309 310 return ret;311}312 313bool link_query_ddc_data(314 struct ddc_service *ddc,315 uint32_t address,316 uint8_t *write_buf,317 uint32_t write_size,318 uint8_t *read_buf,319 uint32_t read_size)320{321 bool success = true;322 uint32_t payload_size =323 link_is_in_aux_transaction_mode(ddc) ?324 DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;325 326 uint32_t write_payloads =327 (write_size + payload_size - 1) / payload_size;328 329 uint32_t read_payloads =330 (read_size + payload_size - 1) / payload_size;331 332 uint32_t payloads_num = write_payloads + read_payloads;333 334 if (!payloads_num)335 return false;336 337 if (link_is_in_aux_transaction_mode(ddc)) {338 struct aux_payload payload;339 340 payload.i2c_over_aux = true;341 payload.address = address;342 payload.reply = NULL;343 payload.defer_delay = link_get_aux_defer_delay(ddc);344 payload.write_status_update = false;345 346 if (write_size != 0) {347 payload.write = true;348 /* should not set mot (middle of transaction) to 0349 * if there are pending read payloads350 */351 payload.mot = !(read_size == 0);352 payload.length = write_size;353 payload.data = write_buf;354 355 success = submit_aux_command(ddc, &payload);356 }357 358 if (read_size != 0 && success) {359 payload.write = false;360 /* should set mot (middle of transaction) to 0361 * since it is the last payload to send362 */363 payload.mot = false;364 payload.length = read_size;365 payload.data = read_buf;366 367 success = submit_aux_command(ddc, &payload);368 }369 } else {370 struct i2c_command command = {0};371 struct i2c_payloads payloads;372 373 if (!i2c_payloads_create(ddc->ctx, &payloads, payloads_num))374 return false;375 376 command.payloads = i2c_payloads_get(&payloads);377 command.number_of_payloads = 0;378 command.engine = DDC_I2C_COMMAND_ENGINE;379 command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;380 381 i2c_payloads_add(382 &payloads, address, write_size, write_buf, true);383 384 i2c_payloads_add(385 &payloads, address, read_size, read_buf, false);386 387 command.number_of_payloads =388 i2c_payloads_get_count(&payloads);389 390 success = dm_helpers_submit_i2c(391 ddc->ctx,392 ddc->link,393 &command);394 395 i2c_payloads_destroy(&payloads);396 }397 398 return success;399}400 401int link_aux_transfer_raw(struct ddc_service *ddc,402 struct aux_payload *payload,403 enum aux_return_code_type *operation_result)404{405 if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||406 !ddc->ddc_pin) {407 return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);408 } else {409 return dce_aux_transfer_raw(ddc, payload, operation_result);410 }411}412 413uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link)414{415 uint32_t vendor_lttpr_write_address = 0xF004F;416 uint8_t offset;417 418 switch (link->dpcd_caps.lttpr_caps.phy_repeater_cnt) {419 case 0x80: // 1 lttpr repeater420 offset = 1;421 break;422 case 0x40: // 2 lttpr repeaters423 offset = 2;424 break;425 case 0x20: // 3 lttpr repeaters426 offset = 3;427 break;428 case 0x10: // 4 lttpr repeaters429 offset = 4;430 break;431 case 0x08: // 5 lttpr repeaters432 offset = 5;433 break;434 case 0x04: // 6 lttpr repeaters435 offset = 6;436 break;437 case 0x02: // 7 lttpr repeaters438 offset = 7;439 break;440 case 0x01: // 8 lttpr repeaters441 offset = 8;442 break;443 default:444 offset = 0xFF;445 }446 447 if (offset != 0xFF) {448 vendor_lttpr_write_address +=449 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));450 }451 return vendor_lttpr_write_address;452}453 454uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link)455{456 return link_get_fixed_vs_pe_retimer_write_address(link) + 4;457}458 459bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)460{461 struct aux_payload write_payload = {462 .i2c_over_aux = false,463 .write = true,464 .address = link_get_fixed_vs_pe_retimer_write_address(ddc->link),465 .length = length,466 .data = (uint8_t *) data,467 .reply = NULL,468 .mot = I2C_MOT_UNDEF,469 .write_status_update = false,470 .defer_delay = 0,471 };472 473 return link_aux_transfer_with_retries_no_mutex(ddc,474 &write_payload);475}476 477bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)478{479 struct aux_payload read_payload = {480 .i2c_over_aux = false,481 .write = false,482 .address = link_get_fixed_vs_pe_retimer_read_address(ddc->link),483 .length = length,484 .data = data,485 .reply = NULL,486 .mot = I2C_MOT_UNDEF,487 .write_status_update = false,488 .defer_delay = 0,489 };490 491 return link_aux_transfer_with_retries_no_mutex(ddc,492 &read_payload);493}494 495bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,496 struct aux_payload *payload)497{498 return dce_aux_transfer_with_retries(ddc, payload);499}500 501 502bool try_to_configure_aux_timeout(struct ddc_service *ddc,503 uint32_t timeout)504{505 bool result = false;506 struct ddc *ddc_pin = ddc->ddc_pin;507 508 if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&509 !ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&510 ddc->ctx->dce_version == DCN_VERSION_3_1) {511 /* Fixed VS workaround for AUX timeout */512 const uint32_t fixed_vs_address = 0xF004F;513 const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};514 515 core_link_write_dpcd(ddc->link,516 fixed_vs_address,517 fixed_vs_data,518 sizeof(fixed_vs_data));519 520 timeout = 3072;521 }522 523 /* Do not try to access nonexistent DDC pin. */524 if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)525 return true;526 527 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {528 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);529 result = true;530 }531 532 return result;533}534 535struct ddc *get_ddc_pin(struct ddc_service *ddc_service)536{537 return ddc_service->ddc_pin;538}539 540void write_scdc_data(struct ddc_service *ddc_service,541 uint32_t pix_clk,542 bool lte_340_scramble)543{544 bool over_340_mhz = pix_clk > 340000 ? 1 : 0;545 uint8_t slave_address = HDMI_SCDC_ADDRESS;546 uint8_t offset = HDMI_SCDC_SINK_VERSION;547 uint8_t sink_version = 0;548 uint8_t write_buffer[2] = {0};549 /*Lower than 340 Scramble bit from SCDC caps*/550 551 if (ddc_service->link->local_sink &&552 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)553 return;554 555 link_query_ddc_data(ddc_service, slave_address, &offset,556 sizeof(offset), &sink_version, sizeof(sink_version));557 if (sink_version == 1) {558 /*Source Version = 1*/559 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;560 write_buffer[1] = 1;561 link_query_ddc_data(ddc_service, slave_address,562 write_buffer, sizeof(write_buffer), NULL, 0);563 /*Read Request from SCDC caps*/564 }565 write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;566 567 if (over_340_mhz) {568 write_buffer[1] = 3;569 } else if (lte_340_scramble) {570 write_buffer[1] = 1;571 } else {572 write_buffer[1] = 0;573 }574 link_query_ddc_data(ddc_service, slave_address, write_buffer,575 sizeof(write_buffer), NULL, 0);576}577 578void read_scdc_data(struct ddc_service *ddc_service)579{580 uint8_t slave_address = HDMI_SCDC_ADDRESS;581 uint8_t offset = HDMI_SCDC_TMDS_CONFIG;582 uint8_t tmds_config = 0;583 584 if (ddc_service->link->local_sink &&585 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)586 return;587 588 link_query_ddc_data(ddc_service, slave_address, &offset,589 sizeof(offset), &tmds_config, sizeof(tmds_config));590 if (tmds_config & 0x1) {591 union hdmi_scdc_status_flags_data status_data = {0};592 uint8_t scramble_status = 0;593 594 offset = HDMI_SCDC_SCRAMBLER_STATUS;595 link_query_ddc_data(ddc_service, slave_address,596 &offset, sizeof(offset), &scramble_status,597 sizeof(scramble_status));598 offset = HDMI_SCDC_STATUS_FLAGS;599 link_query_ddc_data(ddc_service, slave_address,600 &offset, sizeof(offset), &status_data.byte,601 sizeof(status_data.byte));602 }603}604