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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "reg_helper.h"27#include "dcn10_mpc.h"28 29#define REG(reg)\30 mpc10->mpc_regs->reg31 32#define CTX \33 mpc10->base.ctx34 35#undef FN36#define FN(reg_name, field_name) \37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name38 39 40void mpc1_set_bg_color(struct mpc *mpc,41 struct tg_color *bg_color,42 int mpcc_id)43{44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);46 uint32_t bg_r_cr, bg_g_y, bg_b_cb;47 48 bottommost_mpcc->blnd_cfg.black_color = *bg_color;49 50 /* find bottommost mpcc. */51 while (bottommost_mpcc->mpcc_bot) {52 /* avoid circular linked link */53 ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot);54 if (bottommost_mpcc == bottommost_mpcc->mpcc_bot)55 break;56 57 bottommost_mpcc = bottommost_mpcc->mpcc_bot;58 }59 60 /* mpc color is 12 bit. tg_color is 10 bit */61 /* todo: might want to use 16 bit to represent color and have each62 * hw block translate to correct color depth.63 */64 bg_r_cr = bg_color->color_r_cr << 2;65 bg_g_y = bg_color->color_g_y << 2;66 bg_b_cb = bg_color->color_b_cb << 2;67 68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,69 MPCC_BG_R_CR, bg_r_cr);70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,71 MPCC_BG_G_Y, bg_g_y);72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,73 MPCC_BG_B_CB, bg_b_cb);74}75 76static void mpc1_update_blending(77 struct mpc *mpc,78 struct mpcc_blnd_cfg *blnd_cfg,79 int mpcc_id)80{81 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);83 84 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],85 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,86 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,87 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,88 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,89 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);90 91 mpcc->blnd_cfg = *blnd_cfg;92}93 94void mpc1_update_stereo_mix(95 struct mpc *mpc,96 struct mpcc_sm_cfg *sm_cfg,97 int mpcc_id)98{99 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);100 101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],102 MPCC_SM_EN, sm_cfg->enable,103 MPCC_SM_MODE, sm_cfg->sm_mode,104 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt,105 MPCC_SM_FIELD_ALT, sm_cfg->field_alt,106 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity,107 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity);108}109void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)110{111 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);112 113 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));114 REG_WAIT(MPCC_STATUS[id],115 MPCC_IDLE, 1,116 1, 100000);117}118 119struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)120{121 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);122 123 ASSERT(mpcc_id < mpc10->num_mpcc);124 return &(mpc->mpcc_array[mpcc_id]);125}126 127struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)128{129 struct mpcc *tmp_mpcc = tree->opp_list;130 131 while (tmp_mpcc != NULL) {132 if (tmp_mpcc->dpp_id == dpp_id)133 return tmp_mpcc;134 135 /* avoid circular linked list */136 ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);137 if (tmp_mpcc == tmp_mpcc->mpcc_bot)138 break;139 140 tmp_mpcc = tmp_mpcc->mpcc_bot;141 }142 return NULL;143}144 145bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)146{147 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);148 unsigned int top_sel;149 unsigned int opp_id;150 unsigned int idle;151 152 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);154 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);155 if (top_sel == 0xf && opp_id == 0xf && idle)156 return true;157 else158 return false;159}160 161void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)162{163 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);164 unsigned int top_sel, mpc_busy, mpc_idle;165 166 REG_GET(MPCC_TOP_SEL[mpcc_id],167 MPCC_TOP_SEL, &top_sel);168 169 if (top_sel == 0xf) {170 REG_GET_2(MPCC_STATUS[mpcc_id],171 MPCC_BUSY, &mpc_busy,172 MPCC_IDLE, &mpc_idle);173 174 ASSERT(mpc_busy == 0);175 ASSERT(mpc_idle == 1);176 }177}178 179/*180 * Insert DPP into MPC tree based on specified blending position.181 * Only used for planes that are part of blending chain for OPP output182 *183 * Parameters:184 * [in/out] mpc - MPC context.185 * [in/out] tree - MPC tree structure that plane will be added to.186 * [in] blnd_cfg - MPCC blending configuration for the new blending layer.187 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.188 * stereo mix must disable for the very bottom layer of the tree config.189 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.190 * [in] dpp_id - DPP instance for the plane to be added.191 * [in] mpcc_id - The MPCC physical instance to use for blending.192 *193 * Return: struct mpcc* - MPCC that was added.194 */195struct mpcc *mpc1_insert_plane(196 struct mpc *mpc,197 struct mpc_tree *tree,198 struct mpcc_blnd_cfg *blnd_cfg,199 struct mpcc_sm_cfg *sm_cfg,200 struct mpcc *insert_above_mpcc,201 int dpp_id,202 int mpcc_id)203{204 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);205 struct mpcc *new_mpcc = NULL;206 207 /* sanity check parameters */208 ASSERT(mpcc_id < mpc10->num_mpcc);209 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));210 211 if (insert_above_mpcc) {212 /* check insert_above_mpcc exist in tree->opp_list */213 struct mpcc *temp_mpcc = tree->opp_list;214 215 if (temp_mpcc != insert_above_mpcc)216 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)217 temp_mpcc = temp_mpcc->mpcc_bot;218 if (temp_mpcc == NULL)219 return NULL;220 }221 222 /* Get and update MPCC struct parameters */223 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);224 new_mpcc->dpp_id = dpp_id;225 226 /* program mux and MPCC_MODE */227 if (insert_above_mpcc) {228 new_mpcc->mpcc_bot = insert_above_mpcc;229 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);230 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);231 } else {232 new_mpcc->mpcc_bot = NULL;233 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);234 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);235 }236 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);238 239 /* Configure VUPDATE lock set for this MPCC to map to the OPP */240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);241 242 /* update mpc tree mux setting */243 if (tree->opp_list == insert_above_mpcc) {244 /* insert the toppest mpcc */245 tree->opp_list = new_mpcc;246 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);247 } else {248 /* find insert position */249 struct mpcc *temp_mpcc = tree->opp_list;250 251 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)252 temp_mpcc = temp_mpcc->mpcc_bot;253 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {254 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);255 temp_mpcc->mpcc_bot = new_mpcc;256 if (!insert_above_mpcc)257 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],258 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);259 }260 }261 262 /* update the blending configuration */263 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);264 265 /* update the stereo mix settings, if provided */266 if (sm_cfg != NULL) {267 new_mpcc->sm_cfg = *sm_cfg;268 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);269 }270 271 /* mark this mpcc as in use */272 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;273 274 return new_mpcc;275}276 277/*278 * Remove a specified MPCC from the MPC tree.279 *280 * Parameters:281 * [in/out] mpc - MPC context.282 * [in/out] tree - MPC tree structure that plane will be removed from.283 * [in/out] mpcc - MPCC to be removed from tree.284 *285 * Return: void286 */287void mpc1_remove_mpcc(288 struct mpc *mpc,289 struct mpc_tree *tree,290 struct mpcc *mpcc_to_remove)291{292 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);293 bool found = false;294 int mpcc_id = mpcc_to_remove->mpcc_id;295 296 if (tree->opp_list == mpcc_to_remove) {297 found = true;298 /* remove MPCC from top of tree */299 if (mpcc_to_remove->mpcc_bot) {300 /* set the next MPCC in list to be the top MPCC */301 tree->opp_list = mpcc_to_remove->mpcc_bot;302 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);303 } else {304 /* there are no other MPCC is list */305 tree->opp_list = NULL;306 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);307 }308 } else {309 /* find mpcc to remove MPCC list */310 struct mpcc *temp_mpcc = tree->opp_list;311 312 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)313 temp_mpcc = temp_mpcc->mpcc_bot;314 315 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {316 found = true;317 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;318 if (mpcc_to_remove->mpcc_bot) {319 /* remove MPCC in middle of list */320 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,321 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);322 } else {323 /* remove MPCC from bottom of list */324 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,325 MPCC_BOT_SEL, 0xf);326 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],327 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);328 }329 }330 }331 332 if (found) {333 /* turn off MPCC mux registers */334 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);335 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);336 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);337 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);338 339 /* mark this mpcc as not in use */340 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);341 mpcc_to_remove->dpp_id = 0xf;342 mpcc_to_remove->mpcc_bot = NULL;343 } else {344 /* In case of resume from S3/S4, remove mpcc from bios left over */345 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);346 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);347 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);348 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);349 }350}351 352static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)353{354 mpcc->mpcc_id = mpcc_inst;355 mpcc->dpp_id = 0xf;356 mpcc->mpcc_bot = NULL;357 mpcc->blnd_cfg.overlap_only = false;358 mpcc->blnd_cfg.global_alpha = 0xff;359 mpcc->blnd_cfg.global_gain = 0xff;360 mpcc->sm_cfg.enable = false;361}362 363/*364 * Reset the MPCC HW status by disconnecting all muxes.365 *366 * Parameters:367 * [in/out] mpc - MPC context.368 *369 * Return: void370 */371void mpc1_mpc_init(struct mpc *mpc)372{373 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);374 int mpcc_id;375 int opp_id;376 377 mpc10->mpcc_in_use_mask = 0;378 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {379 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);380 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);381 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);382 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);383 384 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);385 }386 387 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {388 if (REG(MUX[opp_id]))389 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);390 }391}392 393void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)394{395 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);396 int opp_id;397 398 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);399 400 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);401 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);402 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);403 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);404 405 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);406 407 if (opp_id < MAX_OPP && REG(MUX[opp_id]))408 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);409}410 411 412void mpc1_init_mpcc_list_from_hw(413 struct mpc *mpc,414 struct mpc_tree *tree)415{416 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);417 unsigned int opp_id;418 unsigned int top_sel;419 unsigned int bot_sel;420 unsigned int out_mux;421 struct mpcc *mpcc;422 int mpcc_id;423 int bot_mpcc_id;424 425 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);426 427 if (out_mux != 0xf) {428 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {429 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);430 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);431 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);432 433 if (bot_sel == mpcc_id)434 bot_sel = 0xf;435 436 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {437 mpcc = mpc1_get_mpcc(mpc, mpcc_id);438 mpcc->dpp_id = top_sel;439 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;440 441 if (out_mux == mpcc_id)442 tree->opp_list = mpcc;443 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {444 bot_mpcc_id = bot_sel;445 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);446 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);447 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {448 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);449 450 mpcc->mpcc_bot = mpcc_bottom;451 }452 }453 }454 }455 }456}457 458void mpc1_read_mpcc_state(459 struct mpc *mpc,460 int mpcc_inst,461 struct mpcc_state *s)462{463 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);464 465 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);466 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);467 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);468 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,469 MPCC_ALPHA_BLND_MODE, &s->alpha_mode,470 MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,471 MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);472 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,473 MPCC_BUSY, &s->busy);474}475 476void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)477{478 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);479 480 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);481}482 483unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)484{485 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);486 uint32_t val = 0xf;487 488 if (opp_id < MAX_OPP && REG(MUX[opp_id]))489 REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);490 491 return val;492}493 494static const struct mpc_funcs dcn10_mpc_funcs = {495 .read_mpcc_state = mpc1_read_mpcc_state,496 .insert_plane = mpc1_insert_plane,497 .remove_mpcc = mpc1_remove_mpcc,498 .mpc_init = mpc1_mpc_init,499 .mpc_init_single_inst = mpc1_mpc_init_single_inst,500 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,501 .wait_for_idle = mpc1_assert_idle_mpcc,502 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,503 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,504 .update_blending = mpc1_update_blending,505 .cursor_lock = mpc1_cursor_lock,506 .set_denorm = NULL,507 .set_denorm_clamp = NULL,508 .set_output_csc = NULL,509 .set_output_gamma = NULL,510 .get_mpc_out_mux = mpc1_get_mpc_out_mux,511 .set_bg_color = mpc1_set_bg_color,512};513 514void dcn10_mpc_construct(struct dcn10_mpc *mpc10,515 struct dc_context *ctx,516 const struct dcn_mpc_registers *mpc_regs,517 const struct dcn_mpc_shift *mpc_shift,518 const struct dcn_mpc_mask *mpc_mask,519 int num_mpcc)520{521 int i;522 523 mpc10->base.ctx = ctx;524 525 mpc10->base.funcs = &dcn10_mpc_funcs;526 527 mpc10->mpc_regs = mpc_regs;528 mpc10->mpc_shift = mpc_shift;529 mpc10->mpc_mask = mpc_mask;530 531 mpc10->mpcc_in_use_mask = 0;532 mpc10->num_mpcc = num_mpcc;533 534 for (i = 0; i < MAX_MPCC; i++)535 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);536}537 538