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1/* Copyright 2020 Advanced Micro Devices, Inc.2 *3 * Permission is hereby granted, free of charge, to any person obtaining a4 * copy of this software and associated documentation files (the "Software"),5 * to deal in the Software without restriction, including without limitation6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,7 * and/or sell copies of the Software, and to permit persons to whom the8 * Software is furnished to do so, subject to the following conditions:9 *10 * The above copyright notice and this permission notice shall be included in11 * all copies or substantial portions of the Software.12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19 * OTHER DEALINGS IN THE SOFTWARE.20 *21 * Authors: AMD22 *23 */24 25#ifndef __DC_MPCC_DCN30_H__26#define __DC_MPCC_DCN30_H__27 28#include "dcn20/dcn20_mpc.h"29 30#define MAX_RMU 331 32#define TO_DCN30_MPC(mpc_base) \33 container_of(mpc_base, struct dcn30_mpc, base)34 35#ifdef SRII_MPC_RMU36#undef SRII_MPC_RMU37 38#define SRII_MPC_RMU(reg_name, block, id)\39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \40 mm ## block ## id ## _ ## reg_name41 42#endif43 44 45#define MPC_REG_LIST_DCN3_0(inst)\46 MPC_COMMON_REG_LIST_DCN1_0(inst),\47 SRII(MPCC_TOP_GAIN, MPCC, inst),\48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\57 SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\58 SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\59 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\60 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\61 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\62 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\63 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\64 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\65 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\66 SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\67 SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\68 SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\69 SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\70 SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\71 SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\72 SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\73 SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\74 SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\75 SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\76 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\77 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\78 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\79 SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\80 SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\81 SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\82 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\83 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\84 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\85 SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\86 SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\87 SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\88 SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\89 SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\90 SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\91 SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\92 SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\93 SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\94 SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\95 SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\96 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\97 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\98 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\99 SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\100 SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)101 102#define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \103 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\104 SRII(CSC_MODE, MPC_OUT, inst),\105 SRII(CSC_C11_C12_A, MPC_OUT, inst),\106 SRII(CSC_C33_C34_A, MPC_OUT, inst),\107 SRII(CSC_C11_C12_B, MPC_OUT, inst),\108 SRII(CSC_C33_C34_B, MPC_OUT, inst),\109 SRII(DENORM_CONTROL, MPC_OUT, inst),\110 SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\111 SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \112 SR(MPC_OUT_CSC_COEF_FORMAT)113 114#define MPC_RMU_GLOBAL_REG_LIST_DCN3AG \115 SR(MPC_RMU_CONTROL),\116 SR(MPC_RMU_MEM_PWR_CTRL)117 118#define MPC_RMU_REG_LIST_DCN3AG(inst) \119 SRII(SHAPER_CONTROL, MPC_RMU, inst),\120 SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\121 SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\122 SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\123 SRII(SHAPER_SCALE_R, MPC_RMU, inst),\124 SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\125 SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\126 SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\127 SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\128 SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\129 SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\130 SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\131 SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\132 SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\133 SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\134 SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\135 SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\136 SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\137 SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\138 SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\139 SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\140 SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\141 SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\142 SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\143 SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\144 SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\145 SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\146 SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\147 SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\148 SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\149 SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\150 SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\151 SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\152 SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\153 SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\154 SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\155 SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\156 SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\157 SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\158 SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\159 SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\160 SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\161 SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\162 SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\163 SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\164 SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\165 SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\166 SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\167 SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\168 SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\169 SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\170 SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\171 SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\172 SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\173 SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\174 SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\175 SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\176 SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\177 SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\178 SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\179 SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\180 SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\181 SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\182 SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst)183 184 185#define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \186 SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)187 188#define MPC_REG_VARIABLE_LIST_DCN3_0 \189 MPC_REG_VARIABLE_LIST_DCN2_0 \190 uint32_t DWB_MUX[MAX_DWB]; \191 uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \192 uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \193 uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \194 uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \195 uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \196 uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \197 uint32_t MPC_RMU_CONTROL; \198 uint32_t MPC_RMU_MEM_PWR_CTRL; \199 uint32_t SHAPER_CONTROL[MAX_RMU]; \200 uint32_t SHAPER_OFFSET_R[MAX_RMU]; \201 uint32_t SHAPER_OFFSET_G[MAX_RMU]; \202 uint32_t SHAPER_OFFSET_B[MAX_RMU]; \203 uint32_t SHAPER_SCALE_R[MAX_RMU]; \204 uint32_t SHAPER_SCALE_G_B[MAX_RMU]; \205 uint32_t SHAPER_LUT_INDEX[MAX_RMU]; \206 uint32_t SHAPER_LUT_DATA[MAX_RMU]; \207 uint32_t SHAPER_LUT_WRITE_EN_MASK[MAX_RMU]; \208 uint32_t SHAPER_RAMA_START_CNTL_B[MAX_RMU]; \209 uint32_t SHAPER_RAMA_START_CNTL_G[MAX_RMU]; \210 uint32_t SHAPER_RAMA_START_CNTL_R[MAX_RMU]; \211 uint32_t SHAPER_RAMA_END_CNTL_B[MAX_RMU]; \212 uint32_t SHAPER_RAMA_END_CNTL_G[MAX_RMU]; \213 uint32_t SHAPER_RAMA_END_CNTL_R[MAX_RMU]; \214 uint32_t SHAPER_RAMA_REGION_0_1[MAX_RMU]; \215 uint32_t SHAPER_RAMA_REGION_2_3[MAX_RMU]; \216 uint32_t SHAPER_RAMA_REGION_4_5[MAX_RMU]; \217 uint32_t SHAPER_RAMA_REGION_6_7[MAX_RMU]; \218 uint32_t SHAPER_RAMA_REGION_8_9[MAX_RMU]; \219 uint32_t SHAPER_RAMA_REGION_10_11[MAX_RMU]; \220 uint32_t SHAPER_RAMA_REGION_12_13[MAX_RMU]; \221 uint32_t SHAPER_RAMA_REGION_14_15[MAX_RMU]; \222 uint32_t SHAPER_RAMA_REGION_16_17[MAX_RMU]; \223 uint32_t SHAPER_RAMA_REGION_18_19[MAX_RMU]; \224 uint32_t SHAPER_RAMA_REGION_20_21[MAX_RMU]; \225 uint32_t SHAPER_RAMA_REGION_22_23[MAX_RMU]; \226 uint32_t SHAPER_RAMA_REGION_24_25[MAX_RMU]; \227 uint32_t SHAPER_RAMA_REGION_26_27[MAX_RMU]; \228 uint32_t SHAPER_RAMA_REGION_28_29[MAX_RMU]; \229 uint32_t SHAPER_RAMA_REGION_30_31[MAX_RMU]; \230 uint32_t SHAPER_RAMA_REGION_32_33[MAX_RMU]; \231 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \232 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \233 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \234 uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \235 uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \236 uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \237 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \238 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \239 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_R[MAX_MPCC];\240 uint32_t SHAPER_RAMB_START_CNTL_B[MAX_RMU]; \241 uint32_t SHAPER_RAMB_START_CNTL_G[MAX_RMU]; \242 uint32_t SHAPER_RAMB_START_CNTL_R[MAX_RMU]; \243 uint32_t SHAPER_RAMB_END_CNTL_B[MAX_RMU]; \244 uint32_t SHAPER_RAMB_END_CNTL_G[MAX_RMU]; \245 uint32_t SHAPER_RAMB_END_CNTL_R[MAX_RMU]; \246 uint32_t SHAPER_RAMB_REGION_0_1[MAX_RMU]; \247 uint32_t SHAPER_RAMB_REGION_2_3[MAX_RMU]; \248 uint32_t SHAPER_RAMB_REGION_4_5[MAX_RMU]; \249 uint32_t SHAPER_RAMB_REGION_6_7[MAX_RMU]; \250 uint32_t SHAPER_RAMB_REGION_8_9[MAX_RMU]; \251 uint32_t SHAPER_RAMB_REGION_10_11[MAX_RMU]; \252 uint32_t SHAPER_RAMB_REGION_12_13[MAX_RMU]; \253 uint32_t SHAPER_RAMB_REGION_14_15[MAX_RMU]; \254 uint32_t SHAPER_RAMB_REGION_16_17[MAX_RMU]; \255 uint32_t SHAPER_RAMB_REGION_18_19[MAX_RMU]; \256 uint32_t SHAPER_RAMB_REGION_20_21[MAX_RMU]; \257 uint32_t SHAPER_RAMB_REGION_22_23[MAX_RMU]; \258 uint32_t SHAPER_RAMB_REGION_24_25[MAX_RMU]; \259 uint32_t SHAPER_RAMB_REGION_26_27[MAX_RMU]; \260 uint32_t SHAPER_RAMB_REGION_28_29[MAX_RMU]; \261 uint32_t SHAPER_RAMB_REGION_30_31[MAX_RMU]; \262 uint32_t SHAPER_RAMB_REGION_32_33[MAX_RMU]; \263 uint32_t RMU_3DLUT_MODE[MAX_RMU]; \264 uint32_t RMU_3DLUT_INDEX[MAX_RMU]; \265 uint32_t RMU_3DLUT_DATA[MAX_RMU]; \266 uint32_t RMU_3DLUT_DATA_30BIT[MAX_RMU]; \267 uint32_t RMU_3DLUT_READ_WRITE_CONTROL[MAX_RMU]; \268 uint32_t RMU_3DLUT_OUT_NORM_FACTOR[MAX_RMU]; \269 uint32_t RMU_3DLUT_OUT_OFFSET_R[MAX_RMU]; \270 uint32_t RMU_3DLUT_OUT_OFFSET_G[MAX_RMU]; \271 uint32_t RMU_3DLUT_OUT_OFFSET_B[MAX_RMU]; \272 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \273 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \274 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \275 uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \276 uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \277 uint32_t MPCC_OGAM_RAMB_OFFSET_B[MAX_MPCC]; \278 uint32_t MPCC_OGAM_RAMB_OFFSET_G[MAX_MPCC]; \279 uint32_t MPCC_OGAM_RAMB_OFFSET_R[MAX_MPCC]; \280 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \281 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \282 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \283 uint32_t MPC_OUT_CSC_COEF_FORMAT284 285#define MPC_REG_VARIABLE_LIST_DCN32 \286 uint32_t MPCC_MOVABLE_CM_LOCATION_CONTROL[MAX_MPCC]; \287 uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \288 uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \289 uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \290 uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \291 uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \292 uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \293 uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \294 uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \295 uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \296 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \297 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \298 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \299 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \300 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \301 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \302 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \303 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \304 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \305 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \306 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \307 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \308 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \309 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \310 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \311 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \312 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \313 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \314 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \315 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \316 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \317 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \318 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \319 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \320 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \321 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \322 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \323 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \324 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \325 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \326 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \327 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \328 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \329 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \330 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \331 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \332 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \333 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \334 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \335 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \336 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \337 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \338 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \339 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \340 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \341 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \342 uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \343 uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \344 uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \345 uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \346 uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \347 uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \348 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \349 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \350 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \351 uint32_t MPCC_MCM_1DLUT_CONTROL[MAX_MPCC]; \352 uint32_t MPCC_MCM_1DLUT_LUT_INDEX[MAX_MPCC]; \353 uint32_t MPCC_MCM_1DLUT_LUT_DATA[MAX_MPCC]; \354 uint32_t MPCC_MCM_1DLUT_LUT_CONTROL[MAX_MPCC]; \355 uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_B[MAX_MPCC]; \356 uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_G[MAX_MPCC]; \357 uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_R[MAX_MPCC]; \358 uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \359 uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \360 uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \361 uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \362 uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \363 uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R[MAX_MPCC]; \364 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[MAX_MPCC]; \365 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[MAX_MPCC]; \366 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[MAX_MPCC]; \367 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[MAX_MPCC]; \368 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[MAX_MPCC]; \369 uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[MAX_MPCC]; \370 uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_B[MAX_MPCC]; \371 uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_G[MAX_MPCC]; \372 uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_R[MAX_MPCC]; \373 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_0_1[MAX_MPCC]; \374 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_2_3[MAX_MPCC]; \375 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_4_5[MAX_MPCC]; \376 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_6_7[MAX_MPCC]; \377 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_8_9[MAX_MPCC]; \378 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_10_11[MAX_MPCC]; \379 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_12_13[MAX_MPCC]; \380 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_14_15[MAX_MPCC]; \381 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_16_17[MAX_MPCC]; \382 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_18_19[MAX_MPCC]; \383 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_20_21[MAX_MPCC]; \384 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_22_23[MAX_MPCC]; \385 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_24_25[MAX_MPCC]; \386 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_26_27[MAX_MPCC]; \387 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_28_29[MAX_MPCC]; \388 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_30_31[MAX_MPCC]; \389 uint32_t MPCC_MCM_1DLUT_RAMA_REGION_32_33[MAX_MPCC]; \390 uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_B[MAX_MPCC]; \391 uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_G[MAX_MPCC]; \392 uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_R[MAX_MPCC]; \393 uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \394 uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \395 uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \396 uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \397 uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \398 uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \399 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[MAX_MPCC]; \400 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[MAX_MPCC]; \401 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[MAX_MPCC]; \402 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[MAX_MPCC]; \403 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[MAX_MPCC]; \404 uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[MAX_MPCC]; \405 uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_B[MAX_MPCC]; \406 uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_G[MAX_MPCC]; \407 uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_R[MAX_MPCC]; \408 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_0_1[MAX_MPCC]; \409 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_2_3[MAX_MPCC]; \410 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_4_5[MAX_MPCC]; \411 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_6_7[MAX_MPCC]; \412 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_8_9[MAX_MPCC]; \413 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_10_11[MAX_MPCC]; \414 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_12_13[MAX_MPCC]; \415 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_14_15[MAX_MPCC]; \416 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_16_17[MAX_MPCC]; \417 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_18_19[MAX_MPCC]; \418 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_20_21[MAX_MPCC]; \419 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_22_23[MAX_MPCC]; \420 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_24_25[MAX_MPCC]; \421 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_26_27[MAX_MPCC]; \422 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_28_29[MAX_MPCC]; \423 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_30_31[MAX_MPCC]; \424 uint32_t MPCC_MCM_1DLUT_RAMB_REGION_32_33[MAX_MPCC]; \425 uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC]426 427#define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \428 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\429 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\430 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\431 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\432 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\433 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\434 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\435 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\436 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\437 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\438 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\439 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\440 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\441 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\442 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\443 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\444 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\445 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\446 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\447 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\448 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\449 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\450 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\451 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\452 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\453 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\454 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\455 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\456 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\457 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\458 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \459 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \460 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \461 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \462 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \463 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\464 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\465 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\466 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\467 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\468 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\469 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\470 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\471 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\472 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\473 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\474 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\475 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\476 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\477 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\478 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\479 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\480 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\481 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\482 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\483 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\484 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\485 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\486 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\487 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\488 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),\489 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\490 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\491 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\492 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),\493 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\494 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\495 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\496 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),\497 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\498 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\499 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\500 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\501 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\502 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\503 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),\504 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\505 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\506 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\507 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\508 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\509 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\510 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\511 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\512 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\513 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\514 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),\515 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\516 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\517 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\518 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\519 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\520 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\521 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\522 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\523 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\524 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\525 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\526 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\527 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\528 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\529 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\530 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\531 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)532 533 534#define MPC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \535 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\536 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\537 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\538 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\539 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\540 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\541 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\542 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\543 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\544 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\545 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\546 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\547 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\548 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\549 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\550 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\551 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\552 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\553 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\554 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\555 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\556 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\557 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\558 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\559 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\560 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\561 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\562 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\563 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\564 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\565 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\566 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \567 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \568 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \569 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \570 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \571 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\572 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\573 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\574 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\575 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\576 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\577 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\578 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\579 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\580 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\581 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\582 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\583 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\584 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\585 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\586 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\587 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\588 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\589 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\590 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\591 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\592 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\593 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\594 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\595 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\596 /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\597 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\598 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\599 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\600 /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\601 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\602 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\603 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\604 /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\605 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\606 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\607 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\608 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\609 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\610 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\611 /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\612 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\613 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\614 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\615 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\616 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\617 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\618 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\619 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\620 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\621 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\622 /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\623 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\624 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\625 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\626 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\627 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\628 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\629 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\630 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\631 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\632 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\633 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\634 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\635 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\636 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\637 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\638 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\639 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\640 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\641 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\642 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)643 644 645#define MPC_REG_FIELD_LIST_DCN3_0(type) \646 MPC_REG_FIELD_LIST_DCN2_0(type) \647 type MPC_DWB0_MUX;\648 type MPC_DWB0_MUX_STATUS;\649 type MPC_OUT_RATE_CONTROL;\650 type MPC_OUT_RATE_CONTROL_DISABLE;\651 type MPC_OUT_FLOW_CONTROL_MODE;\652 type MPC_OUT_FLOW_CONTROL_COUNT; \653 type MPCC_GAMUT_REMAP_MODE; \654 type MPCC_GAMUT_REMAP_MODE_CURRENT;\655 type MPCC_GAMUT_REMAP_COEF_FORMAT; \656 type MPCC_GAMUT_REMAP_C11_A; \657 type MPCC_GAMUT_REMAP_C12_A; \658 type MPC_RMU0_MUX; \659 type MPC_RMU1_MUX; \660 type MPC_RMU0_MUX_STATUS; \661 type MPC_RMU1_MUX_STATUS; \662 type MPC_RMU0_MEM_PWR_FORCE;\663 type MPC_RMU0_MEM_PWR_DIS;\664 type MPC_RMU0_MEM_LOW_PWR_MODE;\665 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\666 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\667 type MPC_RMU1_MEM_PWR_FORCE;\668 type MPC_RMU1_MEM_PWR_DIS;\669 type MPC_RMU1_MEM_LOW_PWR_MODE;\670 type MPC_RMU1_SHAPER_MEM_PWR_STATE;\671 type MPC_RMU1_3DLUT_MEM_PWR_STATE;\672 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \673 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\674 type MPCC_OGAM_RAMA_OFFSET_B;\675 type MPCC_OGAM_RAMA_OFFSET_G;\676 type MPCC_OGAM_RAMA_OFFSET_R;\677 type MPCC_OGAM_SELECT; \678 type MPCC_OGAM_PWL_DISABLE; \679 type MPCC_OGAM_MODE_CURRENT; \680 type MPCC_OGAM_SELECT_CURRENT; \681 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \682 type MPCC_OGAM_LUT_READ_COLOR_SEL; \683 type MPCC_OGAM_LUT_READ_DBG; \684 type MPCC_OGAM_LUT_HOST_SEL; \685 type MPCC_OGAM_LUT_CONFIG_MODE; \686 type MPCC_OGAM_LUT_STATUS; \687 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\688 type MPCC_OGAM_MEM_LOW_PWR_MODE;\689 type MPCC_OGAM_MEM_PWR_STATE;\690 type MPC_RMU_3DLUT_MODE; \691 type MPC_RMU_3DLUT_SIZE; \692 type MPC_RMU_3DLUT_MODE_CURRENT; \693 type MPC_RMU_3DLUT_WRITE_EN_MASK;\694 type MPC_RMU_3DLUT_RAM_SEL;\695 type MPC_RMU_3DLUT_30BIT_EN;\696 type MPC_RMU_3DLUT_CONFIG_STATUS;\697 type MPC_RMU_3DLUT_READ_SEL;\698 type MPC_RMU_3DLUT_INDEX;\699 type MPC_RMU_3DLUT_DATA0;\700 type MPC_RMU_3DLUT_DATA1;\701 type MPC_RMU_3DLUT_DATA_30BIT;\702 type MPC_RMU_SHAPER_LUT_MODE;\703 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\704 type MPC_RMU_SHAPER_OFFSET_R;\705 type MPC_RMU_SHAPER_OFFSET_G;\706 type MPC_RMU_SHAPER_OFFSET_B;\707 type MPC_RMU_SHAPER_SCALE_R;\708 type MPC_RMU_SHAPER_SCALE_G;\709 type MPC_RMU_SHAPER_SCALE_B;\710 type MPC_RMU_SHAPER_LUT_INDEX;\711 type MPC_RMU_SHAPER_LUT_DATA;\712 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\713 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\714 type MPC_RMU_SHAPER_CONFIG_STATUS;\715 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\716 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\717 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\718 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\719 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\720 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\721 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\722 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\723 type MPC_RMU_SHAPER_MODE_CURRENT724 725#define MPC_REG_FIELD_LIST_DCN32(type) \726 type MPCC_MOVABLE_CM_LOCATION_CNTL;\727 type MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT;\728 type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\729 type MPCC_MCM_SHAPER_MEM_PWR_DIS;\730 type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\731 type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\732 type MPCC_MCM_3DLUT_MEM_PWR_DIS;\733 type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\734 type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\735 type MPCC_MCM_1DLUT_MEM_PWR_DIS;\736 type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\737 type MPCC_MCM_SHAPER_MEM_PWR_STATE;\738 type MPCC_MCM_3DLUT_MEM_PWR_STATE;\739 type MPCC_MCM_1DLUT_MEM_PWR_STATE;\740 type MPCC_MCM_3DLUT_MODE; \741 type MPCC_MCM_3DLUT_SIZE; \742 type MPCC_MCM_3DLUT_MODE_CURRENT; \743 type MPCC_MCM_3DLUT_WRITE_EN_MASK;\744 type MPCC_MCM_3DLUT_RAM_SEL;\745 type MPCC_MCM_3DLUT_30BIT_EN;\746 type MPCC_MCM_3DLUT_CONFIG_STATUS;\747 type MPCC_MCM_3DLUT_READ_SEL;\748 type MPCC_MCM_3DLUT_INDEX;\749 type MPCC_MCM_3DLUT_DATA0;\750 type MPCC_MCM_3DLUT_DATA1;\751 type MPCC_MCM_3DLUT_DATA_30BIT;\752 type MPCC_MCM_SHAPER_LUT_MODE;\753 type MPCC_MCM_SHAPER_MODE_CURRENT;\754 type MPCC_MCM_SHAPER_OFFSET_R;\755 type MPCC_MCM_SHAPER_OFFSET_G;\756 type MPCC_MCM_SHAPER_OFFSET_B;\757 type MPCC_MCM_SHAPER_SCALE_R;\758 type MPCC_MCM_SHAPER_SCALE_G;\759 type MPCC_MCM_SHAPER_SCALE_B;\760 type MPCC_MCM_SHAPER_LUT_INDEX;\761 type MPCC_MCM_SHAPER_LUT_DATA;\762 type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\763 type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\764 type MPCC_MCM_SHAPER_CONFIG_STATUS;\765 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\766 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\767 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\768 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\769 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\770 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\771 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\772 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \773 type MPCC_MCM_1DLUT_MODE;\774 type MPCC_MCM_1DLUT_SELECT;\775 type MPCC_MCM_1DLUT_PWL_DISABLE;\776 type MPCC_MCM_1DLUT_MODE_CURRENT;\777 type MPCC_MCM_1DLUT_SELECT_CURRENT;\778 type MPCC_MCM_1DLUT_LUT_INDEX;\779 type MPCC_MCM_1DLUT_LUT_DATA;\780 type MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK;\781 type MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL;\782 type MPCC_MCM_1DLUT_LUT_HOST_SEL;\783 type MPCC_MCM_1DLUT_LUT_CONFIG_MODE;\784 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;\785 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;\786 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;\787 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B;\788 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;\789 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;\790 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;\791 type MPCC_MCM_1DLUT_RAMA_OFFSET_B;\792 type MPCC_MCM_1DLUT_RAMA_OFFSET_G;\793 type MPCC_MCM_1DLUT_RAMA_OFFSET_R;\794 type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;\795 type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;\796 type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;\797 type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS798 799 800#define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \801 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\802 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\803 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\804 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\805 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\806 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\807 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\808 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\809 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\810 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\811 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\812 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\813 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\814 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\815 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\816 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\817 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\818 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\819 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\820 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\821 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\822 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\823 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\824 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\825 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\826 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\827 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\828 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\829 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\830 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\831 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\832 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \833 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \834 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \835 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\836 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\837 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\838 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\839 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\840 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\841 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\842 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\843 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\844 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\845 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\846 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\847 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\848 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\849 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\850 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\851 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\852 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\853 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\854 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\855 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\856 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\857 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\858 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\859 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\860 /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\861 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\862 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\863 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\864 /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\865 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\866 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\867 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\868 /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\869 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\870 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\871 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\872 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\873 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\874 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\875 /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\876 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\877 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\878 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\879 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\880 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\881 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\882 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\883 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\884 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\885 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\886 /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\887 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\888 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\889 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\890 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\891 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\892 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\893 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\894 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\895 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\896 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\897 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\898 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\899 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\900 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\901 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)902 903#define MPC_REG_FIELD_LIST_DCN3_03(type) \904 MPC_REG_FIELD_LIST_DCN2_0(type) \905 type MPC_DWB0_MUX;\906 type MPC_DWB0_MUX_STATUS;\907 type MPC_OUT_RATE_CONTROL;\908 type MPC_OUT_RATE_CONTROL_DISABLE;\909 type MPC_OUT_FLOW_CONTROL_MODE;\910 type MPC_OUT_FLOW_CONTROL_COUNT; \911 type MPCC_GAMUT_REMAP_MODE; \912 type MPCC_GAMUT_REMAP_MODE_CURRENT;\913 type MPCC_GAMUT_REMAP_COEF_FORMAT; \914 type MPCC_GAMUT_REMAP_C11_A; \915 type MPCC_GAMUT_REMAP_C12_A; \916 type MPC_RMU0_MUX; \917 type MPC_RMU0_MUX_STATUS; \918 type MPC_RMU0_MEM_PWR_FORCE;\919 type MPC_RMU0_MEM_PWR_DIS;\920 type MPC_RMU0_MEM_LOW_PWR_MODE;\921 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\922 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\923 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \924 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\925 type MPCC_OGAM_RAMA_OFFSET_B;\926 type MPCC_OGAM_RAMA_OFFSET_G;\927 type MPCC_OGAM_RAMA_OFFSET_R;\928 type MPCC_OGAM_SELECT; \929 type MPCC_OGAM_PWL_DISABLE; \930 type MPCC_OGAM_MODE_CURRENT; \931 type MPCC_OGAM_SELECT_CURRENT; \932 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \933 type MPCC_OGAM_LUT_READ_COLOR_SEL; \934 type MPCC_OGAM_LUT_READ_DBG; \935 type MPCC_OGAM_LUT_HOST_SEL; \936 type MPCC_OGAM_LUT_CONFIG_MODE; \937 type MPCC_OGAM_LUT_STATUS; \938 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\939 type MPCC_OGAM_MEM_LOW_PWR_MODE;\940 type MPCC_OGAM_MEM_PWR_STATE;\941 type MPC_RMU_3DLUT_MODE; \942 type MPC_RMU_3DLUT_SIZE; \943 type MPC_RMU_3DLUT_MODE_CURRENT; \944 type MPC_RMU_3DLUT_WRITE_EN_MASK;\945 type MPC_RMU_3DLUT_RAM_SEL;\946 type MPC_RMU_3DLUT_30BIT_EN;\947 type MPC_RMU_3DLUT_CONFIG_STATUS;\948 type MPC_RMU_3DLUT_READ_SEL;\949 type MPC_RMU_3DLUT_INDEX;\950 type MPC_RMU_3DLUT_DATA0;\951 type MPC_RMU_3DLUT_DATA1;\952 type MPC_RMU_3DLUT_DATA_30BIT;\953 type MPC_RMU_SHAPER_LUT_MODE;\954 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\955 type MPC_RMU_SHAPER_OFFSET_R;\956 type MPC_RMU_SHAPER_OFFSET_G;\957 type MPC_RMU_SHAPER_OFFSET_B;\958 type MPC_RMU_SHAPER_SCALE_R;\959 type MPC_RMU_SHAPER_SCALE_G;\960 type MPC_RMU_SHAPER_SCALE_B;\961 type MPC_RMU_SHAPER_LUT_INDEX;\962 type MPC_RMU_SHAPER_LUT_DATA;\963 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\964 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\965 type MPC_RMU_SHAPER_CONFIG_STATUS;\966 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\967 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\968 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\969 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\970 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\971 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\972 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\973 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\974 type MPC_RMU_SHAPER_MODE_CURRENT975 976struct dcn30_mpc_registers {977 MPC_REG_VARIABLE_LIST_DCN3_0;978 MPC_REG_VARIABLE_LIST_DCN32;979};980 981struct dcn30_mpc_shift {982 MPC_REG_FIELD_LIST_DCN3_0(uint8_t);983 MPC_REG_FIELD_LIST_DCN32(uint8_t);984};985 986struct dcn30_mpc_mask {987 MPC_REG_FIELD_LIST_DCN3_0(uint32_t);988 MPC_REG_FIELD_LIST_DCN32(uint32_t);989};990 991struct dcn30_mpc {992 struct mpc base;993 994 int mpcc_in_use_mask;995 int num_mpcc;996 const struct dcn30_mpc_registers *mpc_regs;997 const struct dcn30_mpc_shift *mpc_shift;998 const struct dcn30_mpc_mask *mpc_mask;999 int num_rmu;1000};1001 1002void dcn30_mpc_construct(struct dcn30_mpc *mpc30,1003 struct dc_context *ctx,1004 const struct dcn30_mpc_registers *mpc_regs,1005 const struct dcn30_mpc_shift *mpc_shift,1006 const struct dcn30_mpc_mask *mpc_mask,1007 int num_mpcc,1008 int num_rmu);1009 1010void mpc3_mpc_init(1011 struct mpc *mpc);1012 1013void mpc3_mpc_init_single_inst(1014 struct mpc *mpc,1015 unsigned int mpcc_id);1016 1017bool mpc3_program_shaper(1018 struct mpc *mpc,1019 const struct pwl_params *params,1020 uint32_t rmu_idx);1021 1022bool mpc3_program_3dlut(1023 struct mpc *mpc,1024 const struct tetrahedral_params *params,1025 int rmu_idx);1026 1027uint32_t mpcc3_acquire_rmu(struct mpc *mpc,1028 int mpcc_id, int rmu_idx);1029 1030void mpc3_set_denorm(1031 struct mpc *mpc,1032 int opp_id,1033 enum dc_color_depth output_depth);1034 1035void mpc3_set_denorm_clamp(1036 struct mpc *mpc,1037 int opp_id,1038 struct mpc_denorm_clamp denorm_clamp);1039 1040void mpc3_set_output_csc(1041 struct mpc *mpc,1042 int opp_id,1043 const uint16_t *regval,1044 enum mpc_output_csc_mode ocsc_mode);1045 1046void mpc3_set_ocsc_default(1047 struct mpc *mpc,1048 int opp_id,1049 enum dc_color_space color_space,1050 enum mpc_output_csc_mode ocsc_mode);1051 1052void mpc3_set_output_gamma(1053 struct mpc *mpc,1054 int mpcc_id,1055 const struct pwl_params *params);1056 1057uint32_t mpc3_get_rmu_mux_status(1058 struct mpc *mpc,1059 int rmu_idx);1060 1061void mpc3_set_gamut_remap(1062 struct mpc *mpc,1063 int mpcc_id,1064 const struct mpc_grph_gamut_adjustment *adjust);1065 1066void mpc3_get_gamut_remap(struct mpc *mpc,1067 int mpcc_id,1068 struct mpc_grph_gamut_adjustment *adjust);1069 1070void mpc3_set_rmu_mux(1071 struct mpc *mpc,1072 int rmu_idx,1073 int value);1074 1075void mpc3_set_dwb_mux(1076 struct mpc *mpc,1077 int dwb_id,1078 int mpcc_id);1079 1080void mpc3_disable_dwb_mux(1081 struct mpc *mpc,1082 int dwb_id);1083 1084bool mpc3_is_dwb_idle(1085 struct mpc *mpc,1086 int dwb_id);1087 1088void mpc3_power_on_ogam_lut(1089 struct mpc *mpc, int mpcc_id,1090 bool power_on);1091 1092void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);1093 1094enum dc_lut_mode mpc3_get_ogam_current(1095 struct mpc *mpc,1096 int mpcc_id);1097 1098#endif1099