175 lines · c
1/* Copyright 2012-15 Advanced Micro Devices, Inc.2 *3 * Permission is hereby granted, free of charge, to any person obtaining a4 * copy of this software and associated documentation files (the "Software"),5 * to deal in the Software without restriction, including without limitation6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,7 * and/or sell copies of the Software, and to permit persons to whom the8 * Software is furnished to do so, subject to the following conditions:9 *10 * The above copyright notice and this permission notice shall be included in11 * all copies or substantial portions of the Software.12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19 * OTHER DEALINGS IN THE SOFTWARE.20 *21 * Authors: AMD22 *23 */24 25#ifndef __DC_OPP_DCN20_H__26#define __DC_OPP_DCN20_H__27 28#include "dcn10/dcn10_opp.h"29 30#define TO_DCN20_OPP(opp)\31 container_of(opp, struct dcn20_opp, base)32 33#define OPP_SF(reg_name, field_name, post_fix)\34 .field_name = reg_name ## __ ## field_name ## post_fix35 36#define OPP_DPG_REG_LIST(id) \37 SRI(DPG_CONTROL, DPG, id), \38 SRI(DPG_DIMENSIONS, DPG, id), \39 SRI(DPG_OFFSET_SEGMENT, DPG, id), \40 SRI(DPG_COLOUR_B_CB, DPG, id), \41 SRI(DPG_COLOUR_G_Y, DPG, id), \42 SRI(DPG_COLOUR_R_CR, DPG, id), \43 SRI(DPG_RAMP_CONTROL, DPG, id), \44 SRI(DPG_STATUS, DPG, id)45 46#define OPP_REG_LIST_DCN20(id) \47 OPP_REG_LIST_DCN10(id), \48 OPP_DPG_REG_LIST(id), \49 SRI(FMT_422_CONTROL, FMT, id), \50 SRI(OPPBUF_CONTROL1, OPPBUF, id)51 52#define OPP_REG_VARIABLE_LIST_DCN2_0 \53 OPP_COMMON_REG_VARIABLE_LIST; \54 uint32_t FMT_422_CONTROL; \55 uint32_t DPG_CONTROL; \56 uint32_t DPG_DIMENSIONS; \57 uint32_t DPG_OFFSET_SEGMENT; \58 uint32_t DPG_COLOUR_B_CB; \59 uint32_t DPG_COLOUR_G_Y; \60 uint32_t DPG_COLOUR_R_CR; \61 uint32_t DPG_RAMP_CONTROL; \62 uint32_t DPG_STATUS63 64#define OPP_DPG_MASK_SH_LIST(mask_sh) \65 OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \66 OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \67 OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \68 OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \69 OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \70 OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \71 OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \72 OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \73 OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_X_OFFSET, mask_sh), \74 OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_SEGMENT_WIDTH, mask_sh), \75 OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \76 OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \77 OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \78 OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \79 OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \80 OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \81 OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \82 OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \83 OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \84 OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh)85 86#define OPP_MASK_SH_LIST_DCN20(mask_sh) \87 OPP_MASK_SH_LIST_DCN(mask_sh), \88 OPP_DPG_MASK_SH_LIST(mask_sh), \89 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\90 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \91 OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh)92 93#define OPP_DCN20_REG_FIELD_LIST(type) \94 OPP_DCN10_REG_FIELD_LIST(type); \95 type FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT; \96 type DPG_EN; \97 type DPG_MODE; \98 type DPG_DYNAMIC_RANGE; \99 type DPG_BIT_DEPTH; \100 type DPG_VRES; \101 type DPG_HRES; \102 type DPG_ACTIVE_WIDTH; \103 type DPG_ACTIVE_HEIGHT; \104 type DPG_X_OFFSET; \105 type DPG_SEGMENT_WIDTH; \106 type DPG_COLOUR0_R_CR; \107 type DPG_COLOUR1_R_CR; \108 type DPG_COLOUR0_B_CB; \109 type DPG_COLOUR1_B_CB; \110 type DPG_COLOUR0_G_Y; \111 type DPG_COLOUR1_G_Y; \112 type DPG_RAMP0_OFFSET; \113 type DPG_INC0; \114 type DPG_INC1; \115 type DPG_DOUBLE_BUFFER_PENDING116 117struct dcn20_opp_registers {118 OPP_REG_VARIABLE_LIST_DCN2_0;119};120 121struct dcn20_opp_shift {122 OPP_DCN20_REG_FIELD_LIST(uint8_t);123};124 125struct dcn20_opp_mask {126 OPP_DCN20_REG_FIELD_LIST(uint32_t);127};128 129struct dcn20_opp {130 struct output_pixel_processor base;131 132 const struct dcn20_opp_registers *regs;133 const struct dcn20_opp_shift *opp_shift;134 const struct dcn20_opp_mask *opp_mask;135 136 bool is_write_to_ram_a_safe;137};138 139void dcn20_opp_construct(struct dcn20_opp *oppn20,140 struct dc_context *ctx,141 uint32_t inst,142 const struct dcn20_opp_registers *regs,143 const struct dcn20_opp_shift *opp_shift,144 const struct dcn20_opp_mask *opp_mask);145 146void opp2_set_disp_pattern_generator(147 struct output_pixel_processor *opp,148 enum controller_dp_test_pattern test_pattern,149 enum controller_dp_color_space color_space,150 enum dc_color_depth color_depth,151 const struct tg_color *solid_color,152 int width,153 int height,154 int offset);155 156void opp2_program_dpg_dimensions(157 struct output_pixel_processor *opp,158 int width, int height);159 160bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);161 162bool opp2_dpg_is_pending(struct output_pixel_processor *opp);163 164void opp2_dpg_set_blank_color(165 struct output_pixel_processor *opp,166 const struct tg_color *color);167 168void opp2_program_left_edge_extra_pixel (169 struct output_pixel_processor *opp,170 enum dc_pixel_encoding pixel_encoding, bool is_primary);171 172uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,173 enum dc_pixel_encoding pixel_encoding, bool is_primary);174#endif175