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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dcn35_opp.h"28#include "reg_helper.h"29 30#define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg31 32#undef FN33#define FN(reg_name, field_name) \34 ((const struct dcn35_opp_shift *)(oppn20->opp_shift))->field_name, \35 ((const struct dcn35_opp_mask *)(oppn20->opp_mask))->field_name36 37#define CTX oppn20->base.ctx38 39void dcn35_opp_construct(struct dcn20_opp *oppn20, struct dc_context *ctx,40 uint32_t inst, const struct dcn35_opp_registers *regs,41 const struct dcn35_opp_shift *opp_shift,42 const struct dcn35_opp_mask *opp_mask)43{44 dcn20_opp_construct(oppn20, ctx, inst,45 (const struct dcn20_opp_registers *)regs,46 (const struct dcn20_opp_shift *)opp_shift,47 (const struct dcn20_opp_mask *)opp_mask);48}49 50void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable)51{52 REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable);53}54