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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "reg_helper.h"27#include "dcn201_optc.h"28#include "dcn10/dcn10_optc.h"29#include "dc.h"30 31#define REG(reg)\32 optc1->tg_regs->reg33 34#define CTX \35 optc1->base.ctx36 37#undef FN38#define FN(reg_name, field_name) \39 optc1->tg_shift->field_name, optc1->tg_mask->field_name40 41static void optc201_triplebuffer_lock(struct timing_generator *optc)42{43 struct optc *optc1 = DCN10TG_FROM_TG(optc);44 45 REG_SET(OTG_GLOBAL_CONTROL0, 0,46 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);47 REG_SET(OTG_VUPDATE_KEEPOUT, 0,48 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);49 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,50 OTG_MASTER_UPDATE_LOCK, 1);51 52 REG_WAIT(OTG_MASTER_UPDATE_LOCK,53 UPDATE_LOCK_STATUS, 1,54 1, 10);55}56 57static void optc201_triplebuffer_unlock(struct timing_generator *optc)58{59 struct optc *optc1 = DCN10TG_FROM_TG(optc);60 61 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,62 OTG_MASTER_UPDATE_LOCK, 0);63 REG_SET(OTG_VUPDATE_KEEPOUT, 0,64 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);65 66}67 68static bool optc201_validate_timing(69 struct timing_generator *optc,70 const struct dc_crtc_timing *timing)71{72 uint32_t v_blank;73 uint32_t h_blank;74 uint32_t min_v_blank;75 struct optc *optc1 = DCN10TG_FROM_TG(optc);76 77 ASSERT(timing != NULL);78 79 v_blank = (timing->v_total - timing->v_addressable -80 timing->v_border_top - timing->v_border_bottom);81 82 h_blank = (timing->h_total - timing->h_addressable -83 timing->h_border_right -84 timing->h_border_left);85 86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&89 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&90 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&91 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)92 return false;93 94 /* Check maximum number of pixels supported by Timing Generator95 * (Currently will never fail, in order to fail needs display which96 * needs more than 8192 horizontal and97 * more than 8192 vertical total pixels)98 */99 if (timing->h_total > optc1->max_h_total ||100 timing->v_total > optc1->max_v_total)101 return false;102 103 if (h_blank < optc1->min_h_blank)104 return false;105 106 if (timing->h_sync_width < optc1->min_h_sync_width ||107 timing->v_sync_width < optc1->min_v_sync_width)108 return false;109 110 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;111 112 if (v_blank < min_v_blank)113 return false;114 115 return true;116 117}118 119static void optc201_get_optc_source(struct timing_generator *optc,120 uint32_t *num_of_src_opp,121 uint32_t *src_opp_id_0,122 uint32_t *src_opp_id_1)123{124 struct optc *optc1 = DCN10TG_FROM_TG(optc);125 126 REG_GET(OPTC_DATA_SOURCE_SELECT,127 OPTC_SEG0_SRC_SEL, src_opp_id_0);128 129 *num_of_src_opp = 1;130}131 132static struct timing_generator_funcs dcn201_tg_funcs = {133 .validate_timing = optc201_validate_timing,134 .program_timing = optc1_program_timing,135 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,136 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,137 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,138 .program_global_sync = optc1_program_global_sync,139 .enable_crtc = optc2_enable_crtc,140 .disable_crtc = optc1_disable_crtc,141 /* used by enable_timing_synchronization. Not need for FPGA */142 .is_counter_moving = optc1_is_counter_moving,143 .get_position = optc1_get_position,144 .get_frame_count = optc1_get_vblank_counter,145 .get_scanoutpos = optc1_get_crtc_scanoutpos,146 .get_otg_active_size = optc1_get_otg_active_size,147 .set_early_control = optc1_set_early_control,148 /* used by enable_timing_synchronization. Not need for FPGA */149 .wait_for_state = optc1_wait_for_state,150 .set_blank = optc1_set_blank,151 .is_blanked = optc1_is_blanked,152 .set_blank_color = optc1_program_blank_color,153 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,154 .enable_reset_trigger = optc1_enable_reset_trigger,155 .enable_crtc_reset = optc1_enable_crtc_reset,156 .disable_reset_trigger = optc1_disable_reset_trigger,157 .triplebuffer_lock = optc201_triplebuffer_lock,158 .triplebuffer_unlock = optc201_triplebuffer_unlock,159 .lock = optc1_lock,160 .unlock = optc1_unlock,161 .enable_optc_clock = optc1_enable_optc_clock,162 .set_drr = optc1_set_drr,163 .get_last_used_drr_vtotal = NULL,164 .set_vtotal_min_max = optc1_set_vtotal_min_max,165 .set_static_screen_control = optc1_set_static_screen_control,166 .program_stereo = optc1_program_stereo,167 .is_stereo_left_eye = optc1_is_stereo_left_eye,168 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,169 .tg_init = optc1_tg_init,170 .is_tg_enabled = optc1_is_tg_enabled,171 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,172 .clear_optc_underflow = optc1_clear_optc_underflow,173 .get_crc = optc1_get_crc,174 .configure_crc = optc2_configure_crc,175 .set_dsc_config = optc2_set_dsc_config,176 .set_dwb_source = NULL,177 .get_optc_source = optc201_get_optc_source,178 .set_vtg_params = optc1_set_vtg_params,179 .program_manual_trigger = optc2_program_manual_trigger,180 .setup_manual_trigger = optc2_setup_manual_trigger,181 .get_hw_timing = optc1_get_hw_timing,182 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,183};184 185void dcn201_timing_generator_init(struct optc *optc1)186{187 optc1->base.funcs = &dcn201_tg_funcs;188 189 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;190 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;191 192 optc1->min_h_blank = 32;193 optc1->min_v_blank = 3;194 optc1->min_v_blank_interlace = 5;195 optc1->min_h_sync_width = 8;196 optc1->min_v_sync_width = 1;197}198