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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "dcn31_optc.h"27 28#include "dcn30/dcn30_optc.h"29#include "reg_helper.h"30#include "dc.h"31#include "dcn_calc_math.h"32 33#define REG(reg)\34 optc1->tg_regs->reg35 36#define CTX \37 optc1->base.ctx38 39#undef FN40#define FN(reg_name, field_name) \41 optc1->tg_shift->field_name, optc1->tg_mask->field_name42 43static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,44 int segment_width, int last_segment_width)45{46 struct optc *optc1 = DCN10TG_FROM_TG(optc);47 uint32_t memory_mask = 0;48 int mem_count_per_opp = (segment_width + 2559) / 2560;49 50 /* Assume less than 6 pipes */51 if (opp_cnt == 4) {52 if (mem_count_per_opp == 1)53 memory_mask = 0xf;54 else {55 ASSERT(mem_count_per_opp == 2);56 memory_mask = 0xff;57 }58 } else if (mem_count_per_opp == 1)59 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);60 else if (mem_count_per_opp == 2)61 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);62 else if (mem_count_per_opp == 3)63 memory_mask = 0x77;64 else if (mem_count_per_opp == 4)65 memory_mask = 0xff;66 67 if (REG(OPTC_MEMORY_CONFIG))68 REG_SET(OPTC_MEMORY_CONFIG, 0,69 OPTC_MEM_SEL, memory_mask);70 71 if (opp_cnt == 2) {72 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,73 OPTC_NUM_OF_INPUT_SEGMENT, 1,74 OPTC_SEG0_SRC_SEL, opp_id[0],75 OPTC_SEG1_SRC_SEL, opp_id[1]);76 } else if (opp_cnt == 4) {77 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,78 OPTC_NUM_OF_INPUT_SEGMENT, 3,79 OPTC_SEG0_SRC_SEL, opp_id[0],80 OPTC_SEG1_SRC_SEL, opp_id[1],81 OPTC_SEG2_SRC_SEL, opp_id[2],82 OPTC_SEG3_SRC_SEL, opp_id[3]);83 }84 85 REG_UPDATE(OPTC_WIDTH_CONTROL,86 OPTC_SEGMENT_WIDTH, segment_width);87 88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);89 optc1->opp_count = opp_cnt;90}91 92/*93 * Enable CRTC - call ASIC Control Object to enable Timing generator.94 */95static bool optc31_enable_crtc(struct timing_generator *optc)96{97 struct optc *optc1 = DCN10TG_FROM_TG(optc);98 99 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */100 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,101 OPTC_SEG0_SRC_SEL, optc->inst);102 103 /* VTG enable first is for HW workaround */104 REG_UPDATE(CONTROL,105 VTG0_ENABLE, 1);106 107 REG_SEQ_START();108 109 /* Enable CRTC */110 REG_UPDATE_2(OTG_CONTROL,111 OTG_DISABLE_POINT_CNTL, 2,112 OTG_MASTER_EN, 1);113 114 REG_SEQ_SUBMIT();115 REG_SEQ_WAIT_DONE();116 117 return true;118}119 120/* disable_crtc - call ASIC Control Object to disable Timing generator. */121static bool optc31_disable_crtc(struct timing_generator *optc)122{123 struct optc *optc1 = DCN10TG_FROM_TG(optc);124 125 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,126 OPTC_SEG0_SRC_SEL, 0xf,127 OPTC_SEG1_SRC_SEL, 0xf,128 OPTC_SEG2_SRC_SEL, 0xf,129 OPTC_SEG3_SRC_SEL, 0xf,130 OPTC_NUM_OF_INPUT_SEGMENT, 0);131 132 REG_UPDATE(OPTC_MEMORY_CONFIG,133 OPTC_MEM_SEL, 0);134 135 /* disable otg request until end of the first line136 * in the vertical blank region137 */138 REG_UPDATE(OTG_CONTROL,139 OTG_MASTER_EN, 0);140 141 REG_UPDATE(CONTROL,142 VTG0_ENABLE, 0);143 144 /* CRTC disabled, so disable clock. */145 REG_WAIT(OTG_CLOCK_CONTROL,146 OTG_BUSY, 0,147 1, 100000);148 optc1_clear_optc_underflow(optc);149 150 return true;151}152/*153 * Immediate_Disable_Crtc - this is to temp disable Timing generator without reset ODM.154 */155bool optc31_immediate_disable_crtc(struct timing_generator *optc)156{157 struct optc *optc1 = DCN10TG_FROM_TG(optc);158 159 REG_UPDATE_2(OTG_CONTROL,160 OTG_DISABLE_POINT_CNTL, 0,161 OTG_MASTER_EN, 0);162 163 REG_UPDATE(CONTROL,164 VTG0_ENABLE, 0);165 166 /* CRTC disabled, so disable clock. */167 if (optc->ctx->dce_environment != DCE_ENV_DIAG)168 REG_WAIT(OTG_CLOCK_CONTROL,169 OTG_BUSY, 0,170 1, 100000);171 172 173 /* clear the false state */174 optc1_clear_optc_underflow(optc);175 176 return true;177}178 179void optc31_set_drr(180 struct timing_generator *optc,181 const struct drr_params *params)182{183 struct optc *optc1 = DCN10TG_FROM_TG(optc);184 185 if (params != NULL &&186 params->vertical_total_max > 0 &&187 params->vertical_total_min > 0) {188 189 if (params->vertical_total_mid != 0) {190 191 REG_SET(OTG_V_TOTAL_MID, 0,192 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);193 194 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,195 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,196 OTG_VTOTAL_MID_FRAME_NUM,197 (uint8_t)params->vertical_total_mid_frame_num);198 199 }200 201 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);202 203 /*204 * MIN_MASK_EN is gone and MASK is now always enabled.205 *206 * To get it to it work with manual trigger we need to make sure207 * we program the correct bit.208 */209 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,210 OTG_V_TOTAL_MIN_SEL, 1,211 OTG_V_TOTAL_MAX_SEL, 1,212 OTG_FORCE_LOCK_ON_EVENT, 0,213 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */214 215 // Setup manual flow control for EOF via TRIG_A216 optc->funcs->setup_manual_trigger(optc);217 } else {218 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,219 OTG_SET_V_TOTAL_MIN_MASK, 0,220 OTG_V_TOTAL_MIN_SEL, 0,221 OTG_V_TOTAL_MAX_SEL, 0,222 OTG_FORCE_LOCK_ON_EVENT, 0);223 224 optc->funcs->set_vtotal_min_max(optc, 0, 0);225 }226}227 228void optc3_init_odm(struct timing_generator *optc)229{230 struct optc *optc1 = DCN10TG_FROM_TG(optc);231 232 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,233 OPTC_NUM_OF_INPUT_SEGMENT, 0,234 OPTC_SEG0_SRC_SEL, optc->inst,235 OPTC_SEG1_SRC_SEL, 0xf,236 OPTC_SEG2_SRC_SEL, 0xf,237 OPTC_SEG3_SRC_SEL, 0xf238 );239 240 REG_SET(OTG_H_TIMING_CNTL, 0,241 OTG_H_TIMING_DIV_MODE, 0);242 243 REG_SET(OPTC_MEMORY_CONFIG, 0,244 OPTC_MEM_SEL, 0);245 optc1->opp_count = 1;246}247 248static struct timing_generator_funcs dcn31_tg_funcs = {249 .validate_timing = optc1_validate_timing,250 .program_timing = optc1_program_timing,251 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,252 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,253 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,254 .program_global_sync = optc1_program_global_sync,255 .enable_crtc = optc31_enable_crtc,256 .disable_crtc = optc31_disable_crtc,257 .immediate_disable_crtc = optc31_immediate_disable_crtc,258 /* used by enable_timing_synchronization. Not need for FPGA */259 .is_counter_moving = optc1_is_counter_moving,260 .get_position = optc1_get_position,261 .get_frame_count = optc1_get_vblank_counter,262 .get_scanoutpos = optc1_get_crtc_scanoutpos,263 .get_otg_active_size = optc1_get_otg_active_size,264 .set_early_control = optc1_set_early_control,265 /* used by enable_timing_synchronization. Not need for FPGA */266 .wait_for_state = optc1_wait_for_state,267 .set_blank_color = optc3_program_blank_color,268 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,269 .triplebuffer_lock = optc3_triplebuffer_lock,270 .triplebuffer_unlock = optc2_triplebuffer_unlock,271 .enable_reset_trigger = optc1_enable_reset_trigger,272 .enable_crtc_reset = optc1_enable_crtc_reset,273 .disable_reset_trigger = optc1_disable_reset_trigger,274 .lock = optc3_lock,275 .unlock = optc1_unlock,276 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,277 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,278 .enable_optc_clock = optc1_enable_optc_clock,279 .set_drr = optc31_set_drr,280 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,281 .set_vtotal_min_max = optc1_set_vtotal_min_max,282 .set_static_screen_control = optc1_set_static_screen_control,283 .program_stereo = optc1_program_stereo,284 .is_stereo_left_eye = optc1_is_stereo_left_eye,285 .tg_init = optc3_tg_init,286 .is_tg_enabled = optc1_is_tg_enabled,287 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,288 .clear_optc_underflow = optc1_clear_optc_underflow,289 .setup_global_swap_lock = NULL,290 .get_crc = optc1_get_crc,291 .configure_crc = optc2_configure_crc,292 .set_dsc_config = optc3_set_dsc_config,293 .get_dsc_status = optc2_get_dsc_status,294 .set_dwb_source = NULL,295 .set_odm_bypass = optc3_set_odm_bypass,296 .set_odm_combine = optc31_set_odm_combine,297 .get_optc_source = optc2_get_optc_source,298 .set_out_mux = optc3_set_out_mux,299 .set_drr_trigger_window = optc3_set_drr_trigger_window,300 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,301 .set_gsl = optc2_set_gsl,302 .set_gsl_source_select = optc2_set_gsl_source_select,303 .set_vtg_params = optc1_set_vtg_params,304 .program_manual_trigger = optc2_program_manual_trigger,305 .setup_manual_trigger = optc2_setup_manual_trigger,306 .get_hw_timing = optc1_get_hw_timing,307 .init_odm = optc3_init_odm,308 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,309};310 311void dcn31_timing_generator_init(struct optc *optc1)312{313 optc1->base.funcs = &dcn31_tg_funcs;314 315 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;316 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;317 318 optc1->min_h_blank = 32;319 optc1->min_v_blank = 3;320 optc1->min_v_blank_interlace = 5;321 optc1->min_h_sync_width = 4;322 optc1->min_v_sync_width = 1;323}324 325