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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2022 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#ifndef __DC_OPTC_DCN314_H__28#define __DC_OPTC_DCN314_H__29 30#include "dcn10/dcn10_optc.h"31 32#define OPTC_COMMON_REG_LIST_DCN3_14(inst) \33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\35 SRI(OTG_VREADY_PARAM, OTG, inst),\36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\42 SRI(OTG_H_TOTAL, OTG, inst),\43 SRI(OTG_H_BLANK_START_END, OTG, inst),\44 SRI(OTG_H_SYNC_A, OTG, inst),\45 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\47 SRI(OTG_V_TOTAL, OTG, inst),\48 SRI(OTG_V_BLANK_START_END, OTG, inst),\49 SRI(OTG_V_SYNC_A, OTG, inst),\50 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\51 SRI(OTG_CONTROL, OTG, inst),\52 SRI(OTG_STEREO_CONTROL, OTG, inst),\53 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\54 SRI(OTG_STEREO_STATUS, OTG, inst),\55 SRI(OTG_V_TOTAL_MAX, OTG, inst),\56 SRI(OTG_V_TOTAL_MIN, OTG, inst),\57 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\58 SRI(OTG_TRIGA_CNTL, OTG, inst),\59 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\60 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\61 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\62 SRI(OTG_STATUS, OTG, inst),\63 SRI(OTG_STATUS_POSITION, OTG, inst),\64 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\65 SRI(OTG_M_CONST_DTO0, OTG, inst),\66 SRI(OTG_M_CONST_DTO1, OTG, inst),\67 SRI(OTG_CLOCK_CONTROL, OTG, inst),\68 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\69 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\70 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\71 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\72 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\73 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\74 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\75 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\76 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\77 SRI(CONTROL, VTG, inst),\78 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\79 SRI(OTG_GSL_CONTROL, OTG, inst),\80 SRI(OTG_CRC_CNTL, OTG, inst),\81 SRI(OTG_CRC0_DATA_RG, OTG, inst),\82 SRI(OTG_CRC0_DATA_B, OTG, inst),\83 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\84 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\85 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\86 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\87 SR(GSL_SOURCE_SELECT),\88 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\89 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\90 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\91 SRI(OTG_GSL_WINDOW_X, OTG, inst),\92 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\93 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\94 SRI(OTG_DSC_START_POSITION, OTG, inst),\95 SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\96 SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\97 SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\98 SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\99 SRI(OPTC_WIDTH_CONTROL, ODM, inst),\100 SRI(OPTC_MEMORY_CONFIG, ODM, inst),\101 SRI(OTG_DRR_CONTROL, OTG, inst)102 103#define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\104 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\105 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\107 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\108 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\110 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\113 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\114 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\115 SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\116 SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\117 SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\118 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\120 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\121 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\122 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\123 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\124 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\126 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\127 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\128 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\129 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\130 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\131 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\133 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\134 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\135 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\137 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\138 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\139 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\140 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\141 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\142 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\143 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\144 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\145 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\146 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\147 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\148 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\149 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\150 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\151 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\152 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\153 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\154 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\155 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\156 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\157 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\158 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\159 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\160 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\161 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\162 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\163 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\164 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\165 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\166 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\167 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\169 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\170 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\171 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\172 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\173 SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\174 SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\175 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\176 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\177 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\178 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\179 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\180 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\181 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\182 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\183 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\184 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\185 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\186 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\187 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\188 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\189 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\190 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\194 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\195 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\196 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\197 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\198 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\199 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\200 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\201 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\202 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\203 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\204 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\206 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\208 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\209 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\210 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\211 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\212 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\213 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\214 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\215 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\216 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\217 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\218 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\219 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\220 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\221 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\222 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\223 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\224 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \225 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\226 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\227 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \228 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \229 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \230 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \231 SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \232 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \233 SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\234 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\235 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\236 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\237 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\238 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\239 SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\240 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\241 SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\242 SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\243 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\244 SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\245 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\246 SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\247 SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\248 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\249 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\250 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\251 SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)252 253void dcn314_timing_generator_init(struct optc *optc1);254 255#endif /* __DC_OPTC_DCN314_H__ */256