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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dcn35_optc.h"28 29#include "dcn30/dcn30_optc.h"30#include "dcn31/dcn31_optc.h"31#include "dcn32/dcn32_optc.h"32#include "reg_helper.h"33#include "dc.h"34#include "dcn_calc_math.h"35#include "dc_dmub_srv.h"36 37#define REG(reg)\38 optc1->tg_regs->reg39 40#define CTX \41 optc1->base.ctx42 43#undef FN44#define FN(reg_name, field_name) \45 optc1->tg_shift->field_name, optc1->tg_mask->field_name46 47/**48 * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.49 *50 * @optc: Output Pipe Timing Combine instance reference.51 * @opp_id: Output Plane Processor instance ID.52 * @opp_cnt: Output Plane Processor count.53 * @segment_width: Width of the segment.54 * @last_segment_width: Width of the last segment.55 *56 * Return: void.57 */58static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,59 int segment_width, int last_segment_width)60{61 struct optc *optc1 = DCN10TG_FROM_TG(optc);62 uint32_t memory_mask = 0;63 int h_active = segment_width * opp_cnt;64 /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */65 int odm_mem_count = (h_active + 2047) / 2048;66 67 /*68 * display <= 4k : 2 memories + 2 pipes69 * 4k < display <= 8k : 4 memories + 2 pipes70 * 8k < display <= 12k : 6 memories + 4 pipes71 */72 if (opp_cnt == 4) {73 if (odm_mem_count <= 2)74 memory_mask = 0x3;75 else if (odm_mem_count <= 4)76 memory_mask = 0xf;77 else78 memory_mask = 0x3f;79 } else {80 if (odm_mem_count <= 2)81 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);82 else if (odm_mem_count <= 4)83 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);84 else85 memory_mask = 0x77;86 }87 88 REG_SET(OPTC_MEMORY_CONFIG, 0,89 OPTC_MEM_SEL, memory_mask);90 91 if (opp_cnt == 2) {92 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,93 OPTC_NUM_OF_INPUT_SEGMENT, 1,94 OPTC_SEG0_SRC_SEL, opp_id[0],95 OPTC_SEG1_SRC_SEL, opp_id[1]);96 } else if (opp_cnt == 4) {97 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,98 OPTC_NUM_OF_INPUT_SEGMENT, 3,99 OPTC_SEG0_SRC_SEL, opp_id[0],100 OPTC_SEG1_SRC_SEL, opp_id[1],101 OPTC_SEG2_SRC_SEL, opp_id[2],102 OPTC_SEG3_SRC_SEL, opp_id[3]);103 }104 105 REG_UPDATE(OPTC_WIDTH_CONTROL,106 OPTC_SEGMENT_WIDTH, segment_width);107 108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);109 optc1->opp_count = opp_cnt;110}111 112static bool optc35_enable_crtc(struct timing_generator *optc)113{114 struct optc *optc1 = DCN10TG_FROM_TG(optc);115 116 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */117 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,118 OPTC_SEG0_SRC_SEL, optc->inst);119 120 /* VTG enable first is for HW workaround */121 REG_UPDATE(CONTROL,122 VTG0_ENABLE, 1);123 124 REG_SEQ_START();125 126 /* Enable CRTC */127 REG_UPDATE_2(OTG_CONTROL,128 OTG_DISABLE_POINT_CNTL, 2,129 OTG_MASTER_EN, 1);130 131 REG_SEQ_SUBMIT();132 REG_SEQ_WAIT_DONE();133 134 return true;135}136 137/* disable_crtc */138static bool optc35_disable_crtc(struct timing_generator *optc)139{140 struct optc *optc1 = DCN10TG_FROM_TG(optc);141 142 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,143 OPTC_SEG0_SRC_SEL, 0xf,144 OPTC_SEG1_SRC_SEL, 0xf,145 OPTC_SEG2_SRC_SEL, 0xf,146 OPTC_SEG3_SRC_SEL, 0xf,147 OPTC_NUM_OF_INPUT_SEGMENT, 0);148 149 REG_UPDATE(OPTC_MEMORY_CONFIG,150 OPTC_MEM_SEL, 0);151 152 /* disable otg request until end of the first line153 * in the vertical blank region154 */155 REG_UPDATE(OTG_CONTROL,156 OTG_MASTER_EN, 0);157 158 REG_UPDATE(CONTROL,159 VTG0_ENABLE, 0);160 161 /* CRTC disabled, so disable clock. */162 REG_WAIT(OTG_CLOCK_CONTROL,163 OTG_BUSY, 0,164 1, 100000);165 optc1_clear_optc_underflow(optc);166 167 return true;168}169 170static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)171{172 struct optc *optc1 = DCN10TG_FROM_TG(optc);173 174 /* Disable immediately. */175 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);176 177 /* CRTC disabled, so disable clock. */178 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);179}180 181static bool optc35_configure_crc(struct timing_generator *optc,182 const struct crc_params *params)183{184 struct optc *optc1 = DCN10TG_FROM_TG(optc);185 186 if (!optc1_is_tg_enabled(optc))187 return false;188 REG_WRITE(OTG_CRC_CNTL, 0);189 if (!params->enable)190 return true;191 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,192 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,193 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);194 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,195 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,196 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);197 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,198 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,199 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);200 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,201 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,202 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);203 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) {204 REG_UPDATE_4(OTG_CRC_CNTL,205 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,206 OTG_CRC0_SELECT, params->selection,207 OTG_CRC_EN, 1,208 OTG_CRC_WINDOW_DB_EN, 1);209 } else210 REG_UPDATE_3(OTG_CRC_CNTL,211 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,212 OTG_CRC0_SELECT, params->selection,213 OTG_CRC_EN, 1);214 return true;215}216 217static void optc35_setup_manual_trigger(struct timing_generator *optc)218{219 if (!optc || !optc->ctx)220 return;221 222 struct optc *optc1 = DCN10TG_FROM_TG(optc);223 struct dc *dc = optc->ctx->dc;224 225 if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)226 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);227 else {228 /*229 * MIN_MASK_EN is gone and MASK is now always enabled.230 *231 * To get it to it work with manual trigger we need to make sure232 * we program the correct bit.233 */234 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,235 OTG_V_TOTAL_MIN_SEL, 1,236 OTG_V_TOTAL_MAX_SEL, 1,237 OTG_FORCE_LOCK_ON_EVENT, 0,238 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */239 240 // Setup manual flow control for EOF via TRIG_A241 if (optc->funcs && optc->funcs->setup_manual_trigger)242 optc->funcs->setup_manual_trigger(optc);243 }244}245 246void optc35_set_drr(247 struct timing_generator *optc,248 const struct drr_params *params)249{250 if (!optc || !params)251 return;252 253 struct optc *optc1 = DCN10TG_FROM_TG(optc);254 uint32_t max_otg_v_total = optc1->max_v_total - 1;255 256 if (params != NULL &&257 params->vertical_total_max > 0 &&258 params->vertical_total_min > 0) {259 260 if (params->vertical_total_mid != 0) {261 262 REG_SET(OTG_V_TOTAL_MID, 0,263 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);264 265 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,266 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,267 OTG_VTOTAL_MID_FRAME_NUM,268 (uint8_t)params->vertical_total_mid_frame_num);269 270 }271 272 if (optc->funcs && optc->funcs->set_vtotal_min_max)273 optc->funcs->set_vtotal_min_max(optc,274 params->vertical_total_min - 1, params->vertical_total_max - 1);275 optc35_setup_manual_trigger(optc);276 } else {277 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,278 OTG_SET_V_TOTAL_MIN_MASK, 0,279 OTG_V_TOTAL_MIN_SEL, 0,280 OTG_V_TOTAL_MAX_SEL, 0,281 OTG_FORCE_LOCK_ON_EVENT, 0);282 283 if (optc->funcs && optc->funcs->set_vtotal_min_max)284 optc->funcs->set_vtotal_min_max(optc, 0, 0);285 }286 287 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);288 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);289}290 291static void optc35_set_long_vtotal(292 struct timing_generator *optc,293 const struct long_vtotal_params *params)294{295 if (!optc || !params)296 return;297 298 struct optc *optc1 = DCN10TG_FROM_TG(optc);299 uint32_t vcount_stop_timer = 0, vcount_stop = 0;300 uint32_t max_otg_v_total = optc1->max_v_total - 1;301 302 if (params->vertical_total_min <= max_otg_v_total && params->vertical_total_max <= max_otg_v_total)303 return;304 305 if (params->vertical_total_max == 0 || params->vertical_total_min == 0) {306 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,307 OTG_SET_V_TOTAL_MIN_MASK, 0,308 OTG_V_TOTAL_MIN_SEL, 0,309 OTG_V_TOTAL_MAX_SEL, 0,310 OTG_FORCE_LOCK_ON_EVENT, 0);311 312 if (optc->funcs && optc->funcs->set_vtotal_min_max)313 optc->funcs->set_vtotal_min_max(optc, 0, 0);314 } else if (params->vertical_total_max == params->vertical_total_min) {315 vcount_stop = params->vertical_blank_start;316 vcount_stop_timer = params->vertical_total_max - max_otg_v_total;317 318 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,319 OTG_V_TOTAL_MIN_SEL, 1,320 OTG_V_TOTAL_MAX_SEL, 1,321 OTG_FORCE_LOCK_ON_EVENT, 0,322 OTG_SET_V_TOTAL_MIN_MASK, 0);323 324 if (optc->funcs && optc->funcs->set_vtotal_min_max)325 optc->funcs->set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);326 327 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);328 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);329 } else {330 // Variable rate, keep DRR trigger mask331 if (params->vertical_total_min > max_otg_v_total) {332 // cannot be supported333 // If MAX_OTG_V_COUNT < DRR trigger < v_total_min < v_total_max,334 // DRR trigger will drop the vtotal counting directly to a new frame.335 // But it should trigger between v_total_min and v_total_max.336 ASSERT(0);337 338 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,339 OTG_SET_V_TOTAL_MIN_MASK, 0,340 OTG_V_TOTAL_MIN_SEL, 0,341 OTG_V_TOTAL_MAX_SEL, 0,342 OTG_FORCE_LOCK_ON_EVENT, 0);343 344 if (optc->funcs && optc->funcs->set_vtotal_min_max)345 optc->funcs->set_vtotal_min_max(optc, 0, 0);346 347 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);348 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);349 } else {350 // For total_min <= MAX_OTG_V_COUNT and total_max > MAX_OTG_V_COUNT351 vcount_stop = params->vertical_total_min;352 vcount_stop_timer = params->vertical_total_max - max_otg_v_total;353 354 // Example:355 // params->vertical_total_min 1000356 // params->vertical_total_max 2000357 // MAX_OTG_V_COUNT_STOP = 1500358 //359 // If DRR event not happened,360 // time 0,1,2,3,4,...1000,1001,........,1500,1501,1502, ...1999361 // vcount 0,1,2,3,4....1000...................,1001,1002,1003,...1399362 // vcount2 0,1,2,3,4,..499,363 // else (DRR event happened, ex : at line 1004)364 // time 0,1,2,3,4,...1000,1001.....1004, 0365 // vcount 0,1,2,3,4....1000,.............. 0 (new frame)366 // vcount2 0,1,2, 3, -367 if (optc->funcs && optc->funcs->set_vtotal_min_max)368 optc->funcs->set_vtotal_min_max(optc,369 params->vertical_total_min - 1, max_otg_v_total);370 optc35_setup_manual_trigger(optc);371 372 REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);373 REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);374 }375 }376}377 378static struct timing_generator_funcs dcn35_tg_funcs = {379 .validate_timing = optc1_validate_timing,380 .program_timing = optc1_program_timing,381 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,382 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,383 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,384 .program_global_sync = optc1_program_global_sync,385 .enable_crtc = optc35_enable_crtc,386 .disable_crtc = optc35_disable_crtc,387 .immediate_disable_crtc = optc31_immediate_disable_crtc,388 .phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,389 /* used by enable_timing_synchronization. Not need for FPGA */390 .is_counter_moving = optc1_is_counter_moving,391 .get_position = optc1_get_position,392 .get_frame_count = optc1_get_vblank_counter,393 .get_scanoutpos = optc1_get_crtc_scanoutpos,394 .get_otg_active_size = optc1_get_otg_active_size,395 .set_early_control = optc1_set_early_control,396 /* used by enable_timing_synchronization. Not need for FPGA */397 .wait_for_state = optc1_wait_for_state,398 .set_blank_color = optc3_program_blank_color,399 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,400 .triplebuffer_lock = optc3_triplebuffer_lock,401 .triplebuffer_unlock = optc2_triplebuffer_unlock,402 .enable_reset_trigger = optc1_enable_reset_trigger,403 .enable_crtc_reset = optc1_enable_crtc_reset,404 .disable_reset_trigger = optc1_disable_reset_trigger,405 .lock = optc3_lock,406 .unlock = optc1_unlock,407 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,408 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,409 .enable_optc_clock = optc1_enable_optc_clock,410 .set_drr = optc35_set_drr,411 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,412 .set_vtotal_min_max = optc1_set_vtotal_min_max,413 .set_static_screen_control = optc1_set_static_screen_control,414 .program_stereo = optc1_program_stereo,415 .is_stereo_left_eye = optc1_is_stereo_left_eye,416 .tg_init = optc3_tg_init,417 .is_tg_enabled = optc1_is_tg_enabled,418 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,419 .clear_optc_underflow = optc1_clear_optc_underflow,420 .setup_global_swap_lock = NULL,421 .get_crc = optc1_get_crc,422 .configure_crc = optc35_configure_crc,423 .set_dsc_config = optc3_set_dsc_config,424 .get_dsc_status = optc2_get_dsc_status,425 .set_dwb_source = NULL,426 .set_odm_bypass = optc32_set_odm_bypass,427 .set_odm_combine = optc35_set_odm_combine,428 .get_optc_source = optc2_get_optc_source,429 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,430 .set_out_mux = optc3_set_out_mux,431 .set_drr_trigger_window = optc3_set_drr_trigger_window,432 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,433 .set_gsl = optc2_set_gsl,434 .set_gsl_source_select = optc2_set_gsl_source_select,435 .set_vtg_params = optc1_set_vtg_params,436 .program_manual_trigger = optc2_program_manual_trigger,437 .setup_manual_trigger = optc2_setup_manual_trigger,438 .get_hw_timing = optc1_get_hw_timing,439 .init_odm = optc3_init_odm,440 .set_long_vtotal = optc35_set_long_vtotal,441 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,442};443 444void dcn35_timing_generator_init(struct optc *optc1)445{446 optc1->base.funcs = &dcn35_tg_funcs;447 448 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;449 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;450 451 optc1->min_h_blank = 32;452 optc1->min_v_blank = 3;453 optc1->min_v_blank_interlace = 5;454 optc1->min_h_sync_width = 4;455 optc1->min_v_sync_width = 1;456 457 dcn35_timing_generator_set_fgcg(458 optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);459}460 461void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)462{463 REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);464}465