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1// SPDX-License-Identifier: MIT2//3// Copyright 2024 Advanced Micro Devices, Inc.4 5#include "dcn401_optc.h"6#include "dcn30/dcn30_optc.h"7#include "dcn31/dcn31_optc.h"8#include "dcn32/dcn32_optc.h"9#include "reg_helper.h"10#include "dc.h"11#include "dcn_calc_math.h"12#include "dc_dmub_srv.h"13 14#define REG(reg)\15 optc1->tg_regs->reg16 17#define CTX \18 optc1->base.ctx19 20#undef FN21#define FN(reg_name, field_name) \22 optc1->tg_shift->field_name, optc1->tg_mask->field_name23 24/*25 * OPTC uses ODM_MEM sub block to merge pixel data coming from different OPPs26 * into unified memory location per horizontal line. ODM_MEM contains shared27 * memory resources global to the ASIC. Each memory resource is capable of28 * storing 2048 pixels independent from actual pixel data size. Total number of29 * memory allocated must be even. The memory resource allocation is described in30 * a memory bit map per OPTC instance. Driver has to make sure that there is no31 * double allocation across different OPTC instances. Bit offset in the map32 * represents memory instance id. Driver allocates a memory instance to the33 * current OPTC by setting the bit with offset associated with the desired34 * memory instance to 1 in the current OPTC memory map register.35 *36 * It is upto software to decide how to allocate the shared memory resources37 * across different OPTC instances. Driver understands that the total number38 * of memory available is always 2 times the max number of OPP pipes. So each39 * OPP pipe can be mapped 2 pieces of memory. However there exists cases such as40 * 11520x2160 which could use 6 pieces of memory for 2 OPP pipes i.e. 3 pieces41 * for each OPP pipe.42 *43 * Driver will reserve the first and second preferred memory instances for each44 * OPP pipe. For example, OPP0's first and second preferred memory is ODM_MEM045 * and ODM_MEM1. OPP1's first and second preferred memory is ODM_MEM2 and46 * ODM_MEM3 so on so forth.47 *48 * Driver will first allocate from first preferred memory instances associated49 * with current OPP pipes in use. If needed driver will then allocate from50 * second preferred memory instances associated with current OPP pipes in use.51 * Finally if still needed, driver will allocate from second preferred memory52 * instances not associated with current OPP pipes. So if memory instances are53 * enough other OPTCs can still allocate from their OPPs' first preferred memory54 * instances without worrying about double allocation.55 */56 57static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active)58{59 bool first_preferred_memory_for_opp[MAX_PIPES] = {0};60 bool second_preferred_memory_for_opp[MAX_PIPES] = {0};61 uint32_t memory_bit_map = 0;62 int total_required = ((h_active + 4095) / 4096) * 2;63 int total_allocated = 0;64 int i;65 66 for (i = 0; i < opp_cnt; i++) {67 first_preferred_memory_for_opp[opp_id[i]] = true;68 total_allocated++;69 if (total_required == total_allocated)70 break;71 }72 73 if (total_required > total_allocated) {74 for (i = 0; i < opp_cnt; i++) {75 second_preferred_memory_for_opp[opp_id[i]] = true;76 total_allocated++;77 if (total_required == total_allocated)78 break;79 }80 }81 82 if (total_required > total_allocated) {83 for (i = 0; i < MAX_PIPES; i++) {84 if (second_preferred_memory_for_opp[i] == false) {85 second_preferred_memory_for_opp[i] = true;86 total_allocated++;87 if (total_required == total_allocated)88 break;89 }90 }91 }92 ASSERT(total_required == total_allocated);93 94 for (i = 0; i < MAX_PIPES; i++) {95 if (first_preferred_memory_for_opp[i])96 memory_bit_map |= 0x1 << (i * 2);97 if (second_preferred_memory_for_opp[i])98 memory_bit_map |= 0x2 << (i * 2);99 }100 101 return memory_bit_map;102}103 104static void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,105 int opp_cnt, int segment_width, int last_segment_width)106{107 struct optc *optc1 = DCN10TG_FROM_TG(optc);108 uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width;109 uint32_t odm_mem_bit_map = decide_odm_mem_bit_map(110 opp_id, opp_cnt, h_active);111 112 REG_SET(OPTC_MEMORY_CONFIG, 0,113 OPTC_MEM_SEL, odm_mem_bit_map);114 115 switch (opp_cnt) {116 case 2: /* ODM Combine 2:1 */117 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,118 OPTC_NUM_OF_INPUT_SEGMENT, 1,119 OPTC_SEG0_SRC_SEL, opp_id[0],120 OPTC_SEG1_SRC_SEL, opp_id[1]);121 REG_UPDATE(OPTC_WIDTH_CONTROL,122 OPTC_SEGMENT_WIDTH, segment_width);123 124 REG_UPDATE(OTG_H_TIMING_CNTL,125 OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY2);126 break;127 case 3: /* ODM Combine 3:1 */128 REG_SET_4(OPTC_DATA_SOURCE_SELECT, 0,129 OPTC_NUM_OF_INPUT_SEGMENT, 2,130 OPTC_SEG0_SRC_SEL, opp_id[0],131 OPTC_SEG1_SRC_SEL, opp_id[1],132 OPTC_SEG2_SRC_SEL, opp_id[2]);133 REG_UPDATE(OPTC_WIDTH_CONTROL,134 OPTC_SEGMENT_WIDTH, segment_width);135 REG_UPDATE(OPTC_WIDTH_CONTROL2,136 OPTC_SEGMENT_WIDTH_LAST,137 last_segment_width);138 /* In ODM combine 3:1 mode ODM packs 4 pixels per data transfer139 * so OTG_H_TIMING_DIV_MODE should be configured to140 * H_TIMING_DIV_BY4 even though ODM combines 3 OPP inputs, it141 * outputs 4 pixels from single OPP at a time.142 */143 REG_UPDATE(OTG_H_TIMING_CNTL,144 OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);145 break;146 case 4: /* ODM Combine 4:1 */147 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,148 OPTC_NUM_OF_INPUT_SEGMENT, 3,149 OPTC_SEG0_SRC_SEL, opp_id[0],150 OPTC_SEG1_SRC_SEL, opp_id[1],151 OPTC_SEG2_SRC_SEL, opp_id[2],152 OPTC_SEG3_SRC_SEL, opp_id[3]);153 REG_UPDATE(OPTC_WIDTH_CONTROL,154 OPTC_SEGMENT_WIDTH, segment_width);155 REG_UPDATE(OTG_H_TIMING_CNTL,156 OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);157 break;158 default:159 ASSERT(false);160 }161;162 optc1->opp_count = opp_cnt;163}164 165static void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)166{167 struct optc *optc1 = DCN10TG_FROM_TG(optc);168 169 REG_UPDATE(OTG_H_TIMING_CNTL,170 OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);171}172/**173 * optc401_enable_crtc() - Enable CRTC174 * @optc: Pointer to the timing generator structure175 *176 * This function calls ASIC Control Object to enable Timing generator.177 *178 * Return: Always returns true179 */180static bool optc401_enable_crtc(struct timing_generator *optc)181{182 struct optc *optc1 = DCN10TG_FROM_TG(optc);183 184 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */185 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,186 OPTC_SEG0_SRC_SEL, optc->inst);187 188 /* VTG enable first is for HW workaround */189 REG_UPDATE(CONTROL,190 VTG0_ENABLE, 1);191 192 REG_SEQ_START();193 194 /* Enable CRTC */195 REG_UPDATE_2(OTG_CONTROL,196 OTG_DISABLE_POINT_CNTL, 2,197 OTG_MASTER_EN, 1);198 199 REG_SEQ_SUBMIT();200 REG_SEQ_WAIT_DONE();201 202 return true;203}204 205/* disable_crtc */206static bool optc401_disable_crtc(struct timing_generator *optc)207{208 struct optc *optc1 = DCN10TG_FROM_TG(optc);209 210 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,211 OPTC_SEG0_SRC_SEL, 0xf,212 OPTC_SEG1_SRC_SEL, 0xf,213 OPTC_SEG2_SRC_SEL, 0xf,214 OPTC_SEG3_SRC_SEL, 0xf,215 OPTC_NUM_OF_INPUT_SEGMENT, 0);216 217 REG_UPDATE(OPTC_MEMORY_CONFIG,218 OPTC_MEM_SEL, 0);219 220 /* disable otg request until end of the first line221 * in the vertical blank region222 */223 REG_UPDATE(OTG_CONTROL,224 OTG_MASTER_EN, 0);225 226 REG_UPDATE(CONTROL,227 VTG0_ENABLE, 0);228 229 /* CRTC disabled, so disable clock. */230 REG_WAIT(OTG_CLOCK_CONTROL,231 OTG_BUSY, 0,232 1, 150000);233 234 return true;235}236 237static void optc401_phantom_crtc_post_enable(struct timing_generator *optc)238{239 struct optc *optc1 = DCN10TG_FROM_TG(optc);240 241 /* Disable immediately. */242 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);243 244 /* CRTC disabled, so disable clock. */245 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);246}247 248static void optc401_disable_phantom_otg(struct timing_generator *optc)249{250 struct optc *optc1 = DCN10TG_FROM_TG(optc);251 252 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,253 OPTC_SEG0_SRC_SEL, 0xf,254 OPTC_SEG1_SRC_SEL, 0xf,255 OPTC_SEG2_SRC_SEL, 0xf,256 OPTC_SEG3_SRC_SEL, 0xf,257 OPTC_NUM_OF_INPUT_SEGMENT, 0);258 259 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);260}261 262static void optc401_set_odm_bypass(struct timing_generator *optc,263 const struct dc_crtc_timing *dc_crtc_timing)264{265 struct optc *optc1 = DCN10TG_FROM_TG(optc);266 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;267 268 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,269 OPTC_NUM_OF_INPUT_SEGMENT, 0,270 OPTC_SEG0_SRC_SEL, optc->inst,271 OPTC_SEG1_SRC_SEL, 0xf,272 OPTC_SEG2_SRC_SEL, 0xf,273 OPTC_SEG3_SRC_SEL, 0xf274 );275 276 h_div = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);277 REG_UPDATE(OTG_H_TIMING_CNTL,278 OTG_H_TIMING_DIV_MODE, h_div);279 280 REG_SET(OPTC_MEMORY_CONFIG, 0,281 OPTC_MEM_SEL, 0);282 optc1->opp_count = 1;283}284 285/* only to be used when FAMS2 is disabled or unsupported */286void optc401_setup_manual_trigger(struct timing_generator *optc)287{288 struct optc *optc1 = DCN10TG_FROM_TG(optc);289 struct dc *dc = optc->ctx->dc;290 291 if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams)292 /* FAMS */293 dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);294 else {295 /*296 * MIN_MASK_EN is gone and MASK is now always enabled.297 *298 * To get it to it work with manual trigger we need to make sure299 * we program the correct bit.300 */301 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,302 OTG_V_TOTAL_MIN_SEL, 1,303 OTG_V_TOTAL_MAX_SEL, 1,304 OTG_FORCE_LOCK_ON_EVENT, 0,305 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */306 }307}308 309void optc401_set_drr(310 struct timing_generator *optc,311 const struct drr_params *params)312{313 struct optc *optc1 = DCN10TG_FROM_TG(optc);314 struct dc *dc = optc->ctx->dc;315 struct drr_params amended_params = { 0 };316 bool program_manual_trigger = false;317 318 if (dc->caps.dmub_caps.fams_ver >= 2 && dc->debug.fams2_config.bits.enable) {319 if (params != NULL &&320 params->vertical_total_max > 0 &&321 params->vertical_total_min > 0) {322 amended_params.vertical_total_max = params->vertical_total_max - 1;323 amended_params.vertical_total_min = params->vertical_total_min - 1;324 if (params->vertical_total_mid != 0) {325 amended_params.vertical_total_mid = params->vertical_total_mid - 1;326 amended_params.vertical_total_mid_frame_num = params->vertical_total_mid_frame_num;327 }328 program_manual_trigger = true;329 }330 331 dc_dmub_srv_fams2_drr_update(dc, optc->inst,332 amended_params.vertical_total_min,333 amended_params.vertical_total_max,334 amended_params.vertical_total_mid,335 amended_params.vertical_total_mid_frame_num,336 program_manual_trigger);337 } else {338 if (params != NULL &&339 params->vertical_total_max > 0 &&340 params->vertical_total_min > 0) {341 342 if (params->vertical_total_mid != 0) {343 344 REG_SET(OTG_V_TOTAL_MID, 0,345 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);346 347 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,348 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,349 OTG_VTOTAL_MID_FRAME_NUM,350 (uint8_t)params->vertical_total_mid_frame_num);351 352 }353 354 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);355 optc401_setup_manual_trigger(optc);356 } else {357 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,358 OTG_SET_V_TOTAL_MIN_MASK, 0,359 OTG_V_TOTAL_MIN_SEL, 0,360 OTG_V_TOTAL_MAX_SEL, 0,361 OTG_FORCE_LOCK_ON_EVENT, 0);362 363 optc->funcs->set_vtotal_min_max(optc, 0, 0);364 }365 }366}367 368static void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)369{370 struct optc *optc1 = DCN10TG_FROM_TG(optc);371 372 /* 00 - OTG_CONTROL_OTG_OUT_MUX_0 : Connects to DIO.373 01 - OTG_CONTROL_OTG_OUT_MUX_1 : Reserved.374 02 - OTG_CONTROL_OTG_OUT_MUX_2 : Connects to HPO.375 */376 REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);377}378 379void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)380{381 struct dc *dc = optc->ctx->dc;382 383 if (dc->caps.dmub_caps.fams_ver >= 2 && dc->debug.fams2_config.bits.enable) {384 /* FAMS2 */385 dc_dmub_srv_fams2_drr_update(dc, optc->inst,386 vtotal_min,387 vtotal_max,388 0,389 0,390 false);391 } else if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams) {392 /* FAMS */393 dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);394 } else {395 optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);396 }397}398 399static void optc401_program_global_sync(400 struct timing_generator *optc,401 int vready_offset,402 int vstartup_start,403 int vupdate_offset,404 int vupdate_width,405 int pstate_keepout)406{407 struct optc *optc1 = DCN10TG_FROM_TG(optc);408 409 optc1->vready_offset = vready_offset;410 optc1->vstartup_start = vstartup_start;411 optc1->vupdate_offset = vupdate_offset;412 optc1->vupdate_width = vupdate_width;413 optc1->pstate_keepout = pstate_keepout;414 415 if (optc1->vstartup_start == 0) {416 BREAK_TO_DEBUGGER();417 return;418 }419 420 REG_SET(OTG_VSTARTUP_PARAM, 0,421 VSTARTUP_START, optc1->vstartup_start);422 423 REG_SET_2(OTG_VUPDATE_PARAM, 0,424 VUPDATE_OFFSET, optc1->vupdate_offset,425 VUPDATE_WIDTH, optc1->vupdate_width);426 427 REG_SET(OTG_VREADY_PARAM, 0,428 VREADY_OFFSET, optc1->vready_offset);429 430 REG_UPDATE(OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, pstate_keepout);431}432 433static struct timing_generator_funcs dcn401_tg_funcs = {434 .validate_timing = optc1_validate_timing,435 .program_timing = optc1_program_timing,436 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,437 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,438 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,439 .program_global_sync = optc401_program_global_sync,440 .enable_crtc = optc401_enable_crtc,441 .disable_crtc = optc401_disable_crtc,442 .phantom_crtc_post_enable = optc401_phantom_crtc_post_enable,443 .disable_phantom_crtc = optc401_disable_phantom_otg,444 /* used by enable_timing_synchronization. Not need for FPGA */445 .is_counter_moving = optc1_is_counter_moving,446 .get_position = optc1_get_position,447 .get_frame_count = optc1_get_vblank_counter,448 .get_scanoutpos = optc1_get_crtc_scanoutpos,449 .get_otg_active_size = optc1_get_otg_active_size,450 .set_early_control = optc1_set_early_control,451 /* used by enable_timing_synchronization. Not need for FPGA */452 .wait_for_state = optc1_wait_for_state,453 .set_blank_color = optc3_program_blank_color,454 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,455 .triplebuffer_lock = optc3_triplebuffer_lock,456 .triplebuffer_unlock = optc2_triplebuffer_unlock,457 .enable_reset_trigger = optc1_enable_reset_trigger,458 .enable_crtc_reset = optc1_enable_crtc_reset,459 .disable_reset_trigger = optc1_disable_reset_trigger,460 .lock = optc3_lock,461 .unlock = optc1_unlock,462 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,463 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,464 .enable_optc_clock = optc1_enable_optc_clock,465 .set_drr = optc401_set_drr,466 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,467 .set_vtotal_min_max = optc401_set_vtotal_min_max,468 .set_static_screen_control = optc1_set_static_screen_control,469 .program_stereo = optc1_program_stereo,470 .is_stereo_left_eye = optc1_is_stereo_left_eye,471 .tg_init = optc3_tg_init,472 .is_tg_enabled = optc1_is_tg_enabled,473 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,474 .clear_optc_underflow = optc1_clear_optc_underflow,475 .setup_global_swap_lock = NULL,476 .get_crc = optc1_get_crc,477 .configure_crc = optc1_configure_crc,478 .set_dsc_config = optc3_set_dsc_config,479 .get_dsc_status = optc2_get_dsc_status,480 .set_dwb_source = NULL,481 .set_odm_bypass = optc401_set_odm_bypass,482 .set_odm_combine = optc401_set_odm_combine,483 .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear,484 .set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode,485 .get_optc_source = optc2_get_optc_source,486 .set_out_mux = optc401_set_out_mux,487 .set_drr_trigger_window = optc3_set_drr_trigger_window,488 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,489 .set_gsl = optc2_set_gsl,490 .set_gsl_source_select = optc2_set_gsl_source_select,491 .set_vtg_params = optc1_set_vtg_params,492 .program_manual_trigger = optc2_program_manual_trigger,493 .setup_manual_trigger = optc2_setup_manual_trigger,494 .get_hw_timing = optc1_get_hw_timing,495 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,496 .get_double_buffer_pending = optc32_get_double_buffer_pending,497};498 499void dcn401_timing_generator_init(struct optc *optc1)500{501 optc1->base.funcs = &dcn401_tg_funcs;502 503 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;504 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;505 506 optc1->min_h_blank = 32;507 optc1->min_v_blank = 3;508 optc1->min_v_blank_interlace = 5;509 optc1->min_h_sync_width = 4;510 optc1->min_v_sync_width = 1;511}512 513