brintos / linux-shallow public Read only

1/*2* Copyright 2016 Advanced Micro Devices, Inc.3 * Copyright 2019 Raptor Engineering, LLC4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dm_services.h"28#include "dc.h"29 30#include "dcn20/dcn20_init.h"31 32#include "resource.h"33#include "include/irq_service_interface.h"34#include "dcn20/dcn20_resource.h"35 36#include "dml/dcn20/dcn20_fpu.h"37 38#include "dcn10/dcn10_hubp.h"39#include "dcn10/dcn10_ipp.h"40#include "dcn20/dcn20_hubbub.h"41#include "dcn20/dcn20_mpc.h"42#include "dcn20/dcn20_hubp.h"43#include "irq/dcn20/irq_service_dcn20.h"44#include "dcn20/dcn20_dpp.h"45#include "dcn20/dcn20_optc.h"46#include "dcn20/dcn20_hwseq.h"47#include "dce110/dce110_hwseq.h"48#include "dcn10/dcn10_resource.h"49#include "dcn20/dcn20_opp.h"50 51#include "dcn20/dcn20_dsc.h"52 53#include "dcn20/dcn20_link_encoder.h"54#include "dcn20/dcn20_stream_encoder.h"55#include "dce/dce_clock_source.h"56#include "dce/dce_audio.h"57#include "dce/dce_hwseq.h"58#include "virtual/virtual_stream_encoder.h"59#include "dce110/dce110_resource.h"60#include "dml/display_mode_vba.h"61#include "dcn20/dcn20_dccg.h"62#include "dcn20/dcn20_vmid.h"63#include "dce/dce_panel_cntl.h"64 65#include "dcn20/dcn20_dwb.h"66#include "dcn20/dcn20_mmhubbub.h"67 68#include "navi10_ip_offset.h"69 70#include "dcn/dcn_2_0_0_offset.h"71#include "dcn/dcn_2_0_0_sh_mask.h"72#include "dpcs/dpcs_2_0_0_offset.h"73#include "dpcs/dpcs_2_0_0_sh_mask.h"74 75#include "nbio/nbio_2_3_offset.h"76 77#include "mmhub/mmhub_2_0_0_offset.h"78#include "mmhub/mmhub_2_0_0_sh_mask.h"79 80#include "reg_helper.h"81#include "dce/dce_abm.h"82#include "dce/dce_dmcu.h"83#include "dce/dce_aux.h"84#include "dce/dce_i2c.h"85#include "vm_helper.h"86 87#include "link_enc_cfg.h"88#include "link.h"89 90#define DC_LOGGER_INIT(logger)91 92#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL93	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f94	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	295	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f96	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	297	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f98	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	299	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f100	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2101	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f102	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2103	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f104	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2105	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f106	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2107#endif108 109 110enum dcn20_clk_src_array_id {111	DCN20_CLK_SRC_PLL0,112	DCN20_CLK_SRC_PLL1,113	DCN20_CLK_SRC_PLL2,114	DCN20_CLK_SRC_PLL3,115	DCN20_CLK_SRC_PLL4,116	DCN20_CLK_SRC_PLL5,117	DCN20_CLK_SRC_TOTAL118};119 120/* begin *********************121 * macros to expend register list macro defined in HW object header file */122 123/* DCN */124#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg125 126#define BASE(seg) BASE_INNER(seg)127 128#define SR(reg_name)\129		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \130					mm ## reg_name131 132#define SRI(reg_name, block, id)\133	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \134					mm ## block ## id ## _ ## reg_name135 136#define SRI2_DWB(reg_name, block, id)\137	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \138					mm ## reg_name139#define SF_DWB(reg_name, field_name, post_fix)\140	.field_name = reg_name ## __ ## field_name ## post_fix141 142#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\143	.field_name = reg_name ## __ ## field_name ## post_fix144 145#define SRIR(var_name, reg_name, block, id)\146	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \147					mm ## block ## id ## _ ## reg_name148 149#define SRII(reg_name, block, id)\150	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \151					mm ## block ## id ## _ ## reg_name152 153#define DCCG_SRII(reg_name, block, id)\154	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \155					mm ## block ## id ## _ ## reg_name156 157#define VUPDATE_SRII(reg_name, block, id)\158	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \159					mm ## reg_name ## _ ## block ## id160 161/* NBIO */162#define NBIO_BASE_INNER(seg) \163	NBIO_BASE__INST0_SEG ## seg164 165#define NBIO_BASE(seg) \166	NBIO_BASE_INNER(seg)167 168#define NBIO_SR(reg_name)\169		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \170					mm ## reg_name171 172/* MMHUB */173#define MMHUB_BASE_INNER(seg) \174	MMHUB_BASE__INST0_SEG ## seg175 176#define MMHUB_BASE(seg) \177	MMHUB_BASE_INNER(seg)178 179#define MMHUB_SR(reg_name)\180		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \181					mmMM ## reg_name182 183static const struct bios_registers bios_regs = {184		NBIO_SR(BIOS_SCRATCH_3),185		NBIO_SR(BIOS_SCRATCH_6)186};187 188#define clk_src_regs(index, pllid)\189[index] = {\190	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\191}192 193static const struct dce110_clk_src_regs clk_src_regs[] = {194	clk_src_regs(0, A),195	clk_src_regs(1, B),196	clk_src_regs(2, C),197	clk_src_regs(3, D),198	clk_src_regs(4, E),199	clk_src_regs(5, F)200};201 202static const struct dce110_clk_src_shift cs_shift = {203		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)204};205 206static const struct dce110_clk_src_mask cs_mask = {207		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)208};209 210static const struct dce_dmcu_registers dmcu_regs = {211		DMCU_DCN10_REG_LIST()212};213 214static const struct dce_dmcu_shift dmcu_shift = {215		DMCU_MASK_SH_LIST_DCN10(__SHIFT)216};217 218static const struct dce_dmcu_mask dmcu_mask = {219		DMCU_MASK_SH_LIST_DCN10(_MASK)220};221 222static const struct dce_abm_registers abm_regs = {223		ABM_DCN20_REG_LIST()224};225 226static const struct dce_abm_shift abm_shift = {227		ABM_MASK_SH_LIST_DCN20(__SHIFT)228};229 230static const struct dce_abm_mask abm_mask = {231		ABM_MASK_SH_LIST_DCN20(_MASK)232};233 234#define audio_regs(id)\235[id] = {\236		AUD_COMMON_REG_LIST(id)\237}238 239static const struct dce_audio_registers audio_regs[] = {240	audio_regs(0),241	audio_regs(1),242	audio_regs(2),243	audio_regs(3),244	audio_regs(4),245	audio_regs(5),246	audio_regs(6),247};248 249#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\250		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\251		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\252		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)253 254static const struct dce_audio_shift audio_shift = {255		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)256};257 258static const struct dce_audio_mask audio_mask = {259		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)260};261 262#define stream_enc_regs(id)\263[id] = {\264	SE_DCN2_REG_LIST(id)\265}266 267static const struct dcn10_stream_enc_registers stream_enc_regs[] = {268	stream_enc_regs(0),269	stream_enc_regs(1),270	stream_enc_regs(2),271	stream_enc_regs(3),272	stream_enc_regs(4),273	stream_enc_regs(5),274};275 276static const struct dcn10_stream_encoder_shift se_shift = {277		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)278};279 280static const struct dcn10_stream_encoder_mask se_mask = {281		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)282};283 284 285#define aux_regs(id)\286[id] = {\287	DCN2_AUX_REG_LIST(id)\288}289 290static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {291		aux_regs(0),292		aux_regs(1),293		aux_regs(2),294		aux_regs(3),295		aux_regs(4),296		aux_regs(5)297};298 299#define hpd_regs(id)\300[id] = {\301	HPD_REG_LIST(id)\302}303 304static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {305		hpd_regs(0),306		hpd_regs(1),307		hpd_regs(2),308		hpd_regs(3),309		hpd_regs(4),310		hpd_regs(5)311};312 313#define link_regs(id, phyid)\314[id] = {\315	LE_DCN10_REG_LIST(id), \316	UNIPHY_DCN2_REG_LIST(phyid), \317	DPCS_DCN2_REG_LIST(id), \318	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \319}320 321static const struct dcn10_link_enc_registers link_enc_regs[] = {322	link_regs(0, A),323	link_regs(1, B),324	link_regs(2, C),325	link_regs(3, D),326	link_regs(4, E),327	link_regs(5, F)328};329 330static const struct dcn10_link_enc_shift le_shift = {331	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\332	DPCS_DCN2_MASK_SH_LIST(__SHIFT)333};334 335static const struct dcn10_link_enc_mask le_mask = {336	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\337	DPCS_DCN2_MASK_SH_LIST(_MASK)338};339 340static const struct dce_panel_cntl_registers panel_cntl_regs[] = {341	{ DCN_PANEL_CNTL_REG_LIST() }342};343 344static const struct dce_panel_cntl_shift panel_cntl_shift = {345	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)346};347 348static const struct dce_panel_cntl_mask panel_cntl_mask = {349	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)350};351 352#define ipp_regs(id)\353[id] = {\354	IPP_REG_LIST_DCN20(id),\355}356 357static const struct dcn10_ipp_registers ipp_regs[] = {358	ipp_regs(0),359	ipp_regs(1),360	ipp_regs(2),361	ipp_regs(3),362	ipp_regs(4),363	ipp_regs(5),364};365 366static const struct dcn10_ipp_shift ipp_shift = {367		IPP_MASK_SH_LIST_DCN20(__SHIFT)368};369 370static const struct dcn10_ipp_mask ipp_mask = {371		IPP_MASK_SH_LIST_DCN20(_MASK),372};373 374#define opp_regs(id)\375[id] = {\376	OPP_REG_LIST_DCN20(id),\377}378 379static const struct dcn20_opp_registers opp_regs[] = {380	opp_regs(0),381	opp_regs(1),382	opp_regs(2),383	opp_regs(3),384	opp_regs(4),385	opp_regs(5),386};387 388static const struct dcn20_opp_shift opp_shift = {389		OPP_MASK_SH_LIST_DCN20(__SHIFT)390};391 392static const struct dcn20_opp_mask opp_mask = {393		OPP_MASK_SH_LIST_DCN20(_MASK)394};395 396#define aux_engine_regs(id)\397[id] = {\398	AUX_COMMON_REG_LIST0(id), \399	.AUXN_IMPCAL = 0, \400	.AUXP_IMPCAL = 0, \401	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \402}403 404static const struct dce110_aux_registers aux_engine_regs[] = {405		aux_engine_regs(0),406		aux_engine_regs(1),407		aux_engine_regs(2),408		aux_engine_regs(3),409		aux_engine_regs(4),410		aux_engine_regs(5)411};412 413#define tf_regs(id)\414[id] = {\415	TF_REG_LIST_DCN20(id),\416	TF_REG_LIST_DCN20_COMMON_APPEND(id),\417}418 419static const struct dcn2_dpp_registers tf_regs[] = {420	tf_regs(0),421	tf_regs(1),422	tf_regs(2),423	tf_regs(3),424	tf_regs(4),425	tf_regs(5),426};427 428static const struct dcn2_dpp_shift tf_shift = {429		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),430		TF_DEBUG_REG_LIST_SH_DCN20431};432 433static const struct dcn2_dpp_mask tf_mask = {434		TF_REG_LIST_SH_MASK_DCN20(_MASK),435		TF_DEBUG_REG_LIST_MASK_DCN20436};437 438#define dwbc_regs_dcn2(id)\439[id] = {\440	DWBC_COMMON_REG_LIST_DCN2_0(id),\441		}442 443static const struct dcn20_dwbc_registers dwbc20_regs[] = {444	dwbc_regs_dcn2(0),445};446 447static const struct dcn20_dwbc_shift dwbc20_shift = {448	DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)449};450 451static const struct dcn20_dwbc_mask dwbc20_mask = {452	DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)453};454 455#define mcif_wb_regs_dcn2(id)\456[id] = {\457	MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\458		}459 460static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {461	mcif_wb_regs_dcn2(0),462};463 464static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {465	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)466};467 468static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {469	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)470};471 472static const struct dcn20_mpc_registers mpc_regs = {473		MPC_REG_LIST_DCN2_0(0),474		MPC_REG_LIST_DCN2_0(1),475		MPC_REG_LIST_DCN2_0(2),476		MPC_REG_LIST_DCN2_0(3),477		MPC_REG_LIST_DCN2_0(4),478		MPC_REG_LIST_DCN2_0(5),479		MPC_OUT_MUX_REG_LIST_DCN2_0(0),480		MPC_OUT_MUX_REG_LIST_DCN2_0(1),481		MPC_OUT_MUX_REG_LIST_DCN2_0(2),482		MPC_OUT_MUX_REG_LIST_DCN2_0(3),483		MPC_OUT_MUX_REG_LIST_DCN2_0(4),484		MPC_OUT_MUX_REG_LIST_DCN2_0(5),485		MPC_DBG_REG_LIST_DCN2_0()486};487 488static const struct dcn20_mpc_shift mpc_shift = {489	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),490	MPC_DEBUG_REG_LIST_SH_DCN20491};492 493static const struct dcn20_mpc_mask mpc_mask = {494	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),495	MPC_DEBUG_REG_LIST_MASK_DCN20496};497 498#define tg_regs(id)\499[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}500 501 502static const struct dcn_optc_registers tg_regs[] = {503	tg_regs(0),504	tg_regs(1),505	tg_regs(2),506	tg_regs(3),507	tg_regs(4),508	tg_regs(5)509};510 511static const struct dcn_optc_shift tg_shift = {512	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)513};514 515static const struct dcn_optc_mask tg_mask = {516	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)517};518 519#define hubp_regs(id)\520[id] = {\521	HUBP_REG_LIST_DCN20(id)\522}523 524static const struct dcn_hubp2_registers hubp_regs[] = {525		hubp_regs(0),526		hubp_regs(1),527		hubp_regs(2),528		hubp_regs(3),529		hubp_regs(4),530		hubp_regs(5)531};532 533static const struct dcn_hubp2_shift hubp_shift = {534		HUBP_MASK_SH_LIST_DCN20(__SHIFT)535};536 537static const struct dcn_hubp2_mask hubp_mask = {538		HUBP_MASK_SH_LIST_DCN20(_MASK)539};540 541static const struct dcn_hubbub_registers hubbub_reg = {542		HUBBUB_REG_LIST_DCN20(0)543};544 545static const struct dcn_hubbub_shift hubbub_shift = {546		HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)547};548 549static const struct dcn_hubbub_mask hubbub_mask = {550		HUBBUB_MASK_SH_LIST_DCN20(_MASK)551};552 553#define vmid_regs(id)\554[id] = {\555		DCN20_VMID_REG_LIST(id)\556}557 558static const struct dcn_vmid_registers vmid_regs[] = {559	vmid_regs(0),560	vmid_regs(1),561	vmid_regs(2),562	vmid_regs(3),563	vmid_regs(4),564	vmid_regs(5),565	vmid_regs(6),566	vmid_regs(7),567	vmid_regs(8),568	vmid_regs(9),569	vmid_regs(10),570	vmid_regs(11),571	vmid_regs(12),572	vmid_regs(13),573	vmid_regs(14),574	vmid_regs(15)575};576 577static const struct dcn20_vmid_shift vmid_shifts = {578		DCN20_VMID_MASK_SH_LIST(__SHIFT)579};580 581static const struct dcn20_vmid_mask vmid_masks = {582		DCN20_VMID_MASK_SH_LIST(_MASK)583};584 585static const struct dce110_aux_registers_shift aux_shift = {586		DCN_AUX_MASK_SH_LIST(__SHIFT)587};588 589static const struct dce110_aux_registers_mask aux_mask = {590		DCN_AUX_MASK_SH_LIST(_MASK)591};592 593static int map_transmitter_id_to_phy_instance(594	enum transmitter transmitter)595{596	switch (transmitter) {597	case TRANSMITTER_UNIPHY_A:598		return 0;599	break;600	case TRANSMITTER_UNIPHY_B:601		return 1;602	break;603	case TRANSMITTER_UNIPHY_C:604		return 2;605	break;606	case TRANSMITTER_UNIPHY_D:607		return 3;608	break;609	case TRANSMITTER_UNIPHY_E:610		return 4;611	break;612	case TRANSMITTER_UNIPHY_F:613		return 5;614	break;615	default:616		ASSERT(0);617		return 0;618	}619}620 621#define dsc_regsDCN20(id)\622[id] = {\623	DSC_REG_LIST_DCN20(id)\624}625 626static const struct dcn20_dsc_registers dsc_regs[] = {627	dsc_regsDCN20(0),628	dsc_regsDCN20(1),629	dsc_regsDCN20(2),630	dsc_regsDCN20(3),631	dsc_regsDCN20(4),632	dsc_regsDCN20(5)633};634 635static const struct dcn20_dsc_shift dsc_shift = {636	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)637};638 639static const struct dcn20_dsc_mask dsc_mask = {640	DSC_REG_LIST_SH_MASK_DCN20(_MASK)641};642 643static const struct dccg_registers dccg_regs = {644		DCCG_REG_LIST_DCN2()645};646 647static const struct dccg_shift dccg_shift = {648		DCCG_MASK_SH_LIST_DCN2(__SHIFT)649};650 651static const struct dccg_mask dccg_mask = {652		DCCG_MASK_SH_LIST_DCN2(_MASK)653};654 655static const struct resource_caps res_cap_nv10 = {656		.num_timing_generator = 6,657		.num_opp = 6,658		.num_video_plane = 6,659		.num_audio = 7,660		.num_stream_encoder = 6,661		.num_pll = 6,662		.num_dwb = 1,663		.num_ddc = 6,664		.num_vmid = 16,665		.num_dsc = 6,666};667 668static const struct dc_plane_cap plane_cap = {669	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,670	.per_pixel_alpha = true,671 672	.pixel_format_support = {673			.argb8888 = true,674			.nv12 = true,675			.fp16 = true,676			.p010 = true677	},678 679	.max_upscale_factor = {680			.argb8888 = 16000,681			.nv12 = 16000,682			.fp16 = 1683	},684 685	.max_downscale_factor = {686			.argb8888 = 250,687			.nv12 = 250,688			.fp16 = 1689	},690	16,691	16692};693static const struct resource_caps res_cap_nv14 = {694		.num_timing_generator = 5,695		.num_opp = 5,696		.num_video_plane = 5,697		.num_audio = 6,698		.num_stream_encoder = 5,699		.num_pll = 5,700		.num_dwb = 1,701		.num_ddc = 5,702		.num_vmid = 16,703		.num_dsc = 5,704};705 706static const struct dc_debug_options debug_defaults_drv = {707		.disable_dmcu = false,708		.force_abm_enable = false,709		.timing_trace = false,710		.clock_trace = true,711		.disable_pplib_clock_request = true,712		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,713		.force_single_disp_pipe_split = false,714		.disable_dcc = DCC_ENABLE,715		.vsr_support = true,716		.performance_trace = false,717		.max_downscale_src_width = 5120,/*upto 5K*/718		.disable_pplib_wm_range = false,719		.scl_reset_length10 = true,720		.sanity_checks = false,721		.underflow_assert_delay_us = 0xFFFFFFFF,722		.enable_legacy_fast_update = true,723		.using_dml2 = false,724};725 726void dcn20_dpp_destroy(struct dpp **dpp)727{728	kfree(TO_DCN20_DPP(*dpp));729	*dpp = NULL;730}731 732struct dpp *dcn20_dpp_create(733	struct dc_context *ctx,734	uint32_t inst)735{736	struct dcn20_dpp *dpp =737		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);738 739	if (!dpp)740		return NULL;741 742	if (dpp2_construct(dpp, ctx, inst,743			&tf_regs[inst], &tf_shift, &tf_mask))744		return &dpp->base;745 746	BREAK_TO_DEBUGGER();747	kfree(dpp);748	return NULL;749}750 751struct input_pixel_processor *dcn20_ipp_create(752	struct dc_context *ctx, uint32_t inst)753{754	struct dcn10_ipp *ipp =755		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);756 757	if (!ipp) {758		BREAK_TO_DEBUGGER();759		return NULL;760	}761 762	dcn20_ipp_construct(ipp, ctx, inst,763			&ipp_regs[inst], &ipp_shift, &ipp_mask);764	return &ipp->base;765}766 767 768struct output_pixel_processor *dcn20_opp_create(769	struct dc_context *ctx, uint32_t inst)770{771	struct dcn20_opp *opp =772		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);773 774	if (!opp) {775		BREAK_TO_DEBUGGER();776		return NULL;777	}778 779	dcn20_opp_construct(opp, ctx, inst,780			&opp_regs[inst], &opp_shift, &opp_mask);781	return &opp->base;782}783 784struct dce_aux *dcn20_aux_engine_create(785	struct dc_context *ctx,786	uint32_t inst)787{788	struct aux_engine_dce110 *aux_engine =789		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);790 791	if (!aux_engine)792		return NULL;793 794	dce110_aux_engine_construct(aux_engine, ctx, inst,795				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,796				    &aux_engine_regs[inst],797					&aux_mask,798					&aux_shift,799					ctx->dc->caps.extended_aux_timeout_support);800 801	return &aux_engine->base;802}803#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }804 805static const struct dce_i2c_registers i2c_hw_regs[] = {806		i2c_inst_regs(1),807		i2c_inst_regs(2),808		i2c_inst_regs(3),809		i2c_inst_regs(4),810		i2c_inst_regs(5),811		i2c_inst_regs(6),812};813 814static const struct dce_i2c_shift i2c_shifts = {815		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)816};817 818static const struct dce_i2c_mask i2c_masks = {819		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)820};821 822struct dce_i2c_hw *dcn20_i2c_hw_create(823	struct dc_context *ctx,824	uint32_t inst)825{826	struct dce_i2c_hw *dce_i2c_hw =827		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);828 829	if (!dce_i2c_hw)830		return NULL;831 832	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,833				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);834 835	return dce_i2c_hw;836}837struct mpc *dcn20_mpc_create(struct dc_context *ctx)838{839	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),840					  GFP_ATOMIC);841 842	if (!mpc20)843		return NULL;844 845	dcn20_mpc_construct(mpc20, ctx,846			&mpc_regs,847			&mpc_shift,848			&mpc_mask,849			6);850 851	return &mpc20->base;852}853 854struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)855{856	int i;857	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),858					  GFP_ATOMIC);859 860	if (!hubbub)861		return NULL;862 863	hubbub2_construct(hubbub, ctx,864			&hubbub_reg,865			&hubbub_shift,866			&hubbub_mask);867 868	for (i = 0; i < res_cap_nv10.num_vmid; i++) {869		struct dcn20_vmid *vmid = &hubbub->vmid[i];870 871		vmid->ctx = ctx;872 873		vmid->regs = &vmid_regs[i];874		vmid->shifts = &vmid_shifts;875		vmid->masks = &vmid_masks;876	}877 878	return &hubbub->base;879}880 881struct timing_generator *dcn20_timing_generator_create(882		struct dc_context *ctx,883		uint32_t instance)884{885	struct optc *tgn10 =886		kzalloc(sizeof(struct optc), GFP_ATOMIC);887 888	if (!tgn10)889		return NULL;890 891	tgn10->base.inst = instance;892	tgn10->base.ctx = ctx;893 894	tgn10->tg_regs = &tg_regs[instance];895	tgn10->tg_shift = &tg_shift;896	tgn10->tg_mask = &tg_mask;897 898	dcn20_timing_generator_init(tgn10);899 900	return &tgn10->base;901}902 903static const struct encoder_feature_support link_enc_feature = {904		.max_hdmi_deep_color = COLOR_DEPTH_121212,905		.max_hdmi_pixel_clock = 600000,906		.hdmi_ycbcr420_supported = true,907		.dp_ycbcr420_supported = true,908		.fec_supported = true,909		.flags.bits.IS_HBR2_CAPABLE = true,910		.flags.bits.IS_HBR3_CAPABLE = true,911		.flags.bits.IS_TPS3_CAPABLE = true,912		.flags.bits.IS_TPS4_CAPABLE = true913};914 915struct link_encoder *dcn20_link_encoder_create(916	struct dc_context *ctx,917	const struct encoder_init_data *enc_init_data)918{919	struct dcn20_link_encoder *enc20 =920		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);921	int link_regs_id;922 923	if (!enc20)924		return NULL;925 926	link_regs_id =927		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);928 929	dcn20_link_encoder_construct(enc20,930				      enc_init_data,931				      &link_enc_feature,932				      &link_enc_regs[link_regs_id],933				      &link_enc_aux_regs[enc_init_data->channel - 1],934				      &link_enc_hpd_regs[enc_init_data->hpd_source],935				      &le_shift,936				      &le_mask);937 938	return &enc20->enc10.base;939}940 941static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)942{943	struct dce_panel_cntl *panel_cntl =944		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);945 946	if (!panel_cntl)947		return NULL;948 949	dce_panel_cntl_construct(panel_cntl,950			init_data,951			&panel_cntl_regs[init_data->inst],952			&panel_cntl_shift,953			&panel_cntl_mask);954 955	return &panel_cntl->base;956}957 958static struct clock_source *dcn20_clock_source_create(959	struct dc_context *ctx,960	struct dc_bios *bios,961	enum clock_source_id id,962	const struct dce110_clk_src_regs *regs,963	bool dp_clk_src)964{965	struct dce110_clk_src *clk_src =966		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);967 968	if (!clk_src)969		return NULL;970 971	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,972			regs, &cs_shift, &cs_mask)) {973		clk_src->base.dp_clk_src = dp_clk_src;974		return &clk_src->base;975	}976 977	kfree(clk_src);978	BREAK_TO_DEBUGGER();979	return NULL;980}981 982static void read_dce_straps(983	struct dc_context *ctx,984	struct resource_straps *straps)985{986	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),987		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);988}989 990static struct audio *dcn20_create_audio(991		struct dc_context *ctx, unsigned int inst)992{993	return dce_audio_create(ctx, inst,994			&audio_regs[inst], &audio_shift, &audio_mask);995}996 997struct stream_encoder *dcn20_stream_encoder_create(998	enum engine_id eng_id,999	struct dc_context *ctx)1000{1001	struct dcn10_stream_encoder *enc1 =1002		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1003 1004	if (!enc1)1005		return NULL;1006 1007	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {1008		if (eng_id >= ENGINE_ID_DIGD)1009			eng_id++;1010	}1011 1012	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,1013					&stream_enc_regs[eng_id],1014					&se_shift, &se_mask);1015 1016	return &enc1->base;1017}1018 1019static const struct dce_hwseq_registers hwseq_reg = {1020		HWSEQ_DCN2_REG_LIST()1021};1022 1023static const struct dce_hwseq_shift hwseq_shift = {1024		HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)1025};1026 1027static const struct dce_hwseq_mask hwseq_mask = {1028		HWSEQ_DCN2_MASK_SH_LIST(_MASK)1029};1030 1031struct dce_hwseq *dcn20_hwseq_create(1032	struct dc_context *ctx)1033{1034	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1035 1036	if (hws) {1037		hws->ctx = ctx;1038		hws->regs = &hwseq_reg;1039		hws->shifts = &hwseq_shift;1040		hws->masks = &hwseq_mask;1041	}1042	return hws;1043}1044 1045static const struct resource_create_funcs res_create_funcs = {1046	.read_dce_straps = read_dce_straps,1047	.create_audio = dcn20_create_audio,1048	.create_stream_encoder = dcn20_stream_encoder_create,1049	.create_hwseq = dcn20_hwseq_create,1050};1051 1052static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);1053 1054void dcn20_clock_source_destroy(struct clock_source **clk_src)1055{1056	kfree(TO_DCE110_CLK_SRC(*clk_src));1057	*clk_src = NULL;1058}1059 1060 1061struct display_stream_compressor *dcn20_dsc_create(1062	struct dc_context *ctx, uint32_t inst)1063{1064	struct dcn20_dsc *dsc =1065		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);1066 1067	if (!dsc) {1068		BREAK_TO_DEBUGGER();1069		return NULL;1070	}1071 1072	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1073	return &dsc->base;1074}1075 1076void dcn20_dsc_destroy(struct display_stream_compressor **dsc)1077{1078	kfree(container_of(*dsc, struct dcn20_dsc, base));1079	*dsc = NULL;1080}1081 1082 1083static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)1084{1085	unsigned int i;1086 1087	for (i = 0; i < pool->base.stream_enc_count; i++) {1088		if (pool->base.stream_enc[i] != NULL) {1089			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));1090			pool->base.stream_enc[i] = NULL;1091		}1092	}1093 1094	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1095		if (pool->base.dscs[i] != NULL)1096			dcn20_dsc_destroy(&pool->base.dscs[i]);1097	}1098 1099	if (pool->base.mpc != NULL) {1100		kfree(TO_DCN20_MPC(pool->base.mpc));1101		pool->base.mpc = NULL;1102	}1103	if (pool->base.hubbub != NULL) {1104		kfree(pool->base.hubbub);1105		pool->base.hubbub = NULL;1106	}1107	for (i = 0; i < pool->base.pipe_count; i++) {1108		if (pool->base.dpps[i] != NULL)1109			dcn20_dpp_destroy(&pool->base.dpps[i]);1110 1111		if (pool->base.ipps[i] != NULL)1112			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);1113 1114		if (pool->base.hubps[i] != NULL) {1115			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));1116			pool->base.hubps[i] = NULL;1117		}1118 1119		if (pool->base.irqs != NULL) {1120			dal_irq_service_destroy(&pool->base.irqs);1121		}1122	}1123 1124	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1125		if (pool->base.engines[i] != NULL)1126			dce110_engine_destroy(&pool->base.engines[i]);1127		if (pool->base.hw_i2cs[i] != NULL) {1128			kfree(pool->base.hw_i2cs[i]);1129			pool->base.hw_i2cs[i] = NULL;1130		}1131		if (pool->base.sw_i2cs[i] != NULL) {1132			kfree(pool->base.sw_i2cs[i]);1133			pool->base.sw_i2cs[i] = NULL;1134		}1135	}1136 1137	for (i = 0; i < pool->base.res_cap->num_opp; i++) {1138		if (pool->base.opps[i] != NULL)1139			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);1140	}1141 1142	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1143		if (pool->base.timing_generators[i] != NULL)	{1144			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));1145			pool->base.timing_generators[i] = NULL;1146		}1147	}1148 1149	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {1150		if (pool->base.dwbc[i] != NULL) {1151			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));1152			pool->base.dwbc[i] = NULL;1153		}1154		if (pool->base.mcif_wb[i] != NULL) {1155			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));1156			pool->base.mcif_wb[i] = NULL;1157		}1158	}1159 1160	for (i = 0; i < pool->base.audio_count; i++) {1161		if (pool->base.audios[i])1162			dce_aud_destroy(&pool->base.audios[i]);1163	}1164 1165	for (i = 0; i < pool->base.clk_src_count; i++) {1166		if (pool->base.clock_sources[i] != NULL) {1167			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);1168			pool->base.clock_sources[i] = NULL;1169		}1170	}1171 1172	if (pool->base.dp_clock_source != NULL) {1173		dcn20_clock_source_destroy(&pool->base.dp_clock_source);1174		pool->base.dp_clock_source = NULL;1175	}1176 1177 1178	if (pool->base.abm != NULL)1179		dce_abm_destroy(&pool->base.abm);1180 1181	if (pool->base.dmcu != NULL)1182		dce_dmcu_destroy(&pool->base.dmcu);1183 1184	if (pool->base.dccg != NULL)1185		dcn_dccg_destroy(&pool->base.dccg);1186 1187	if (pool->base.pp_smu != NULL)1188		dcn20_pp_smu_destroy(&pool->base.pp_smu);1189 1190	if (pool->base.oem_device != NULL) {1191		struct dc *dc = pool->base.oem_device->ctx->dc;1192 1193		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);1194	}1195}1196 1197struct hubp *dcn20_hubp_create(1198	struct dc_context *ctx,1199	uint32_t inst)1200{1201	struct dcn20_hubp *hubp2 =1202		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);1203 1204	if (!hubp2)1205		return NULL;1206 1207	if (hubp2_construct(hubp2, ctx, inst,1208			&hubp_regs[inst], &hubp_shift, &hubp_mask))1209		return &hubp2->base;1210 1211	BREAK_TO_DEBUGGER();1212	kfree(hubp2);1213	return NULL;1214}1215 1216static void get_pixel_clock_parameters(1217	struct pipe_ctx *pipe_ctx,1218	struct pixel_clk_params *pixel_clk_params)1219{1220	const struct dc_stream_state *stream = pipe_ctx->stream;1221	struct pipe_ctx *odm_pipe;1222	int opp_cnt = 1;1223	struct dc_link *link = stream->link;1224	struct link_encoder *link_enc = NULL;1225	struct dc *dc = pipe_ctx->stream->ctx->dc;1226	struct dce_hwseq *hws = dc->hwseq;1227 1228	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)1229		opp_cnt++;1230 1231	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;1232 1233	link_enc = link_enc_cfg_get_link_enc(link);1234	if (link_enc)1235		pixel_clk_params->encoder_object_id = link_enc->id;1236 1237	pixel_clk_params->signal_type = pipe_ctx->stream->signal;1238	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;1239	/* TODO: un-hardcode*/1240	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */1241	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *1242		LINK_RATE_REF_FREQ_IN_KHZ;1243	pixel_clk_params->flags.ENABLE_SS = 0;1244	pixel_clk_params->color_depth =1245		stream->timing.display_color_depth;1246	pixel_clk_params->flags.DISPLAY_BLANKED = 1;1247	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;1248 1249	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)1250		pixel_clk_params->color_depth = COLOR_DEPTH_888;1251 1252	if (opp_cnt == 4)1253		pixel_clk_params->requested_pix_clk_100hz /= 4;1254	else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)1255		pixel_clk_params->requested_pix_clk_100hz /= 2;1256	else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {1257		if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))1258			pixel_clk_params->requested_pix_clk_100hz /= 2;1259	}1260 1261	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)1262		pixel_clk_params->requested_pix_clk_100hz *= 2;1263 1264	if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&1265			pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||1266			(hws->funcs.is_dp_dig_pixel_rate_div_policy &&1267			hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||1268			opp_cnt > 1) {1269		pixel_clk_params->dio_se_pix_per_cycle = 2;1270	} else {1271		pixel_clk_params->dio_se_pix_per_cycle = 1;1272	}1273}1274 1275static void build_clamping_params(struct dc_stream_state *stream)1276{1277	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;1278	stream->clamping.c_depth = stream->timing.display_color_depth;1279	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;1280}1281 1282void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)1283{1284	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);1285	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(1286			pipe_ctx->clock_source,1287			&pipe_ctx->stream_res.pix_clk_params,1288			&pipe_ctx->pll_settings);1289}1290 1291static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)1292{1293	struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;1294 1295	if (pool->funcs->build_pipe_pix_clk_params) {1296		pool->funcs->build_pipe_pix_clk_params(pipe_ctx);1297	} else {1298		dcn20_build_pipe_pix_clk_params(pipe_ctx);1299	}1300 1301	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;1302 1303	resource_build_bit_depth_reduction_params(pipe_ctx->stream,1304					&pipe_ctx->stream->bit_depth_params);1305	build_clamping_params(pipe_ctx->stream);1306 1307	return DC_OK;1308}1309 1310enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)1311{1312	enum dc_status status = DC_OK;1313	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);1314 1315	if (!pipe_ctx)1316		return DC_ERROR_UNEXPECTED;1317 1318 1319	status = build_pipe_hw_param(pipe_ctx);1320 1321	return status;1322}1323 1324 1325void dcn20_acquire_dsc(const struct dc *dc,1326			struct resource_context *res_ctx,1327			struct display_stream_compressor **dsc,1328			int pipe_idx)1329{1330	int i;1331	const struct resource_pool *pool = dc->res_pool;1332	struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;1333 1334	ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */1335	*dsc = NULL;1336 1337	/* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */1338	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {1339		*dsc = pool->dscs[pipe_idx];1340		res_ctx->is_dsc_acquired[pipe_idx] = true;1341		return;1342	}1343 1344	/* Return old DSC to avoid the need for re-programming */1345	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {1346		*dsc = dsc_old;1347		res_ctx->is_dsc_acquired[dsc_old->inst] = true;1348		return ;1349	}1350 1351	/* Find first free DSC */1352	for (i = 0; i < pool->res_cap->num_dsc; i++)1353		if (!res_ctx->is_dsc_acquired[i]) {1354			*dsc = pool->dscs[i];1355			res_ctx->is_dsc_acquired[i] = true;1356			break;1357		}1358}1359 1360void dcn20_release_dsc(struct resource_context *res_ctx,1361			const struct resource_pool *pool,1362			struct display_stream_compressor **dsc)1363{1364	int i;1365 1366	for (i = 0; i < pool->res_cap->num_dsc; i++)1367		if (pool->dscs[i] == *dsc) {1368			res_ctx->is_dsc_acquired[i] = false;1369			*dsc = NULL;1370			break;1371		}1372}1373 1374 1375 1376enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,1377		struct dc_state *dc_ctx,1378		struct dc_stream_state *dc_stream)1379{1380	enum dc_status result = DC_OK;1381	int i;1382 1383	/* Get a DSC if required and available */1384	for (i = 0; i < dc->res_pool->pipe_count; i++) {1385		struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];1386 1387		if (pipe_ctx->top_pipe)1388			continue;1389 1390		if (pipe_ctx->stream != dc_stream)1391			continue;1392 1393		if (pipe_ctx->stream_res.dsc)1394			continue;1395 1396		dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);1397 1398		/* The number of DSCs can be less than the number of pipes */1399		if (!pipe_ctx->stream_res.dsc) {1400			result = DC_NO_DSC_RESOURCE;1401		}1402 1403		break;1404	}1405 1406	return result;1407}1408 1409 1410static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,1411		struct dc_state *new_ctx,1412		struct dc_stream_state *dc_stream)1413{1414	struct pipe_ctx *pipe_ctx = NULL;1415	int i;1416 1417	for (i = 0; i < MAX_PIPES; i++) {1418		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {1419			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];1420 1421			if (pipe_ctx->stream_res.dsc)1422				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);1423		}1424	}1425 1426	if (!pipe_ctx)1427		return DC_ERROR_UNEXPECTED;1428	else1429		return DC_OK;1430}1431 1432 1433enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)1434{1435	enum dc_status result = DC_ERROR_UNEXPECTED;1436 1437	result = resource_map_pool_resources(dc, new_ctx, dc_stream);1438 1439	if (result == DC_OK)1440		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);1441 1442	/* Get a DSC if required and available */1443	if (result == DC_OK && dc_stream->timing.flags.DSC)1444		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);1445 1446	if (result == DC_OK)1447		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);1448 1449	return result;1450}1451 1452 1453enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)1454{1455	enum dc_status result = DC_OK;1456 1457	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);1458 1459	return result;1460}1461 1462/**1463 * dcn20_split_stream_for_odm - Check if stream can be splited for ODM1464 *1465 * @dc: DC object with resource pool info required for pipe split1466 * @res_ctx: Persistent state of resources1467 * @prev_odm_pipe: Reference to the previous ODM pipe1468 * @next_odm_pipe: Reference to the next ODM pipe1469 *1470 * This function takes a logically active pipe and a logically free pipe and1471 * halves all the scaling parameters that need to be halved while populating1472 * the free pipe with the required resources and configuring the next/previous1473 * ODM pipe pointers.1474 *1475 * Return:1476 * Return true if split stream for ODM is possible, otherwise, return false.1477 */1478bool dcn20_split_stream_for_odm(1479		const struct dc *dc,1480		struct resource_context *res_ctx,1481		struct pipe_ctx *prev_odm_pipe,1482		struct pipe_ctx *next_odm_pipe)1483{1484	int pipe_idx = next_odm_pipe->pipe_idx;1485	const struct resource_pool *pool = dc->res_pool;1486 1487	*next_odm_pipe = *prev_odm_pipe;1488 1489	next_odm_pipe->pipe_idx = pipe_idx;1490	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];1491	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];1492	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];1493	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];1494	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];1495	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;1496	next_odm_pipe->stream_res.dsc = NULL;1497	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {1498		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;1499		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;1500	}1501	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {1502		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;1503		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;1504	}1505	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {1506		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;1507		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;1508	}1509	prev_odm_pipe->next_odm_pipe = next_odm_pipe;1510	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;1511 1512	if (prev_odm_pipe->plane_state) {1513		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;1514		int new_width;1515 1516		/* HACTIVE halved for odm combine */1517		sd->h_active /= 2;1518		/* Calculate new vp and recout for left pipe */1519		/* Need at least 16 pixels width per side */1520		if (sd->recout.x + 16 >= sd->h_active)1521			return false;1522		new_width = sd->h_active - sd->recout.x;1523		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(1524				sd->ratios.horz, sd->recout.width - new_width));1525		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(1526				sd->ratios.horz_c, sd->recout.width - new_width));1527		sd->recout.width = new_width;1528 1529		/* Calculate new vp and recout for right pipe */1530		sd = &next_odm_pipe->plane_res.scl_data;1531		/* HACTIVE halved for odm combine */1532		sd->h_active /= 2;1533		/* Need at least 16 pixels width per side */1534		if (new_width <= 16)1535			return false;1536		new_width = sd->recout.width + sd->recout.x - sd->h_active;1537		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(1538				sd->ratios.horz, sd->recout.width - new_width));1539		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(1540				sd->ratios.horz_c, sd->recout.width - new_width));1541		sd->recout.width = new_width;1542		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(1543				sd->ratios.horz, sd->h_active - sd->recout.x));1544		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(1545				sd->ratios.horz_c, sd->h_active - sd->recout.x));1546		sd->recout.x = 0;1547	}1548	if (!next_odm_pipe->top_pipe)1549		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];1550	else1551		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;1552	if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {1553		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);1554		ASSERT(next_odm_pipe->stream_res.dsc);1555		if (next_odm_pipe->stream_res.dsc == NULL)1556			return false;1557	}1558 1559	return true;1560}1561 1562void dcn20_split_stream_for_mpc(1563		struct resource_context *res_ctx,1564		const struct resource_pool *pool,1565		struct pipe_ctx *primary_pipe,1566		struct pipe_ctx *secondary_pipe)1567{1568	int pipe_idx = secondary_pipe->pipe_idx;1569	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;1570 1571	*secondary_pipe = *primary_pipe;1572	secondary_pipe->bottom_pipe = sec_bot_pipe;1573 1574	secondary_pipe->pipe_idx = pipe_idx;1575	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];1576	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];1577	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];1578	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];1579	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];1580	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;1581	secondary_pipe->stream_res.dsc = NULL;1582	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {1583		ASSERT(!secondary_pipe->bottom_pipe);1584		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;1585		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;1586	}1587	primary_pipe->bottom_pipe = secondary_pipe;1588	secondary_pipe->top_pipe = primary_pipe;1589 1590	ASSERT(primary_pipe->plane_state);1591}1592 1593unsigned int dcn20_calc_max_scaled_time(1594		unsigned int time_per_pixel,1595		enum mmhubbub_wbif_mode mode,1596		unsigned int urgent_watermark)1597{1598	unsigned int time_per_byte = 0;1599	unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */1600	unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */1601	unsigned int small_free_entry, max_free_entry;1602	unsigned int buf_lh_capability;1603	unsigned int max_scaled_time;1604 1605	if (mode == PACKED_444) /* packed mode */1606		time_per_byte = time_per_pixel/4;1607	else if (mode == PLANAR_420_8BPC)1608		time_per_byte  = time_per_pixel;1609	else if (mode == PLANAR_420_10BPC) /* p010 */1610		time_per_byte  = time_per_pixel * 819/1024;1611 1612	if (time_per_byte == 0)1613		time_per_byte = 1;1614 1615	small_free_entry  = total_c_free_entry;1616	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;1617	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */1618	max_scaled_time   = buf_lh_capability - urgent_watermark;1619	return max_scaled_time;1620}1621 1622void dcn20_set_mcif_arb_params(1623		struct dc *dc,1624		struct dc_state *context,1625		display_e2e_pipe_params_st *pipes,1626		int pipe_cnt)1627{1628	enum mmhubbub_wbif_mode wbif_mode;1629	struct mcif_arb_params *wb_arb_params;1630	int i, j, dwb_pipe;1631 1632	/* Writeback MCIF_WB arbitration parameters */1633	dwb_pipe = 0;1634	for (i = 0; i < dc->res_pool->pipe_count; i++) {1635 1636		if (!context->res_ctx.pipe_ctx[i].stream)1637			continue;1638 1639		for (j = 0; j < MAX_DWB_PIPES; j++) {1640			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)1641				continue;1642 1643			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;1644			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];1645 1646			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {1647				if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)1648					wbif_mode = PLANAR_420_8BPC;1649				else1650					wbif_mode = PLANAR_420_10BPC;1651			} else1652				wbif_mode = PACKED_444;1653 1654			DC_FP_START();1655			dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);1656			DC_FP_END();1657 1658			wb_arb_params->slice_lines = 32;1659			wb_arb_params->arbitration_slice = 2;1660			wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,1661				wbif_mode,1662				wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */1663 1664			dwb_pipe++;1665 1666			if (dwb_pipe >= MAX_DWB_PIPES)1667				return;1668		}1669	}1670}1671 1672bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)1673{1674	int i;1675 1676	/* Validate DSC config, dsc count validation is already done */1677	for (i = 0; i < dc->res_pool->pipe_count; i++) {1678		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];1679		struct dc_stream_state *stream = pipe_ctx->stream;1680		struct dsc_config dsc_cfg;1681		struct pipe_ctx *odm_pipe;1682		int opp_cnt = 1;1683 1684		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)1685			opp_cnt++;1686 1687		/* Only need to validate top pipe */1688		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)1689			continue;1690 1691		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left1692				+ stream->timing.h_border_right) / opp_cnt;1693		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top1694				+ stream->timing.v_border_bottom;1695		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;1696		dsc_cfg.color_depth = stream->timing.display_color_depth;1697		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;1698		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;1699		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;1700 1701		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))1702			return false;1703	}1704	return true;1705}1706 1707struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,1708		struct resource_context *res_ctx,1709		const struct resource_pool *pool,1710		const struct pipe_ctx *primary_pipe)1711{1712	struct pipe_ctx *secondary_pipe = NULL;1713 1714	if (dc && primary_pipe) {1715		int j;1716		int preferred_pipe_idx = 0;1717 1718		/* first check the prev dc state:1719		 * if this primary pipe has a bottom pipe in prev. state1720		 * and if the bottom pipe is still available (which it should be),1721		 * pick that pipe as secondary1722		 * Same logic applies for ODM pipes1723		 */1724		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {1725			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;1726			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {1727				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];1728				secondary_pipe->pipe_idx = preferred_pipe_idx;1729			}1730		}1731		if (secondary_pipe == NULL &&1732				dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {1733			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;1734			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {1735				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];1736				secondary_pipe->pipe_idx = preferred_pipe_idx;1737			}1738		}1739 1740		/*1741		 * if this primary pipe does not have a bottom pipe in prev. state1742		 * start backward and find a pipe that did not used to be a bottom pipe in1743		 * prev. dc state. This way we make sure we keep the same assignment as1744		 * last state and will not have to reprogram every pipe1745		 */1746		if (secondary_pipe == NULL) {1747			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {1748				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL1749						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {1750					preferred_pipe_idx = j;1751 1752					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {1753						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];1754						secondary_pipe->pipe_idx = preferred_pipe_idx;1755						break;1756					}1757				}1758			}1759		}1760		/*1761		 * We should never hit this assert unless assignments are shuffled around1762		 * if this happens we will prob. hit a vsync tdr1763		 */1764		ASSERT(secondary_pipe);1765		/*1766		 * search backwards for the second pipe to keep pipe1767		 * assignment more consistent1768		 */1769		if (secondary_pipe == NULL) {1770			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {1771				preferred_pipe_idx = j;1772 1773				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {1774					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];1775					secondary_pipe->pipe_idx = preferred_pipe_idx;1776					break;1777				}1778			}1779		}1780	}1781 1782	return secondary_pipe;1783}1784 1785void dcn20_merge_pipes_for_validate(1786		struct dc *dc,1787		struct dc_state *context)1788{1789	int i;1790 1791	/* merge previously split odm pipes since mode support needs to make the decision */1792	for (i = 0; i < dc->res_pool->pipe_count; i++) {1793		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1794		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;1795 1796		if (pipe->prev_odm_pipe)1797			continue;1798 1799		pipe->next_odm_pipe = NULL;1800		while (odm_pipe) {1801			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;1802 1803			odm_pipe->plane_state = NULL;1804			odm_pipe->stream = NULL;1805			odm_pipe->top_pipe = NULL;1806			odm_pipe->bottom_pipe = NULL;1807			odm_pipe->prev_odm_pipe = NULL;1808			odm_pipe->next_odm_pipe = NULL;1809			if (odm_pipe->stream_res.dsc)1810				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);1811			/* Clear plane_res and stream_res */1812			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));1813			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));1814			odm_pipe = next_odm_pipe;1815		}1816		if (pipe->plane_state)1817			resource_build_scaling_params(pipe);1818	}1819 1820	/* merge previously mpc split pipes since mode support needs to make the decision */1821	for (i = 0; i < dc->res_pool->pipe_count; i++) {1822		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1823		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;1824 1825		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)1826			continue;1827 1828		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;1829		if (hsplit_pipe->bottom_pipe)1830			hsplit_pipe->bottom_pipe->top_pipe = pipe;1831		hsplit_pipe->plane_state = NULL;1832		hsplit_pipe->stream = NULL;1833		hsplit_pipe->top_pipe = NULL;1834		hsplit_pipe->bottom_pipe = NULL;1835 1836		/* Clear plane_res and stream_res */1837		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));1838		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));1839		if (pipe->plane_state)1840			resource_build_scaling_params(pipe);1841	}1842}1843 1844int dcn20_validate_apply_pipe_split_flags(1845		struct dc *dc,1846		struct dc_state *context,1847		int vlevel,1848		int *split,1849		bool *merge)1850{1851	int i, pipe_idx, vlevel_split;1852	int plane_count = 0;1853	bool force_split = false;1854	bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;1855	struct vba_vars_st *v = &context->bw_ctx.dml.vba;1856	int max_mpc_comb = v->maxMpcComb;1857 1858	if (context->stream_count > 1) {1859		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)1860			avoid_split = true;1861	} else if (dc->debug.force_single_disp_pipe_split)1862			force_split = true;1863 1864	for (i = 0; i < dc->res_pool->pipe_count; i++) {1865		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1866 1867		/**1868		 * Workaround for avoiding pipe-split in cases where we'd split1869		 * planes that are too small, resulting in splits that aren't1870		 * valid for the scaler.1871		 */1872		if (pipe->plane_state &&1873		    (pipe->plane_state->dst_rect.width <= 16 ||1874		     pipe->plane_state->dst_rect.height <= 16 ||1875		     pipe->plane_state->src_rect.width <= 16 ||1876		     pipe->plane_state->src_rect.height <= 16))1877			avoid_split = true;1878 1879		/* TODO: fix dc bugs and remove this split threshold thing */1880		if (pipe->stream && !pipe->prev_odm_pipe &&1881				(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))1882			++plane_count;1883	}1884	if (plane_count > dc->res_pool->pipe_count / 2)1885		avoid_split = true;1886 1887	/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */1888	for (i = 0; i < dc->res_pool->pipe_count; i++) {1889		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1890		struct dc_crtc_timing timing;1891 1892		if (!pipe->stream)1893			continue;1894		else {1895			timing = pipe->stream->timing;1896			if (timing.h_border_left + timing.h_border_right1897					+ timing.v_border_top + timing.v_border_bottom > 0) {1898				avoid_split = true;1899				break;1900			}1901		}1902	}1903 1904	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */1905	if (avoid_split) {1906		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {1907			if (!context->res_ctx.pipe_ctx[i].stream)1908				continue;1909 1910			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)1911				if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&1912						v->ModeSupport[vlevel][0])1913					break;1914			/* Impossible to not split this pipe */1915			if (vlevel > context->bw_ctx.dml.soc.num_states)1916				vlevel = vlevel_split;1917			else1918				max_mpc_comb = 0;1919			pipe_idx++;1920		}1921		v->maxMpcComb = max_mpc_comb;1922	}1923 1924	/* Split loop sets which pipe should be split based on dml outputs and dc flags */1925	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {1926		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];1927		int pipe_plane = v->pipe_plane[pipe_idx];1928		bool split4mpc = context->stream_count == 1 && plane_count == 11929				&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;1930 1931		if (!context->res_ctx.pipe_ctx[i].stream)1932			continue;1933 1934		if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)1935			split[i] = 4;1936		else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)1937				split[i] = 2;1938 1939		if ((pipe->stream->view_format ==1940				VIEW_3D_FORMAT_SIDE_BY_SIDE ||1941				pipe->stream->view_format ==1942				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&1943				(pipe->stream->timing.timing_3d_format ==1944				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||1945				 pipe->stream->timing.timing_3d_format ==1946				TIMING_3D_FORMAT_SIDE_BY_SIDE))1947			split[i] = 2;1948		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {1949			split[i] = 2;1950			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;1951		}1952		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {1953			split[i] = 4;1954			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;1955		}1956		/*420 format workaround*/1957		if (pipe->stream->timing.h_addressable > 7680 &&1958				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {1959			split[i] = 4;1960		}1961		v->ODMCombineEnabled[pipe_plane] =1962			v->ODMCombineEnablePerState[vlevel][pipe_plane];1963 1964		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {1965			if (resource_get_mpc_slice_count(pipe) == 2) {1966				/*If need split for mpc but 2 way split already*/1967				if (split[i] == 4)1968					split[i] = 2; /* 2 -> 4 MPC */1969				else if (split[i] == 2)1970					split[i] = 0; /* 2 -> 2 MPC */1971				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)1972					merge[i] = true; /* 2 -> 1 MPC */1973			} else if (resource_get_mpc_slice_count(pipe) == 4) {1974				/*If need split for mpc but 4 way split already*/1975				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)1976						|| !pipe->bottom_pipe)) {1977					merge[i] = true; /* 4 -> 2 MPC */1978				} else if (split[i] == 0 && pipe->top_pipe &&1979						pipe->top_pipe->plane_state == pipe->plane_state)1980					merge[i] = true; /* 4 -> 1 MPC */1981				split[i] = 0;1982			} else if (resource_get_odm_slice_count(pipe) > 1) {1983				/* ODM -> MPC transition */1984				if (pipe->prev_odm_pipe) {1985					split[i] = 0;1986					merge[i] = true;1987				}1988			}1989		} else {1990			if (resource_get_odm_slice_count(pipe) == 2) {1991				/*If need split for odm but 2 way split already*/1992				if (split[i] == 4)1993					split[i] = 2; /* 2 -> 4 ODM */1994				else if (split[i] == 2)1995					split[i] = 0; /* 2 -> 2 ODM */1996				else if (pipe->prev_odm_pipe) {1997					ASSERT(0); /* NOT expected yet */1998					merge[i] = true; /* exit ODM */1999				}2000			} else if (resource_get_odm_slice_count(pipe) == 4) {2001				/*If need split for odm but 4 way split already*/2002				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)2003						|| !pipe->next_odm_pipe)) {2004					merge[i] = true; /* 4 -> 2 ODM */2005				} else if (split[i] == 0 && pipe->prev_odm_pipe) {2006					ASSERT(0); /* NOT expected yet */2007					merge[i] = true; /* exit ODM */2008				}2009				split[i] = 0;2010			} else if (resource_get_mpc_slice_count(pipe) > 1) {2011				/* MPC -> ODM transition */2012				ASSERT(0); /* NOT expected yet */2013				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {2014					split[i] = 0;2015					merge[i] = true;2016				}2017			}2018		}2019 2020		/* Adjust dppclk when split is forced, do not bother with dispclk */2021		if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {2022			DC_FP_START();2023			dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);2024			DC_FP_END();2025		}2026		pipe_idx++;2027	}2028 2029	return vlevel;2030}2031 2032bool dcn20_fast_validate_bw(2033		struct dc *dc,2034		struct dc_state *context,2035		display_e2e_pipe_params_st *pipes,2036		int *pipe_cnt_out,2037		int *pipe_split_from,2038		int *vlevel_out,2039		bool fast_validate)2040{2041	bool out = false;2042	int split[MAX_PIPES] = { 0 };2043	bool merge[MAX_PIPES] = { false };2044	int pipe_cnt, i, pipe_idx, vlevel;2045 2046	ASSERT(pipes);2047	if (!pipes)2048		return false;2049 2050	dcn20_merge_pipes_for_validate(dc, context);2051 2052	DC_FP_START();2053	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);2054	DC_FP_END();2055 2056	*pipe_cnt_out = pipe_cnt;2057 2058	if (!pipe_cnt) {2059		out = true;2060		goto validate_out;2061	}2062 2063	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);2064 2065	if (vlevel > context->bw_ctx.dml.soc.num_states)2066		goto validate_fail;2067 2068	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);2069 2070	/*initialize pipe_just_split_from to invalid idx*/2071	for (i = 0; i < MAX_PIPES; i++)2072		pipe_split_from[i] = -1;2073 2074	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {2075		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];2076		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;2077 2078		if (!pipe->stream || pipe_split_from[i] >= 0)2079			continue;2080 2081		pipe_idx++;2082 2083		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {2084			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);2085			ASSERT(hsplit_pipe);2086			if (!dcn20_split_stream_for_odm(2087					dc, &context->res_ctx,2088					pipe, hsplit_pipe))2089				goto validate_fail;2090			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;2091			dcn20_build_mapped_resource(dc, context, pipe->stream);2092		}2093 2094		if (!pipe->plane_state)2095			continue;2096		/* Skip 2nd half of already split pipe */2097		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)2098			continue;2099 2100		/* We do not support mpo + odm at the moment */2101		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state2102				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])2103			goto validate_fail;2104 2105		if (split[i] == 2) {2106			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {2107				/* pipe not split previously needs split */2108				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);2109				ASSERT(hsplit_pipe);2110				if (!hsplit_pipe) {2111					DC_FP_START();2112					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);2113					DC_FP_END();2114					continue;2115				}2116				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {2117					if (!dcn20_split_stream_for_odm(2118							dc, &context->res_ctx,2119							pipe, hsplit_pipe))2120						goto validate_fail;2121					dcn20_build_mapped_resource(dc, context, pipe->stream);2122				} else {2123					dcn20_split_stream_for_mpc(2124							&context->res_ctx, dc->res_pool,2125							pipe, hsplit_pipe);2126					resource_build_scaling_params(pipe);2127					resource_build_scaling_params(hsplit_pipe);2128				}2129				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;2130			}2131		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {2132			/* merge should already have been done */2133			ASSERT(0);2134		}2135	}2136	/* Actual dsc count per stream dsc validation*/2137	if (!dcn20_validate_dsc(dc, context)) {2138		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =2139				DML_FAIL_DSC_VALIDATION_FAILURE;2140		goto validate_fail;2141	}2142 2143	*vlevel_out = vlevel;2144 2145	out = true;2146	goto validate_out;2147 2148validate_fail:2149	out = false;2150 2151validate_out:2152	return out;2153}2154 2155bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,2156		bool fast_validate)2157{2158	bool voltage_supported;2159	display_e2e_pipe_params_st *pipes;2160 2161	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);2162	if (!pipes)2163		return false;2164 2165	DC_FP_START();2166	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);2167	DC_FP_END();2168 2169	kfree(pipes);2170	return voltage_supported;2171}2172 2173struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(2174		const struct dc_state *cur_ctx,2175		struct dc_state *new_ctx,2176		const struct resource_pool *pool,2177		const struct pipe_ctx *opp_head)2178{2179	struct resource_context *res_ctx = &new_ctx->res_ctx;2180	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);2181	struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);2182 2183	ASSERT(otg_master);2184 2185	if (!sec_dpp_pipe)2186		return NULL;2187 2188	sec_dpp_pipe->stream = opp_head->stream;2189	sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg;2190	sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;2191 2192	sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];2193	sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];2194	sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];2195	sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;2196 2197	return sec_dpp_pipe;2198}2199 2200bool dcn20_get_dcc_compression_cap(const struct dc *dc,2201		const struct dc_dcc_surface_param *input,2202		struct dc_surface_dcc_cap *output)2203{2204	if (dc->res_pool->hubbub->funcs->get_dcc_compression_cap)2205		return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(2206			dc->res_pool->hubbub, input, output);2207 2208	return false;2209}2210 2211static void dcn20_destroy_resource_pool(struct resource_pool **pool)2212{2213	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);2214 2215	dcn20_resource_destruct(dcn20_pool);2216	kfree(dcn20_pool);2217	*pool = NULL;2218}2219 2220 2221static struct dc_cap_funcs cap_funcs = {2222	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap2223};2224 2225 2226enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)2227{2228	enum surface_pixel_format surf_pix_format = plane_state->format;2229	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);2230 2231	plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;2232	if (bpp == 64)2233		plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;2234 2235	return DC_OK;2236}2237 2238void dcn20_release_pipe(struct dc_state *context,2239			struct pipe_ctx *pipe,2240			const struct resource_pool *pool)2241{2242	if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)2243		dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);2244	memset(pipe, 0, sizeof(*pipe));2245}2246 2247static const struct resource_funcs dcn20_res_pool_funcs = {2248	.destroy = dcn20_destroy_resource_pool,2249	.link_enc_create = dcn20_link_encoder_create,2250	.panel_cntl_create = dcn20_panel_cntl_create,2251	.validate_bandwidth = dcn20_validate_bandwidth,2252	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,2253	.release_pipe = dcn20_release_pipe,2254	.add_stream_to_ctx = dcn20_add_stream_to_ctx,2255	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,2256	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,2257	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,2258	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,2259	.set_mcif_arb_params = dcn20_set_mcif_arb_params,2260	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,2261	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link2262};2263 2264bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)2265{2266	int i;2267	uint32_t pipe_count = pool->res_cap->num_dwb;2268 2269	for (i = 0; i < pipe_count; i++) {2270		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),2271						    GFP_KERNEL);2272 2273		if (!dwbc20) {2274			dm_error("DC: failed to create dwbc20!\n");2275			return false;2276		}2277		dcn20_dwbc_construct(dwbc20, ctx,2278				&dwbc20_regs[i],2279				&dwbc20_shift,2280				&dwbc20_mask,2281				i);2282		pool->dwbc[i] = &dwbc20->base;2283	}2284	return true;2285}2286 2287bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)2288{2289	int i;2290	uint32_t pipe_count = pool->res_cap->num_dwb;2291 2292	ASSERT(pipe_count > 0);2293 2294	for (i = 0; i < pipe_count; i++) {2295		struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),2296						    GFP_KERNEL);2297 2298		if (!mcif_wb20) {2299			dm_error("DC: failed to create mcif_wb20!\n");2300			return false;2301		}2302 2303		dcn20_mmhubbub_construct(mcif_wb20, ctx,2304				&mcif_wb20_regs[i],2305				&mcif_wb20_shift,2306				&mcif_wb20_mask,2307				i);2308 2309		pool->mcif_wb[i] = &mcif_wb20->base;2310	}2311	return true;2312}2313 2314static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)2315{2316	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);2317 2318	if (!pp_smu)2319		return pp_smu;2320 2321	dm_pp_get_funcs(ctx, pp_smu);2322 2323	if (pp_smu->ctx.ver != PP_SMU_VER_NV)2324		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));2325 2326	return pp_smu;2327}2328 2329static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)2330{2331	if (pp_smu && *pp_smu) {2332		kfree(*pp_smu);2333		*pp_smu = NULL;2334	}2335}2336 2337static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(2338	uint32_t hw_internal_rev)2339{2340	if (ASICREV_IS_NAVI14_M(hw_internal_rev))2341		return &dcn2_0_nv14_soc;2342 2343	if (ASICREV_IS_NAVI12_P(hw_internal_rev))2344		return &dcn2_0_nv12_soc;2345 2346	return &dcn2_0_soc;2347}2348 2349static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(2350	uint32_t hw_internal_rev)2351{2352	if (ASICREV_IS_NAVI14_M(hw_internal_rev))2353		return &dcn2_0_nv14_ip;2354 2355	/* NV12 and NV10 */2356	return &dcn2_0_ip;2357}2358 2359static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)2360{2361	return DML_PROJECT_NAVI10v2;2362}2363 2364static bool init_soc_bounding_box(struct dc *dc,2365				  struct dcn20_resource_pool *pool)2366{2367	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =2368			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);2369	struct _vcs_dpi_ip_params_st *loaded_ip =2370			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);2371 2372	DC_LOGGER_INIT(dc->ctx->logger);2373 2374	if (pool->base.pp_smu) {2375		struct pp_smu_nv_clock_table max_clocks = {0};2376		unsigned int uclk_states[8] = {0};2377		unsigned int num_states = 0;2378		enum pp_smu_status status;2379		bool clock_limits_available = false;2380		bool uclk_states_available = false;2381 2382		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {2383			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)2384				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);2385 2386			uclk_states_available = (status == PP_SMU_RESULT_OK);2387		}2388 2389		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {2390			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)2391					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);2392			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock2393			 */2394			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)2395				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;2396			clock_limits_available = (status == PP_SMU_RESULT_OK);2397		}2398 2399		if (clock_limits_available && uclk_states_available && num_states) {2400			DC_FP_START();2401			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);2402			DC_FP_END();2403		} else if (clock_limits_available) {2404			DC_FP_START();2405			dcn20_cap_soc_clocks(loaded_bb, max_clocks);2406			DC_FP_END();2407		}2408	}2409 2410	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;2411	loaded_ip->max_num_dpp = pool->base.pipe_count;2412	DC_FP_START();2413	dcn20_patch_bounding_box(dc, loaded_bb);2414	DC_FP_END();2415	return true;2416}2417 2418static bool dcn20_resource_construct(2419	uint8_t num_virtual_links,2420	struct dc *dc,2421	struct dcn20_resource_pool *pool)2422{2423	int i;2424	struct dc_context *ctx = dc->ctx;2425	struct irq_service_init_data init_data;2426	struct ddc_service_init_data ddc_init_data = {0};2427	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =2428			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);2429	struct _vcs_dpi_ip_params_st *loaded_ip =2430			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);2431	enum dml_project dml_project_version =2432			get_dml_project_version(ctx->asic_id.hw_internal_rev);2433 2434	ctx->dc_bios->regs = &bios_regs;2435	pool->base.funcs = &dcn20_res_pool_funcs;2436 2437	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {2438		pool->base.res_cap = &res_cap_nv14;2439		pool->base.pipe_count = 5;2440		pool->base.mpcc_count = 5;2441	} else {2442		pool->base.res_cap = &res_cap_nv10;2443		pool->base.pipe_count = 6;2444		pool->base.mpcc_count = 6;2445	}2446	/*************************************************2447	 *  Resource + asic cap harcoding                *2448	 *************************************************/2449	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;2450 2451	dc->caps.max_downscale_ratio = 200;2452	dc->caps.i2c_speed_in_khz = 100;2453	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/2454	dc->caps.max_cursor_size = 256;2455	dc->caps.min_horizontal_blanking_period = 80;2456	dc->caps.dmdata_alloc_size = 2048;2457 2458	dc->caps.max_slave_planes = 1;2459	dc->caps.max_slave_yuv_planes = 1;2460	dc->caps.max_slave_rgb_planes = 1;2461	dc->caps.post_blend_color_processing = true;2462	dc->caps.force_dp_tps4_for_cp2520 = true;2463	dc->caps.extended_aux_timeout_support = true;2464	dc->caps.dmcub_support = true;2465 2466	/* Color pipeline capabilities */2467	dc->caps.color.dpp.dcn_arch = 1;2468	dc->caps.color.dpp.input_lut_shared = 0;2469	dc->caps.color.dpp.icsc = 1;2470	dc->caps.color.dpp.dgam_ram = 1;2471	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;2472	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;2473	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;2474	dc->caps.color.dpp.dgam_rom_caps.pq = 0;2475	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;2476	dc->caps.color.dpp.post_csc = 0;2477	dc->caps.color.dpp.gamma_corr = 0;2478	dc->caps.color.dpp.dgam_rom_for_yuv = 1;2479 2480	dc->caps.color.dpp.hw_3d_lut = 1;2481	dc->caps.color.dpp.ogam_ram = 1;2482	// no OGAM ROM on DCN2, only MPC ROM2483	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;2484	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;2485	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;2486	dc->caps.color.dpp.ogam_rom_caps.pq = 0;2487	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;2488	dc->caps.color.dpp.ocsc = 0;2489 2490	dc->caps.color.mpc.gamut_remap = 0;2491	dc->caps.color.mpc.num_3dluts = 0;2492	dc->caps.color.mpc.shared_3d_lut = 0;2493	dc->caps.color.mpc.ogam_ram = 1;2494	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;2495	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;2496	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;2497	dc->caps.color.mpc.ogam_rom_caps.pq = 0;2498	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;2499	dc->caps.color.mpc.ocsc = 1;2500 2501	dc->caps.dp_hdmi21_pcon_support = true;2502 2503	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)2504		dc->debug = debug_defaults_drv;2505 2506	//dcn2.0x2507	dc->work_arounds.dedcn20_305_wa = true;2508 2509	// Init the vm_helper2510	if (dc->vm_helper)2511		vm_helper_init(dc->vm_helper, 16);2512 2513	/*************************************************2514	 *  Create resources                             *2515	 *************************************************/2516 2517	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =2518			dcn20_clock_source_create(ctx, ctx->dc_bios,2519				CLOCK_SOURCE_COMBO_PHY_PLL0,2520				&clk_src_regs[0], false);2521	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =2522			dcn20_clock_source_create(ctx, ctx->dc_bios,2523				CLOCK_SOURCE_COMBO_PHY_PLL1,2524				&clk_src_regs[1], false);2525	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =2526			dcn20_clock_source_create(ctx, ctx->dc_bios,2527				CLOCK_SOURCE_COMBO_PHY_PLL2,2528				&clk_src_regs[2], false);2529	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =2530			dcn20_clock_source_create(ctx, ctx->dc_bios,2531				CLOCK_SOURCE_COMBO_PHY_PLL3,2532				&clk_src_regs[3], false);2533	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =2534			dcn20_clock_source_create(ctx, ctx->dc_bios,2535				CLOCK_SOURCE_COMBO_PHY_PLL4,2536				&clk_src_regs[4], false);2537	pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =2538			dcn20_clock_source_create(ctx, ctx->dc_bios,2539				CLOCK_SOURCE_COMBO_PHY_PLL5,2540				&clk_src_regs[5], false);2541	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;2542	/* todo: not reuse phy_pll registers */2543	pool->base.dp_clock_source =2544			dcn20_clock_source_create(ctx, ctx->dc_bios,2545				CLOCK_SOURCE_ID_DP_DTO,2546				&clk_src_regs[0], true);2547 2548	for (i = 0; i < pool->base.clk_src_count; i++) {2549		if (pool->base.clock_sources[i] == NULL) {2550			dm_error("DC: failed to create clock sources!\n");2551			BREAK_TO_DEBUGGER();2552			goto create_fail;2553		}2554	}2555 2556	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);2557	if (pool->base.dccg == NULL) {2558		dm_error("DC: failed to create dccg!\n");2559		BREAK_TO_DEBUGGER();2560		goto create_fail;2561	}2562 2563	pool->base.dmcu = dcn20_dmcu_create(ctx,2564			&dmcu_regs,2565			&dmcu_shift,2566			&dmcu_mask);2567	if (pool->base.dmcu == NULL) {2568		dm_error("DC: failed to create dmcu!\n");2569		BREAK_TO_DEBUGGER();2570		goto create_fail;2571	}2572 2573	pool->base.abm = dce_abm_create(ctx,2574			&abm_regs,2575			&abm_shift,2576			&abm_mask);2577	if (pool->base.abm == NULL) {2578		dm_error("DC: failed to create abm!\n");2579		BREAK_TO_DEBUGGER();2580		goto create_fail;2581	}2582 2583	pool->base.pp_smu = dcn20_pp_smu_create(ctx);2584 2585 2586	if (!init_soc_bounding_box(dc, pool)) {2587		dm_error("DC: failed to initialize soc bounding box!\n");2588		BREAK_TO_DEBUGGER();2589		goto create_fail;2590	}2591 2592	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);2593 2594	if (!dc->debug.disable_pplib_wm_range) {2595		struct pp_smu_wm_range_sets ranges = {0};2596		int i = 0;2597 2598		ranges.num_reader_wm_sets = 0;2599 2600		if (loaded_bb->num_states == 1) {2601			ranges.reader_wm_sets[0].wm_inst = i;2602			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2603			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2604			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2605			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2606 2607			ranges.num_reader_wm_sets = 1;2608		} else if (loaded_bb->num_states > 1) {2609			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {2610				ranges.reader_wm_sets[i].wm_inst = i;2611				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2612				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2613				DC_FP_START();2614				dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);2615				DC_FP_END();2616 2617				ranges.num_reader_wm_sets = i + 1;2618			}2619 2620			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2621			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2622		}2623 2624		ranges.num_writer_wm_sets = 1;2625 2626		ranges.writer_wm_sets[0].wm_inst = 0;2627		ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2628		ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2629		ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;2630		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;2631 2632		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */2633		if (pool->base.pp_smu && pool->base.pp_smu->nv_funcs.set_wm_ranges)2634			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);2635	}2636 2637	init_data.ctx = dc->ctx;2638	pool->base.irqs = dal_irq_service_dcn20_create(&init_data);2639	if (!pool->base.irqs)2640		goto create_fail;2641 2642	/* mem input -> ipp -> dpp -> opp -> TG */2643	for (i = 0; i < pool->base.pipe_count; i++) {2644		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);2645		if (pool->base.hubps[i] == NULL) {2646			BREAK_TO_DEBUGGER();2647			dm_error(2648				"DC: failed to create memory input!\n");2649			goto create_fail;2650		}2651 2652		pool->base.ipps[i] = dcn20_ipp_create(ctx, i);2653		if (pool->base.ipps[i] == NULL) {2654			BREAK_TO_DEBUGGER();2655			dm_error(2656				"DC: failed to create input pixel processor!\n");2657			goto create_fail;2658		}2659 2660		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);2661		if (pool->base.dpps[i] == NULL) {2662			BREAK_TO_DEBUGGER();2663			dm_error(2664				"DC: failed to create dpps!\n");2665			goto create_fail;2666		}2667	}2668	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {2669		pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);2670		if (pool->base.engines[i] == NULL) {2671			BREAK_TO_DEBUGGER();2672			dm_error(2673				"DC:failed to create aux engine!!\n");2674			goto create_fail;2675		}2676		pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);2677		if (pool->base.hw_i2cs[i] == NULL) {2678			BREAK_TO_DEBUGGER();2679			dm_error(2680				"DC:failed to create hw i2c!!\n");2681			goto create_fail;2682		}2683		pool->base.sw_i2cs[i] = NULL;2684	}2685 2686	for (i = 0; i < pool->base.res_cap->num_opp; i++) {2687		pool->base.opps[i] = dcn20_opp_create(ctx, i);2688		if (pool->base.opps[i] == NULL) {2689			BREAK_TO_DEBUGGER();2690			dm_error(2691				"DC: failed to create output pixel processor!\n");2692			goto create_fail;2693		}2694	}2695 2696	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2697		pool->base.timing_generators[i] = dcn20_timing_generator_create(2698				ctx, i);2699		if (pool->base.timing_generators[i] == NULL) {2700			BREAK_TO_DEBUGGER();2701			dm_error("DC: failed to create tg!\n");2702			goto create_fail;2703		}2704	}2705 2706	pool->base.timing_generator_count = i;2707 2708	pool->base.mpc = dcn20_mpc_create(ctx);2709	if (pool->base.mpc == NULL) {2710		BREAK_TO_DEBUGGER();2711		dm_error("DC: failed to create mpc!\n");2712		goto create_fail;2713	}2714 2715	pool->base.hubbub = dcn20_hubbub_create(ctx);2716	if (pool->base.hubbub == NULL) {2717		BREAK_TO_DEBUGGER();2718		dm_error("DC: failed to create hubbub!\n");2719		goto create_fail;2720	}2721 2722	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {2723		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);2724		if (pool->base.dscs[i] == NULL) {2725			BREAK_TO_DEBUGGER();2726			dm_error("DC: failed to create display stream compressor %d!\n", i);2727			goto create_fail;2728		}2729	}2730 2731	if (!dcn20_dwbc_create(ctx, &pool->base)) {2732		BREAK_TO_DEBUGGER();2733		dm_error("DC: failed to create dwbc!\n");2734		goto create_fail;2735	}2736	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {2737		BREAK_TO_DEBUGGER();2738		dm_error("DC: failed to create mcif_wb!\n");2739		goto create_fail;2740	}2741 2742	if (!resource_construct(num_virtual_links, dc, &pool->base,2743			&res_create_funcs))2744		goto create_fail;2745 2746	dcn20_hw_sequencer_construct(dc);2747 2748	// IF NV12, set PG function pointer to NULL. It's not that2749	// PG isn't supported for NV12, it's that we don't want to2750	// program the registers because that will cause more power2751	// to be consumed. We could have created dcn20_init_hw to get2752	// the same effect by checking ASIC rev, but there was a2753	// request at some point to not check ASIC rev on hw sequencer.2754	if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {2755		dc->hwseq->funcs.enable_power_gating_plane = NULL;2756		dc->debug.disable_dpp_power_gate = true;2757		dc->debug.disable_hubp_power_gate = true;2758	}2759 2760 2761	dc->caps.max_planes =  pool->base.pipe_count;2762 2763	for (i = 0; i < dc->caps.max_planes; ++i)2764		dc->caps.planes[i] = plane_cap;2765 2766	dc->cap_funcs = cap_funcs;2767 2768	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {2769		ddc_init_data.ctx = dc->ctx;2770		ddc_init_data.link = NULL;2771		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;2772		ddc_init_data.id.enum_id = 0;2773		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;2774		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);2775	} else {2776		pool->base.oem_device = NULL;2777	}2778 2779	return true;2780 2781create_fail:2782 2783	dcn20_resource_destruct(pool);2784 2785	return false;2786}2787 2788struct resource_pool *dcn20_create_resource_pool(2789		const struct dc_init_data *init_data,2790		struct dc *dc)2791{2792	struct dcn20_resource_pool *pool =2793		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);2794 2795	if (!pool)2796		return NULL;2797 2798	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))2799		return &pool->base;2800 2801	BREAK_TO_DEBUGGER();2802	kfree(pool);2803	return NULL;2804}2805