1715 lines · c
1/*2* Copyright 2018 Advanced Micro Devices, Inc.3 * Copyright 2019 Raptor Engineering, LLC4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include <linux/slab.h>28 29#include "dm_services.h"30#include "dc.h"31 32#include "dcn21/dcn21_init.h"33 34#include "resource.h"35#include "include/irq_service_interface.h"36#include "dcn20/dcn20_resource.h"37#include "dcn21/dcn21_resource.h"38 39#include "dml/dcn20/dcn20_fpu.h"40 41#include "clk_mgr.h"42#include "dcn10/dcn10_hubp.h"43#include "dcn10/dcn10_ipp.h"44#include "dcn20/dcn20_hubbub.h"45#include "dcn20/dcn20_mpc.h"46#include "dcn20/dcn20_hubp.h"47#include "dcn21/dcn21_hubp.h"48#include "irq/dcn21/irq_service_dcn21.h"49#include "dcn20/dcn20_dpp.h"50#include "dcn20/dcn20_optc.h"51#include "dcn21/dcn21_hwseq.h"52#include "dce110/dce110_hwseq.h"53#include "dcn20/dcn20_opp.h"54#include "dcn20/dcn20_dsc.h"55#include "dcn21/dcn21_link_encoder.h"56#include "dcn20/dcn20_stream_encoder.h"57#include "dce/dce_clock_source.h"58#include "dce/dce_audio.h"59#include "dce/dce_hwseq.h"60#include "virtual/virtual_stream_encoder.h"61#include "dml/display_mode_vba.h"62#include "dcn20/dcn20_dccg.h"63#include "dcn21/dcn21_dccg.h"64#include "dcn21/dcn21_hubbub.h"65#include "dcn10/dcn10_resource.h"66#include "dce/dce_panel_cntl.h"67 68#include "dcn20/dcn20_dwb.h"69#include "dcn20/dcn20_mmhubbub.h"70#include "dpcs/dpcs_2_1_0_offset.h"71#include "dpcs/dpcs_2_1_0_sh_mask.h"72 73#include "renoir_ip_offset.h"74#include "dcn/dcn_2_1_0_offset.h"75#include "dcn/dcn_2_1_0_sh_mask.h"76 77#include "nbio/nbio_7_0_offset.h"78 79#include "mmhub/mmhub_2_0_0_offset.h"80#include "mmhub/mmhub_2_0_0_sh_mask.h"81 82#include "reg_helper.h"83#include "dce/dce_abm.h"84#include "dce/dce_dmcu.h"85#include "dce/dce_aux.h"86#include "dce/dce_i2c.h"87#include "dcn21_resource.h"88#include "vm_helper.h"89#include "dcn20/dcn20_vmid.h"90#include "dce/dmub_psr.h"91#include "dce/dmub_abm.h"92 93/* begin *********************94 * macros to expend register list macro defined in HW object header file */95 96/* DCN */97#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg98 99#define BASE(seg) BASE_INNER(seg)100 101#define SR(reg_name)\102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \103 mm ## reg_name104 105#define SRI(reg_name, block, id)\106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \107 mm ## block ## id ## _ ## reg_name108 109#define SRIR(var_name, reg_name, block, id)\110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \111 mm ## block ## id ## _ ## reg_name112 113#define SRII(reg_name, block, id)\114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \115 mm ## block ## id ## _ ## reg_name116 117#define DCCG_SRII(reg_name, block, id)\118 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \119 mm ## block ## id ## _ ## reg_name120 121#define VUPDATE_SRII(reg_name, block, id)\122 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \123 mm ## reg_name ## _ ## block ## id124 125/* NBIO */126#define NBIO_BASE_INNER(seg) \127 NBIF0_BASE__INST0_SEG ## seg128 129#define NBIO_BASE(seg) \130 NBIO_BASE_INNER(seg)131 132#define NBIO_SR(reg_name)\133 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \134 mm ## reg_name135 136/* MMHUB */137#define MMHUB_BASE_INNER(seg) \138 MMHUB_BASE__INST0_SEG ## seg139 140#define MMHUB_BASE(seg) \141 MMHUB_BASE_INNER(seg)142 143#define MMHUB_SR(reg_name)\144 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \145 mmMM ## reg_name146 147#define clk_src_regs(index, pllid)\148[index] = {\149 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\150}151 152static const struct dce110_clk_src_regs clk_src_regs[] = {153 clk_src_regs(0, A),154 clk_src_regs(1, B),155 clk_src_regs(2, C),156 clk_src_regs(3, D),157 clk_src_regs(4, E),158};159 160static const struct dce110_clk_src_shift cs_shift = {161 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)162};163 164static const struct dce110_clk_src_mask cs_mask = {165 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)166};167 168static const struct bios_registers bios_regs = {169 NBIO_SR(BIOS_SCRATCH_3),170 NBIO_SR(BIOS_SCRATCH_6)171};172 173static const struct dce_dmcu_registers dmcu_regs = {174 DMCU_DCN20_REG_LIST()175};176 177static const struct dce_dmcu_shift dmcu_shift = {178 DMCU_MASK_SH_LIST_DCN10(__SHIFT)179};180 181static const struct dce_dmcu_mask dmcu_mask = {182 DMCU_MASK_SH_LIST_DCN10(_MASK)183};184 185static const struct dce_abm_registers abm_regs = {186 ABM_DCN20_REG_LIST()187};188 189static const struct dce_abm_shift abm_shift = {190 ABM_MASK_SH_LIST_DCN20(__SHIFT)191};192 193static const struct dce_abm_mask abm_mask = {194 ABM_MASK_SH_LIST_DCN20(_MASK)195};196 197#define audio_regs(id)\198[id] = {\199 AUD_COMMON_REG_LIST(id)\200}201 202static const struct dce_audio_registers audio_regs[] = {203 audio_regs(0),204 audio_regs(1),205 audio_regs(2),206 audio_regs(3),207 audio_regs(4),208 audio_regs(5),209};210 211#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\212 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\214 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)215 216static const struct dce_audio_shift audio_shift = {217 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)218};219 220static const struct dce_audio_mask audio_mask = {221 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)222};223 224static const struct dccg_registers dccg_regs = {225 DCCG_COMMON_REG_LIST_DCN_BASE()226};227 228static const struct dccg_shift dccg_shift = {229 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)230};231 232static const struct dccg_mask dccg_mask = {233 DCCG_MASK_SH_LIST_DCN2_1(_MASK)234};235 236#define opp_regs(id)\237[id] = {\238 OPP_REG_LIST_DCN20(id),\239}240 241static const struct dcn20_opp_registers opp_regs[] = {242 opp_regs(0),243 opp_regs(1),244 opp_regs(2),245 opp_regs(3),246 opp_regs(4),247 opp_regs(5),248};249 250static const struct dcn20_opp_shift opp_shift = {251 OPP_MASK_SH_LIST_DCN20(__SHIFT)252};253 254static const struct dcn20_opp_mask opp_mask = {255 OPP_MASK_SH_LIST_DCN20(_MASK)256};257 258#define tg_regs(id)\259[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}260 261static const struct dcn_optc_registers tg_regs[] = {262 tg_regs(0),263 tg_regs(1),264 tg_regs(2),265 tg_regs(3)266};267 268static const struct dcn_optc_shift tg_shift = {269 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)270};271 272static const struct dcn_optc_mask tg_mask = {273 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)274};275 276static const struct dcn20_mpc_registers mpc_regs = {277 MPC_REG_LIST_DCN2_0(0),278 MPC_REG_LIST_DCN2_0(1),279 MPC_REG_LIST_DCN2_0(2),280 MPC_REG_LIST_DCN2_0(3),281 MPC_REG_LIST_DCN2_0(4),282 MPC_REG_LIST_DCN2_0(5),283 MPC_OUT_MUX_REG_LIST_DCN2_0(0),284 MPC_OUT_MUX_REG_LIST_DCN2_0(1),285 MPC_OUT_MUX_REG_LIST_DCN2_0(2),286 MPC_OUT_MUX_REG_LIST_DCN2_0(3),287 MPC_DBG_REG_LIST_DCN2_0()288};289 290static const struct dcn20_mpc_shift mpc_shift = {291 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),292 MPC_DEBUG_REG_LIST_SH_DCN20293};294 295static const struct dcn20_mpc_mask mpc_mask = {296 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),297 MPC_DEBUG_REG_LIST_MASK_DCN20298};299 300#define hubp_regs(id)\301[id] = {\302 HUBP_REG_LIST_DCN21(id)\303}304 305static const struct dcn_hubp2_registers hubp_regs[] = {306 hubp_regs(0),307 hubp_regs(1),308 hubp_regs(2),309 hubp_regs(3)310};311 312static const struct dcn_hubp2_shift hubp_shift = {313 HUBP_MASK_SH_LIST_DCN21(__SHIFT)314};315 316static const struct dcn_hubp2_mask hubp_mask = {317 HUBP_MASK_SH_LIST_DCN21(_MASK)318};319 320static const struct dcn_hubbub_registers hubbub_reg = {321 HUBBUB_REG_LIST_DCN21()322};323 324static const struct dcn_hubbub_shift hubbub_shift = {325 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)326};327 328static const struct dcn_hubbub_mask hubbub_mask = {329 HUBBUB_MASK_SH_LIST_DCN21(_MASK)330};331 332 333#define vmid_regs(id)\334[id] = {\335 DCN20_VMID_REG_LIST(id)\336}337 338static const struct dcn_vmid_registers vmid_regs[] = {339 vmid_regs(0),340 vmid_regs(1),341 vmid_regs(2),342 vmid_regs(3),343 vmid_regs(4),344 vmid_regs(5),345 vmid_regs(6),346 vmid_regs(7),347 vmid_regs(8),348 vmid_regs(9),349 vmid_regs(10),350 vmid_regs(11),351 vmid_regs(12),352 vmid_regs(13),353 vmid_regs(14),354 vmid_regs(15)355};356 357static const struct dcn20_vmid_shift vmid_shifts = {358 DCN20_VMID_MASK_SH_LIST(__SHIFT)359};360 361static const struct dcn20_vmid_mask vmid_masks = {362 DCN20_VMID_MASK_SH_LIST(_MASK)363};364 365#define dsc_regsDCN20(id)\366[id] = {\367 DSC_REG_LIST_DCN20(id)\368}369 370static const struct dcn20_dsc_registers dsc_regs[] = {371 dsc_regsDCN20(0),372 dsc_regsDCN20(1),373 dsc_regsDCN20(2),374 dsc_regsDCN20(3),375 dsc_regsDCN20(4),376 dsc_regsDCN20(5)377};378 379static const struct dcn20_dsc_shift dsc_shift = {380 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)381};382 383static const struct dcn20_dsc_mask dsc_mask = {384 DSC_REG_LIST_SH_MASK_DCN20(_MASK)385};386 387#define ipp_regs(id)\388[id] = {\389 IPP_REG_LIST_DCN20(id),\390}391 392static const struct dcn10_ipp_registers ipp_regs[] = {393 ipp_regs(0),394 ipp_regs(1),395 ipp_regs(2),396 ipp_regs(3),397};398 399static const struct dcn10_ipp_shift ipp_shift = {400 IPP_MASK_SH_LIST_DCN20(__SHIFT)401};402 403static const struct dcn10_ipp_mask ipp_mask = {404 IPP_MASK_SH_LIST_DCN20(_MASK),405};406 407#define opp_regs(id)\408[id] = {\409 OPP_REG_LIST_DCN20(id),\410}411 412 413#define aux_engine_regs(id)\414[id] = {\415 AUX_COMMON_REG_LIST0(id), \416 .AUXN_IMPCAL = 0, \417 .AUXP_IMPCAL = 0, \418 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \419}420 421static const struct dce110_aux_registers aux_engine_regs[] = {422 aux_engine_regs(0),423 aux_engine_regs(1),424 aux_engine_regs(2),425 aux_engine_regs(3),426 aux_engine_regs(4),427};428 429#define tf_regs(id)\430[id] = {\431 TF_REG_LIST_DCN20(id),\432 TF_REG_LIST_DCN20_COMMON_APPEND(id),\433}434 435static const struct dcn2_dpp_registers tf_regs[] = {436 tf_regs(0),437 tf_regs(1),438 tf_regs(2),439 tf_regs(3),440};441 442static const struct dcn2_dpp_shift tf_shift = {443 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),444 TF_DEBUG_REG_LIST_SH_DCN20445};446 447static const struct dcn2_dpp_mask tf_mask = {448 TF_REG_LIST_SH_MASK_DCN20(_MASK),449 TF_DEBUG_REG_LIST_MASK_DCN20450};451 452#define stream_enc_regs(id)\453[id] = {\454 SE_DCN2_REG_LIST(id)\455}456 457static const struct dcn10_stream_enc_registers stream_enc_regs[] = {458 stream_enc_regs(0),459 stream_enc_regs(1),460 stream_enc_regs(2),461 stream_enc_regs(3),462 stream_enc_regs(4),463};464 465static const struct dce110_aux_registers_shift aux_shift = {466 DCN_AUX_MASK_SH_LIST(__SHIFT)467};468 469static const struct dce110_aux_registers_mask aux_mask = {470 DCN_AUX_MASK_SH_LIST(_MASK)471};472 473static const struct dcn10_stream_encoder_shift se_shift = {474 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)475};476 477static const struct dcn10_stream_encoder_mask se_mask = {478 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)479};480 481static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);482 483static struct input_pixel_processor *dcn21_ipp_create(484 struct dc_context *ctx, uint32_t inst)485{486 struct dcn10_ipp *ipp =487 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);488 489 if (!ipp) {490 BREAK_TO_DEBUGGER();491 return NULL;492 }493 494 dcn20_ipp_construct(ipp, ctx, inst,495 &ipp_regs[inst], &ipp_shift, &ipp_mask);496 return &ipp->base;497}498 499static struct dpp *dcn21_dpp_create(500 struct dc_context *ctx,501 uint32_t inst)502{503 struct dcn20_dpp *dpp =504 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);505 506 if (!dpp)507 return NULL;508 509 if (dpp2_construct(dpp, ctx, inst,510 &tf_regs[inst], &tf_shift, &tf_mask))511 return &dpp->base;512 513 BREAK_TO_DEBUGGER();514 kfree(dpp);515 return NULL;516}517 518static struct dce_aux *dcn21_aux_engine_create(519 struct dc_context *ctx,520 uint32_t inst)521{522 struct aux_engine_dce110 *aux_engine =523 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);524 525 if (!aux_engine)526 return NULL;527 528 dce110_aux_engine_construct(aux_engine, ctx, inst,529 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,530 &aux_engine_regs[inst],531 &aux_mask,532 &aux_shift,533 ctx->dc->caps.extended_aux_timeout_support);534 535 return &aux_engine->base;536}537 538#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }539 540static const struct dce_i2c_registers i2c_hw_regs[] = {541 i2c_inst_regs(1),542 i2c_inst_regs(2),543 i2c_inst_regs(3),544 i2c_inst_regs(4),545 i2c_inst_regs(5),546};547 548static const struct dce_i2c_shift i2c_shifts = {549 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)550};551 552static const struct dce_i2c_mask i2c_masks = {553 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)554};555 556static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,557 uint32_t inst)558{559 struct dce_i2c_hw *dce_i2c_hw =560 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);561 562 if (!dce_i2c_hw)563 return NULL;564 565 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,566 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);567 568 return dce_i2c_hw;569}570 571static const struct resource_caps res_cap_rn = {572 .num_timing_generator = 4,573 .num_opp = 4,574 .num_video_plane = 4,575 .num_audio = 4, // 4 audio endpoints. 4 audio streams576 .num_stream_encoder = 5,577 .num_pll = 5, // maybe 3 because the last two used for USB-c578 .num_dwb = 1,579 .num_ddc = 5,580 .num_vmid = 16,581 .num_dsc = 3,582};583 584static const struct dc_plane_cap plane_cap = {585 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,586 .per_pixel_alpha = true,587 588 .pixel_format_support = {589 .argb8888 = true,590 .nv12 = true,591 .fp16 = true,592 .p010 = true593 },594 595 .max_upscale_factor = {596 .argb8888 = 16000,597 .nv12 = 16000,598 .fp16 = 16000599 },600 601 .max_downscale_factor = {602 .argb8888 = 250,603 .nv12 = 250,604 .fp16 = 250605 },606 64,607 64608};609 610static const struct dc_debug_options debug_defaults_drv = {611 .disable_dmcu = false,612 .force_abm_enable = false,613 .timing_trace = false,614 .clock_trace = true,615 .disable_pplib_clock_request = true,616 .min_disp_clk_khz = 100000,617 .pipe_split_policy = MPC_SPLIT_DYNAMIC,618 .force_single_disp_pipe_split = false,619 .disable_dcc = DCC_ENABLE,620 .vsr_support = true,621 .performance_trace = false,622 .max_downscale_src_width = 4096,623 .disable_pplib_wm_range = false,624 .scl_reset_length10 = true,625 .sanity_checks = true,626 .disable_48mhz_pwrdwn = false,627 .usbc_combo_phy_reset_wa = true,628 .dmub_command_table = true,629 .use_max_lb = true,630 .enable_legacy_fast_update = true,631 .using_dml2 = false,632};633 634static const struct dc_panel_config panel_config_defaults = {635 .psr = {636 .disable_psr = false,637 .disallow_psrsu = false,638 .disallow_replay = false,639 },640 .ilr = {641 .optimize_edp_link_rate = true,642 },643};644 645enum dcn20_clk_src_array_id {646 DCN20_CLK_SRC_PLL0,647 DCN20_CLK_SRC_PLL1,648 DCN20_CLK_SRC_PLL2,649 DCN20_CLK_SRC_PLL3,650 DCN20_CLK_SRC_PLL4,651 DCN20_CLK_SRC_TOTAL_DCN21652};653 654static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)655{656 unsigned int i;657 658 for (i = 0; i < pool->base.stream_enc_count; i++) {659 if (pool->base.stream_enc[i] != NULL) {660 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));661 pool->base.stream_enc[i] = NULL;662 }663 }664 665 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {666 if (pool->base.dscs[i] != NULL)667 dcn20_dsc_destroy(&pool->base.dscs[i]);668 }669 670 if (pool->base.mpc != NULL) {671 kfree(TO_DCN20_MPC(pool->base.mpc));672 pool->base.mpc = NULL;673 }674 if (pool->base.hubbub != NULL) {675 kfree(pool->base.hubbub);676 pool->base.hubbub = NULL;677 }678 for (i = 0; i < pool->base.pipe_count; i++) {679 if (pool->base.dpps[i] != NULL)680 dcn20_dpp_destroy(&pool->base.dpps[i]);681 682 if (pool->base.ipps[i] != NULL)683 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);684 685 if (pool->base.hubps[i] != NULL) {686 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));687 pool->base.hubps[i] = NULL;688 }689 690 if (pool->base.irqs != NULL)691 dal_irq_service_destroy(&pool->base.irqs);692 }693 694 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {695 if (pool->base.engines[i] != NULL)696 dce110_engine_destroy(&pool->base.engines[i]);697 if (pool->base.hw_i2cs[i] != NULL) {698 kfree(pool->base.hw_i2cs[i]);699 pool->base.hw_i2cs[i] = NULL;700 }701 if (pool->base.sw_i2cs[i] != NULL) {702 kfree(pool->base.sw_i2cs[i]);703 pool->base.sw_i2cs[i] = NULL;704 }705 }706 707 for (i = 0; i < pool->base.res_cap->num_opp; i++) {708 if (pool->base.opps[i] != NULL)709 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);710 }711 712 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {713 if (pool->base.timing_generators[i] != NULL) {714 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));715 pool->base.timing_generators[i] = NULL;716 }717 }718 719 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {720 if (pool->base.dwbc[i] != NULL) {721 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));722 pool->base.dwbc[i] = NULL;723 }724 if (pool->base.mcif_wb[i] != NULL) {725 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));726 pool->base.mcif_wb[i] = NULL;727 }728 }729 730 for (i = 0; i < pool->base.audio_count; i++) {731 if (pool->base.audios[i])732 dce_aud_destroy(&pool->base.audios[i]);733 }734 735 for (i = 0; i < pool->base.clk_src_count; i++) {736 if (pool->base.clock_sources[i] != NULL) {737 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);738 pool->base.clock_sources[i] = NULL;739 }740 }741 742 if (pool->base.dp_clock_source != NULL) {743 dcn20_clock_source_destroy(&pool->base.dp_clock_source);744 pool->base.dp_clock_source = NULL;745 }746 747 if (pool->base.abm != NULL) {748 if (pool->base.abm->ctx->dc->config.disable_dmcu)749 dmub_abm_destroy(&pool->base.abm);750 else751 dce_abm_destroy(&pool->base.abm);752 }753 754 if (pool->base.dmcu != NULL)755 dce_dmcu_destroy(&pool->base.dmcu);756 757 if (pool->base.psr != NULL)758 dmub_psr_destroy(&pool->base.psr);759 760 if (pool->base.dccg != NULL)761 dcn_dccg_destroy(&pool->base.dccg);762 763 if (pool->base.pp_smu != NULL)764 dcn21_pp_smu_destroy(&pool->base.pp_smu);765}766 767bool dcn21_fast_validate_bw(struct dc *dc,768 struct dc_state *context,769 display_e2e_pipe_params_st *pipes,770 int *pipe_cnt_out,771 int *pipe_split_from,772 int *vlevel_out,773 bool fast_validate)774{775 bool out = false;776 int split[MAX_PIPES] = { 0 };777 bool merge[MAX_PIPES] = { false };778 int pipe_cnt, i, pipe_idx, vlevel;779 780 ASSERT(pipes);781 if (!pipes)782 return false;783 784 dcn20_merge_pipes_for_validate(dc, context);785 786 DC_FP_START();787 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);788 DC_FP_END();789 790 *pipe_cnt_out = pipe_cnt;791 792 if (!pipe_cnt) {793 out = true;794 goto validate_out;795 }796 /*797 * DML favors voltage over p-state, but we're more interested in798 * supporting p-state over voltage. We can't support p-state in799 * prefetch mode > 0 so try capping the prefetch mode to start.800 */801 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =802 dm_allow_self_refresh_and_mclk_switch;803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);804 805 if (vlevel > context->bw_ctx.dml.soc.num_states) {806 /*807 * If mode is unsupported or there's still no p-state support then808 * fall back to favoring voltage.809 *810 * We don't actually support prefetch mode 2, so require that we811 * at least support prefetch mode 1.812 */813 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =814 dm_allow_self_refresh;815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);816 if (vlevel > context->bw_ctx.dml.soc.num_states)817 goto validate_fail;818 }819 820 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);821 822 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {823 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];824 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;825 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;826 827 if (!pipe->stream)828 continue;829 830 /* We only support full screen mpo with ODM */831 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled832 && pipe->plane_state && mpo_pipe833 && memcmp(&mpo_pipe->plane_state->clip_rect,834 &pipe->stream->src,835 sizeof(struct rect)) != 0) {836 ASSERT(mpo_pipe->plane_state != pipe->plane_state);837 goto validate_fail;838 }839 pipe_idx++;840 }841 842 /*initialize pipe_just_split_from to invalid idx*/843 for (i = 0; i < MAX_PIPES; i++)844 pipe_split_from[i] = -1;845 846 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {847 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];848 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;849 850 if (!pipe->stream || pipe_split_from[i] >= 0)851 continue;852 853 pipe_idx++;854 855 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {856 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);857 ASSERT(hsplit_pipe);858 if (!dcn20_split_stream_for_odm(859 dc, &context->res_ctx,860 pipe, hsplit_pipe))861 goto validate_fail;862 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;863 dcn20_build_mapped_resource(dc, context, pipe->stream);864 }865 866 if (!pipe->plane_state)867 continue;868 /* Skip 2nd half of already split pipe */869 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)870 continue;871 872 if (split[i] == 2) {873 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {874 /* pipe not split previously needs split */875 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);876 ASSERT(hsplit_pipe);877 if (!hsplit_pipe) {878 DC_FP_START();879 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);880 DC_FP_END();881 continue;882 }883 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {884 if (!dcn20_split_stream_for_odm(885 dc, &context->res_ctx,886 pipe, hsplit_pipe))887 goto validate_fail;888 dcn20_build_mapped_resource(dc, context, pipe->stream);889 } else {890 dcn20_split_stream_for_mpc(891 &context->res_ctx, dc->res_pool,892 pipe, hsplit_pipe);893 resource_build_scaling_params(pipe);894 resource_build_scaling_params(hsplit_pipe);895 }896 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;897 }898 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {899 /* merge should already have been done */900 ASSERT(0);901 }902 }903 /* Actual dsc count per stream dsc validation*/904 if (!dcn20_validate_dsc(dc, context)) {905 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =906 DML_FAIL_DSC_VALIDATION_FAILURE;907 goto validate_fail;908 }909 910 *vlevel_out = vlevel;911 912 out = true;913 goto validate_out;914 915validate_fail:916 out = false;917 918validate_out:919 return out;920}921 922/*923 * Some of the functions further below use the FPU, so we need to wrap this924 * with DC_FP_START()/DC_FP_END(). Use the same approach as for925 * dcn20_validate_bandwidth in dcn20_resource.c.926 */927static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,928 bool fast_validate)929{930 bool voltage_supported;931 display_e2e_pipe_params_st *pipes;932 933 pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);934 if (!pipes)935 return false;936 937 DC_FP_START();938 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);939 DC_FP_END();940 941 kfree(pipes);942 return voltage_supported;943}944 945static void dcn21_destroy_resource_pool(struct resource_pool **pool)946{947 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);948 949 dcn21_resource_destruct(dcn21_pool);950 kfree(dcn21_pool);951 *pool = NULL;952}953 954static struct clock_source *dcn21_clock_source_create(955 struct dc_context *ctx,956 struct dc_bios *bios,957 enum clock_source_id id,958 const struct dce110_clk_src_regs *regs,959 bool dp_clk_src)960{961 struct dce110_clk_src *clk_src =962 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);963 964 if (!clk_src)965 return NULL;966 967 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,968 regs, &cs_shift, &cs_mask)) {969 clk_src->base.dp_clk_src = dp_clk_src;970 return &clk_src->base;971 }972 973 kfree(clk_src);974 BREAK_TO_DEBUGGER();975 return NULL;976}977 978static struct hubp *dcn21_hubp_create(979 struct dc_context *ctx,980 uint32_t inst)981{982 struct dcn21_hubp *hubp21 =983 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);984 985 if (!hubp21)986 return NULL;987 988 if (hubp21_construct(hubp21, ctx, inst,989 &hubp_regs[inst], &hubp_shift, &hubp_mask))990 return &hubp21->base;991 992 BREAK_TO_DEBUGGER();993 kfree(hubp21);994 return NULL;995}996 997static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)998{999 int i;1000 1001 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),1002 GFP_KERNEL);1003 1004 if (!hubbub)1005 return NULL;1006 1007 hubbub21_construct(hubbub, ctx,1008 &hubbub_reg,1009 &hubbub_shift,1010 &hubbub_mask);1011 1012 for (i = 0; i < res_cap_rn.num_vmid; i++) {1013 struct dcn20_vmid *vmid = &hubbub->vmid[i];1014 1015 vmid->ctx = ctx;1016 1017 vmid->regs = &vmid_regs[i];1018 vmid->shifts = &vmid_shifts;1019 vmid->masks = &vmid_masks;1020 }1021 hubbub->num_vmid = res_cap_rn.num_vmid;1022 1023 return &hubbub->base;1024}1025 1026static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,1027 uint32_t inst)1028{1029 struct dcn20_opp *opp =1030 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);1031 1032 if (!opp) {1033 BREAK_TO_DEBUGGER();1034 return NULL;1035 }1036 1037 dcn20_opp_construct(opp, ctx, inst,1038 &opp_regs[inst], &opp_shift, &opp_mask);1039 return &opp->base;1040}1041 1042static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,1043 uint32_t instance)1044{1045 struct optc *tgn10 =1046 kzalloc(sizeof(struct optc), GFP_KERNEL);1047 1048 if (!tgn10)1049 return NULL;1050 1051 tgn10->base.inst = instance;1052 tgn10->base.ctx = ctx;1053 1054 tgn10->tg_regs = &tg_regs[instance];1055 tgn10->tg_shift = &tg_shift;1056 tgn10->tg_mask = &tg_mask;1057 1058 dcn20_timing_generator_init(tgn10);1059 1060 return &tgn10->base;1061}1062 1063static struct mpc *dcn21_mpc_create(struct dc_context *ctx)1064{1065 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),1066 GFP_KERNEL);1067 1068 if (!mpc20)1069 return NULL;1070 1071 dcn20_mpc_construct(mpc20, ctx,1072 &mpc_regs,1073 &mpc_shift,1074 &mpc_mask,1075 6);1076 1077 return &mpc20->base;1078}1079 1080static void read_dce_straps(1081 struct dc_context *ctx,1082 struct resource_straps *straps)1083{1084 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),1085 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);1086 1087}1088 1089 1090static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,1091 uint32_t inst)1092{1093 struct dcn20_dsc *dsc =1094 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);1095 1096 if (!dsc) {1097 BREAK_TO_DEBUGGER();1098 return NULL;1099 }1100 1101 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1102 return &dsc->base;1103}1104 1105static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)1106{1107 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);1108 1109 if (!pp_smu)1110 return pp_smu;1111 1112 dm_pp_get_funcs(ctx, pp_smu);1113 1114 if (pp_smu->ctx.ver != PP_SMU_VER_RN)1115 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));1116 1117 1118 return pp_smu;1119}1120 1121static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)1122{1123 if (pp_smu && *pp_smu) {1124 kfree(*pp_smu);1125 *pp_smu = NULL;1126 }1127}1128 1129static struct audio *dcn21_create_audio(1130 struct dc_context *ctx, unsigned int inst)1131{1132 return dce_audio_create(ctx, inst,1133 &audio_regs[inst], &audio_shift, &audio_mask);1134}1135 1136static struct dc_cap_funcs cap_funcs = {1137 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap1138};1139 1140static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,1141 struct dc_context *ctx)1142{1143 struct dcn10_stream_encoder *enc1 =1144 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1145 1146 if (!enc1)1147 return NULL;1148 1149 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,1150 &stream_enc_regs[eng_id],1151 &se_shift, &se_mask);1152 1153 return &enc1->base;1154}1155 1156static const struct dce_hwseq_registers hwseq_reg = {1157 HWSEQ_DCN21_REG_LIST()1158};1159 1160static const struct dce_hwseq_shift hwseq_shift = {1161 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)1162};1163 1164static const struct dce_hwseq_mask hwseq_mask = {1165 HWSEQ_DCN21_MASK_SH_LIST(_MASK)1166};1167 1168static struct dce_hwseq *dcn21_hwseq_create(1169 struct dc_context *ctx)1170{1171 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1172 1173 if (hws) {1174 hws->ctx = ctx;1175 hws->regs = &hwseq_reg;1176 hws->shifts = &hwseq_shift;1177 hws->masks = &hwseq_mask;1178 hws->wa.DEGVIDCN21 = true;1179 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;1180 }1181 return hws;1182}1183 1184static const struct resource_create_funcs res_create_funcs = {1185 .read_dce_straps = read_dce_straps,1186 .create_audio = dcn21_create_audio,1187 .create_stream_encoder = dcn21_stream_encoder_create,1188 .create_hwseq = dcn21_hwseq_create,1189};1190 1191static const struct encoder_feature_support link_enc_feature = {1192 .max_hdmi_deep_color = COLOR_DEPTH_121212,1193 .max_hdmi_pixel_clock = 600000,1194 .hdmi_ycbcr420_supported = true,1195 .dp_ycbcr420_supported = true,1196 .fec_supported = true,1197 .flags.bits.IS_HBR2_CAPABLE = true,1198 .flags.bits.IS_HBR3_CAPABLE = true,1199 .flags.bits.IS_TPS3_CAPABLE = true,1200 .flags.bits.IS_TPS4_CAPABLE = true1201};1202 1203 1204#define link_regs(id, phyid)\1205[id] = {\1206 LE_DCN2_REG_LIST(id), \1207 UNIPHY_DCN2_REG_LIST(phyid), \1208 DPCS_DCN21_REG_LIST(id), \1209 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \1210}1211 1212static const struct dcn10_link_enc_registers link_enc_regs[] = {1213 link_regs(0, A),1214 link_regs(1, B),1215 link_regs(2, C),1216 link_regs(3, D),1217 link_regs(4, E),1218};1219 1220static const struct dce_panel_cntl_registers panel_cntl_regs[] = {1221 { DCN_PANEL_CNTL_REG_LIST() }1222};1223 1224static const struct dce_panel_cntl_shift panel_cntl_shift = {1225 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)1226};1227 1228static const struct dce_panel_cntl_mask panel_cntl_mask = {1229 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)1230};1231 1232#define aux_regs(id)\1233[id] = {\1234 DCN2_AUX_REG_LIST(id)\1235}1236 1237static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {1238 aux_regs(0),1239 aux_regs(1),1240 aux_regs(2),1241 aux_regs(3),1242 aux_regs(4)1243};1244 1245#define hpd_regs(id)\1246[id] = {\1247 HPD_REG_LIST(id)\1248}1249 1250static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {1251 hpd_regs(0),1252 hpd_regs(1),1253 hpd_regs(2),1254 hpd_regs(3),1255 hpd_regs(4)1256};1257 1258static const struct dcn10_link_enc_shift le_shift = {1259 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\1260 DPCS_DCN21_MASK_SH_LIST(__SHIFT)1261};1262 1263static const struct dcn10_link_enc_mask le_mask = {1264 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\1265 DPCS_DCN21_MASK_SH_LIST(_MASK)1266};1267 1268static int map_transmitter_id_to_phy_instance(1269 enum transmitter transmitter)1270{1271 switch (transmitter) {1272 case TRANSMITTER_UNIPHY_A:1273 return 0;1274 break;1275 case TRANSMITTER_UNIPHY_B:1276 return 1;1277 break;1278 case TRANSMITTER_UNIPHY_C:1279 return 2;1280 break;1281 case TRANSMITTER_UNIPHY_D:1282 return 3;1283 break;1284 case TRANSMITTER_UNIPHY_E:1285 return 4;1286 break;1287 default:1288 ASSERT(0);1289 return 0;1290 }1291}1292 1293static struct link_encoder *dcn21_link_encoder_create(1294 struct dc_context *ctx,1295 const struct encoder_init_data *enc_init_data)1296{1297 struct dcn21_link_encoder *enc21 =1298 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);1299 int link_regs_id;1300 1301 if (!enc21)1302 return NULL;1303 1304 link_regs_id =1305 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);1306 1307 dcn21_link_encoder_construct(enc21,1308 enc_init_data,1309 &link_enc_feature,1310 &link_enc_regs[link_regs_id],1311 &link_enc_aux_regs[enc_init_data->channel - 1],1312 &link_enc_hpd_regs[enc_init_data->hpd_source],1313 &le_shift,1314 &le_mask);1315 1316 return &enc21->enc10.base;1317}1318 1319static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)1320{1321 struct dce_panel_cntl *panel_cntl =1322 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);1323 1324 if (!panel_cntl)1325 return NULL;1326 1327 dce_panel_cntl_construct(panel_cntl,1328 init_data,1329 &panel_cntl_regs[init_data->inst],1330 &panel_cntl_shift,1331 &panel_cntl_mask);1332 1333 return &panel_cntl->base;1334}1335 1336static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)1337{1338 *panel_config = panel_config_defaults;1339}1340 1341#define CTX ctx1342 1343#define REG(reg_name) \1344 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)1345 1346static uint32_t read_pipe_fuses(struct dc_context *ctx)1347{1348 uint32_t value = REG_READ(CC_DC_PIPE_DIS);1349 /* RV1 support max 4 pipes */1350 value = value & 0xf;1351 return value;1352}1353 1354static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)1355{1356 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {1357 plane_state->dcc.enable = 1;1358 /* align to our worst case block width */1359 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;1360 }1361 1362 return dcn20_patch_unknown_plane_state(plane_state);1363}1364 1365static const struct resource_funcs dcn21_res_pool_funcs = {1366 .destroy = dcn21_destroy_resource_pool,1367 .link_enc_create = dcn21_link_encoder_create,1368 .panel_cntl_create = dcn21_panel_cntl_create,1369 .validate_bandwidth = dcn21_validate_bandwidth,1370 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,1371 .add_stream_to_ctx = dcn20_add_stream_to_ctx,1372 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1373 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1374 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,1375 .release_pipe = dcn20_release_pipe,1376 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,1377 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,1378 .set_mcif_arb_params = dcn20_set_mcif_arb_params,1379 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1380 .update_bw_bounding_box = dcn21_update_bw_bounding_box,1381 .get_panel_config_defaults = dcn21_get_panel_config_defaults,1382};1383 1384static bool dcn21_resource_construct(1385 uint8_t num_virtual_links,1386 struct dc *dc,1387 struct dcn21_resource_pool *pool)1388{1389 int i, j;1390 struct dc_context *ctx = dc->ctx;1391 struct irq_service_init_data init_data;1392 uint32_t pipe_fuses = read_pipe_fuses(ctx);1393 uint32_t num_pipes = 0;1394 1395 ctx->dc_bios->regs = &bios_regs;1396 1397 pool->base.res_cap = &res_cap_rn;1398 1399 pool->base.funcs = &dcn21_res_pool_funcs;1400 1401 /*************************************************1402 * Resource + asic cap harcoding *1403 *************************************************/1404 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;1405 1406 /* max pipe num for ASIC before check pipe fuses */1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;1408 1409 dc->caps.max_downscale_ratio = 200;1410 dc->caps.i2c_speed_in_khz = 100;1411 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/1412 dc->caps.max_cursor_size = 256;1413 dc->caps.min_horizontal_blanking_period = 80;1414 dc->caps.dmdata_alloc_size = 2048;1415 1416 dc->caps.max_slave_planes = 1;1417 dc->caps.max_slave_yuv_planes = 1;1418 dc->caps.max_slave_rgb_planes = 1;1419 dc->caps.post_blend_color_processing = true;1420 dc->caps.force_dp_tps4_for_cp2520 = true;1421 dc->caps.extended_aux_timeout_support = true;1422 dc->caps.dmcub_support = true;1423 dc->caps.is_apu = true;1424 1425 /* Color pipeline capabilities */1426 dc->caps.color.dpp.dcn_arch = 1;1427 dc->caps.color.dpp.input_lut_shared = 0;1428 dc->caps.color.dpp.icsc = 1;1429 dc->caps.color.dpp.dgam_ram = 1;1430 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1431 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1432 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;1433 dc->caps.color.dpp.dgam_rom_caps.pq = 0;1434 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;1435 dc->caps.color.dpp.post_csc = 0;1436 dc->caps.color.dpp.gamma_corr = 0;1437 dc->caps.color.dpp.dgam_rom_for_yuv = 1;1438 1439 dc->caps.color.dpp.hw_3d_lut = 1;1440 dc->caps.color.dpp.ogam_ram = 1;1441 // no OGAM ROM on DCN21442 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1443 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1444 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1445 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1446 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1447 dc->caps.color.dpp.ocsc = 0;1448 1449 dc->caps.color.mpc.gamut_remap = 0;1450 dc->caps.color.mpc.num_3dluts = 0;1451 dc->caps.color.mpc.shared_3d_lut = 0;1452 dc->caps.color.mpc.ogam_ram = 1;1453 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1454 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1455 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1456 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1457 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1458 dc->caps.color.mpc.ocsc = 1;1459 1460 dc->caps.dp_hdmi21_pcon_support = true;1461 1462 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1463 dc->debug = debug_defaults_drv;1464 1465 // Init the vm_helper1466 if (dc->vm_helper)1467 vm_helper_init(dc->vm_helper, 16);1468 1469 /*************************************************1470 * Create resources *1471 *************************************************/1472 1473 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =1474 dcn21_clock_source_create(ctx, ctx->dc_bios,1475 CLOCK_SOURCE_COMBO_PHY_PLL0,1476 &clk_src_regs[0], false);1477 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =1478 dcn21_clock_source_create(ctx, ctx->dc_bios,1479 CLOCK_SOURCE_COMBO_PHY_PLL1,1480 &clk_src_regs[1], false);1481 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =1482 dcn21_clock_source_create(ctx, ctx->dc_bios,1483 CLOCK_SOURCE_COMBO_PHY_PLL2,1484 &clk_src_regs[2], false);1485 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =1486 dcn21_clock_source_create(ctx, ctx->dc_bios,1487 CLOCK_SOURCE_COMBO_PHY_PLL3,1488 &clk_src_regs[3], false);1489 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =1490 dcn21_clock_source_create(ctx, ctx->dc_bios,1491 CLOCK_SOURCE_COMBO_PHY_PLL4,1492 &clk_src_regs[4], false);1493 1494 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;1495 1496 /* todo: not reuse phy_pll registers */1497 pool->base.dp_clock_source =1498 dcn21_clock_source_create(ctx, ctx->dc_bios,1499 CLOCK_SOURCE_ID_DP_DTO,1500 &clk_src_regs[0], true);1501 1502 for (i = 0; i < pool->base.clk_src_count; i++) {1503 if (pool->base.clock_sources[i] == NULL) {1504 dm_error("DC: failed to create clock sources!\n");1505 BREAK_TO_DEBUGGER();1506 goto create_fail;1507 }1508 }1509 1510 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1511 if (pool->base.dccg == NULL) {1512 dm_error("DC: failed to create dccg!\n");1513 BREAK_TO_DEBUGGER();1514 goto create_fail;1515 }1516 1517 if (!dc->config.disable_dmcu) {1518 pool->base.dmcu = dcn21_dmcu_create(ctx,1519 &dmcu_regs,1520 &dmcu_shift,1521 &dmcu_mask);1522 if (pool->base.dmcu == NULL) {1523 dm_error("DC: failed to create dmcu!\n");1524 BREAK_TO_DEBUGGER();1525 goto create_fail;1526 }1527 1528 dc->debug.dmub_command_table = false;1529 }1530 1531 if (dc->config.disable_dmcu) {1532 pool->base.psr = dmub_psr_create(ctx);1533 1534 if (pool->base.psr == NULL) {1535 dm_error("DC: failed to create psr obj!\n");1536 BREAK_TO_DEBUGGER();1537 goto create_fail;1538 }1539 }1540 1541 if (dc->config.disable_dmcu)1542 pool->base.abm = dmub_abm_create(ctx,1543 &abm_regs,1544 &abm_shift,1545 &abm_mask);1546 else1547 pool->base.abm = dce_abm_create(ctx,1548 &abm_regs,1549 &abm_shift,1550 &abm_mask);1551 1552 pool->base.pp_smu = dcn21_pp_smu_create(ctx);1553 1554 num_pipes = dcn2_1_ip.max_num_dpp;1555 1556 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)1557 if (pipe_fuses & 1 << i)1558 num_pipes--;1559 dcn2_1_ip.max_num_dpp = num_pipes;1560 dcn2_1_ip.max_num_otg = num_pipes;1561 1562 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);1563 1564 init_data.ctx = dc->ctx;1565 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);1566 if (!pool->base.irqs)1567 goto create_fail;1568 1569 j = 0;1570 /* mem input -> ipp -> dpp -> opp -> TG */1571 for (i = 0; i < pool->base.pipe_count; i++) {1572 /* if pipe is disabled, skip instance of HW pipe,1573 * i.e, skip ASIC register instance1574 */1575 if ((pipe_fuses & (1 << i)) != 0)1576 continue;1577 1578 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);1579 if (pool->base.hubps[j] == NULL) {1580 BREAK_TO_DEBUGGER();1581 dm_error(1582 "DC: failed to create memory input!\n");1583 goto create_fail;1584 }1585 1586 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);1587 if (pool->base.ipps[j] == NULL) {1588 BREAK_TO_DEBUGGER();1589 dm_error(1590 "DC: failed to create input pixel processor!\n");1591 goto create_fail;1592 }1593 1594 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);1595 if (pool->base.dpps[j] == NULL) {1596 BREAK_TO_DEBUGGER();1597 dm_error(1598 "DC: failed to create dpps!\n");1599 goto create_fail;1600 }1601 1602 pool->base.opps[j] = dcn21_opp_create(ctx, i);1603 if (pool->base.opps[j] == NULL) {1604 BREAK_TO_DEBUGGER();1605 dm_error(1606 "DC: failed to create output pixel processor!\n");1607 goto create_fail;1608 }1609 1610 pool->base.timing_generators[j] = dcn21_timing_generator_create(1611 ctx, i);1612 if (pool->base.timing_generators[j] == NULL) {1613 BREAK_TO_DEBUGGER();1614 dm_error("DC: failed to create tg!\n");1615 goto create_fail;1616 }1617 j++;1618 }1619 1620 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1621 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);1622 if (pool->base.engines[i] == NULL) {1623 BREAK_TO_DEBUGGER();1624 dm_error(1625 "DC:failed to create aux engine!!\n");1626 goto create_fail;1627 }1628 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);1629 if (pool->base.hw_i2cs[i] == NULL) {1630 BREAK_TO_DEBUGGER();1631 dm_error(1632 "DC:failed to create hw i2c!!\n");1633 goto create_fail;1634 }1635 pool->base.sw_i2cs[i] = NULL;1636 }1637 1638 pool->base.timing_generator_count = j;1639 pool->base.pipe_count = j;1640 pool->base.mpcc_count = j;1641 1642 pool->base.mpc = dcn21_mpc_create(ctx);1643 if (pool->base.mpc == NULL) {1644 BREAK_TO_DEBUGGER();1645 dm_error("DC: failed to create mpc!\n");1646 goto create_fail;1647 }1648 1649 pool->base.hubbub = dcn21_hubbub_create(ctx);1650 if (pool->base.hubbub == NULL) {1651 BREAK_TO_DEBUGGER();1652 dm_error("DC: failed to create hubbub!\n");1653 goto create_fail;1654 }1655 1656 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1657 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);1658 if (pool->base.dscs[i] == NULL) {1659 BREAK_TO_DEBUGGER();1660 dm_error("DC: failed to create display stream compressor %d!\n", i);1661 goto create_fail;1662 }1663 }1664 1665 if (!dcn20_dwbc_create(ctx, &pool->base)) {1666 BREAK_TO_DEBUGGER();1667 dm_error("DC: failed to create dwbc!\n");1668 goto create_fail;1669 }1670 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {1671 BREAK_TO_DEBUGGER();1672 dm_error("DC: failed to create mcif_wb!\n");1673 goto create_fail;1674 }1675 1676 if (!resource_construct(num_virtual_links, dc, &pool->base,1677 &res_create_funcs))1678 goto create_fail;1679 1680 dcn21_hw_sequencer_construct(dc);1681 1682 dc->caps.max_planes = pool->base.pipe_count;1683 1684 for (i = 0; i < dc->caps.max_planes; ++i)1685 dc->caps.planes[i] = plane_cap;1686 1687 dc->cap_funcs = cap_funcs;1688 1689 return true;1690 1691create_fail:1692 1693 dcn21_resource_destruct(pool);1694 1695 return false;1696}1697 1698struct resource_pool *dcn21_create_resource_pool(1699 const struct dc_init_data *init_data,1700 struct dc *dc)1701{1702 struct dcn21_resource_pool *pool =1703 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);1704 1705 if (!pool)1706 return NULL;1707 1708 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))1709 return &pool->base;1710 1711 BREAK_TO_DEBUGGER();1712 kfree(pool);1713 return NULL;1714}1715