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1// SPDX-License-Identifier: MIT2/*3 * Copyright (C) 2021 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 */25 26#include "dcn303/dcn303_init.h"27#include "dcn303_resource.h"28#include "dcn303/dcn303_dccg.h"29#include "irq/dcn303/irq_service_dcn303.h"30 31#include "dcn30/dcn30_dio_link_encoder.h"32#include "dcn30/dcn30_dio_stream_encoder.h"33#include "dcn30/dcn30_dpp.h"34#include "dcn30/dcn30_dwb.h"35#include "dcn30/dcn30_hubbub.h"36#include "dcn30/dcn30_hubp.h"37#include "dcn30/dcn30_mmhubbub.h"38#include "dcn30/dcn30_mpc.h"39#include "dcn30/dcn30_opp.h"40#include "dcn30/dcn30_optc.h"41#include "dcn30/dcn30_resource.h"42 43#include "dcn20/dcn20_dsc.h"44#include "dcn20/dcn20_resource.h"45 46#include "dml/dcn30/dcn30_fpu.h"47 48#include "dcn10/dcn10_resource.h"49 50#include "link.h"51 52#include "dce/dce_abm.h"53#include "dce/dce_audio.h"54#include "dce/dce_aux.h"55#include "dce/dce_clock_source.h"56#include "dce/dce_hwseq.h"57#include "dce/dce_i2c_hw.h"58#include "dce/dce_panel_cntl.h"59#include "dce/dmub_abm.h"60#include "dce/dmub_psr.h"61#include "clk_mgr.h"62 63#include "hw_sequencer_private.h"64#include "reg_helper.h"65#include "resource.h"66#include "vm_helper.h"67 68#include "sienna_cichlid_ip_offset.h"69#include "dcn/dcn_3_0_3_offset.h"70#include "dcn/dcn_3_0_3_sh_mask.h"71#include "dpcs/dpcs_3_0_3_offset.h"72#include "dpcs/dpcs_3_0_3_sh_mask.h"73#include "nbio/nbio_2_3_offset.h"74 75#include "dml/dcn303/dcn303_fpu.h"76 77#define DC_LOGGER \78 dc->ctx->logger79#define DC_LOGGER_INIT(logger)80 81 82static const struct dc_debug_options debug_defaults_drv = {83 .disable_dmcu = true,84 .force_abm_enable = false,85 .timing_trace = false,86 .clock_trace = true,87 .disable_pplib_clock_request = true,88 .pipe_split_policy = MPC_SPLIT_AVOID,89 .force_single_disp_pipe_split = false,90 .disable_dcc = DCC_ENABLE,91 .vsr_support = true,92 .performance_trace = false,93 .max_downscale_src_width = 7680,/*upto 8K*/94 .disable_pplib_wm_range = false,95 .scl_reset_length10 = true,96 .sanity_checks = false,97 .underflow_assert_delay_us = 0xFFFFFFFF,98 .dwb_fi_phase = -1, // -1 = disable,99 .dmub_command_table = true,100 .use_max_lb = true,101 .exit_idle_opt_for_cursor_updates = true,102 .enable_legacy_fast_update = false,103 .using_dml2 = false,104};105 106static const struct dc_panel_config panel_config_defaults = {107 .psr = {108 .disable_psr = false,109 .disallow_psrsu = false,110 .disallow_replay = false,111 },112};113 114enum dcn303_clk_src_array_id {115 DCN303_CLK_SRC_PLL0,116 DCN303_CLK_SRC_PLL1,117 DCN303_CLK_SRC_TOTAL118};119 120static const struct resource_caps res_cap_dcn303 = {121 .num_timing_generator = 2,122 .num_opp = 2,123 .num_video_plane = 2,124 .num_audio = 2,125 .num_stream_encoder = 2,126 .num_dwb = 1,127 .num_ddc = 2,128 .num_vmid = 16,129 .num_mpc_3dlut = 1,130 .num_dsc = 2,131};132 133static const struct dc_plane_cap plane_cap = {134 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,135 .per_pixel_alpha = true,136 .pixel_format_support = {137 .argb8888 = true,138 .nv12 = true,139 .fp16 = true,140 .p010 = true,141 .ayuv = false,142 },143 .max_upscale_factor = {144 .argb8888 = 16000,145 .nv12 = 16000,146 .fp16 = 16000147 },148 .max_downscale_factor = {149 .argb8888 = 167,150 .nv12 = 167,151 .fp16 = 167152 },153 16,154 16155};156 157/* NBIO */158#define NBIO_BASE_INNER(seg) \159 NBIO_BASE__INST0_SEG ## seg160 161#define NBIO_BASE(seg) \162 NBIO_BASE_INNER(seg)163 164#define NBIO_SR(reg_name)\165 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \166 mm ## reg_name167 168/* DCN */169#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg170 171#define BASE(seg) BASE_INNER(seg)172 173#define SR(reg_name)\174 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name175 176#define SF(reg_name, field_name, post_fix)\177 .field_name = reg_name ## __ ## field_name ## post_fix178 179#define SRI(reg_name, block, id)\180 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name181 182#define SRI2(reg_name, block, id)\183 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name184 185#define SRII(reg_name, block, id)\186 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \187 mm ## block ## id ## _ ## reg_name188 189#define DCCG_SRII(reg_name, block, id)\190 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \191 mm ## block ## id ## _ ## reg_name192 193#define VUPDATE_SRII(reg_name, block, id)\194 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \195 mm ## reg_name ## _ ## block ## id196 197#define SRII_DWB(reg_name, temp_name, block, id)\198 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \199 mm ## block ## id ## _ ## temp_name200 201#define SF_DWB2(reg_name, block, id, field_name, post_fix) \202 .field_name = reg_name ## __ ## field_name ## post_fix203 204#define SRII_MPC_RMU(reg_name, block, id)\205 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \206 mm ## block ## id ## _ ## reg_name207 208static const struct dcn_hubbub_registers hubbub_reg = {209 HUBBUB_REG_LIST_DCN30(0)210};211 212static const struct dcn_hubbub_shift hubbub_shift = {213 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)214};215 216static const struct dcn_hubbub_mask hubbub_mask = {217 HUBBUB_MASK_SH_LIST_DCN30(_MASK)218};219 220#define vmid_regs(id)\221 [id] = { DCN20_VMID_REG_LIST(id) }222 223static const struct dcn_vmid_registers vmid_regs[] = {224 vmid_regs(0),225 vmid_regs(1),226 vmid_regs(2),227 vmid_regs(3),228 vmid_regs(4),229 vmid_regs(5),230 vmid_regs(6),231 vmid_regs(7),232 vmid_regs(8),233 vmid_regs(9),234 vmid_regs(10),235 vmid_regs(11),236 vmid_regs(12),237 vmid_regs(13),238 vmid_regs(14),239 vmid_regs(15)240};241 242static const struct dcn20_vmid_shift vmid_shifts = {243 DCN20_VMID_MASK_SH_LIST(__SHIFT)244};245 246static const struct dcn20_vmid_mask vmid_masks = {247 DCN20_VMID_MASK_SH_LIST(_MASK)248};249 250static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)251{252 int i;253 254 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);255 256 if (!hubbub3)257 return NULL;258 259 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);260 261 for (i = 0; i < res_cap_dcn303.num_vmid; i++) {262 struct dcn20_vmid *vmid = &hubbub3->vmid[i];263 264 vmid->ctx = ctx;265 266 vmid->regs = &vmid_regs[i];267 vmid->shifts = &vmid_shifts;268 vmid->masks = &vmid_masks;269 }270 271 return &hubbub3->base;272}273 274#define vpg_regs(id)\275 [id] = { VPG_DCN3_REG_LIST(id) }276 277static const struct dcn30_vpg_registers vpg_regs[] = {278 vpg_regs(0),279 vpg_regs(1),280 vpg_regs(2)281};282 283static const struct dcn30_vpg_shift vpg_shift = {284 DCN3_VPG_MASK_SH_LIST(__SHIFT)285};286 287static const struct dcn30_vpg_mask vpg_mask = {288 DCN3_VPG_MASK_SH_LIST(_MASK)289};290 291static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)292{293 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);294 295 if (!vpg3)296 return NULL;297 298 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);299 300 return &vpg3->base;301}302 303#define afmt_regs(id)\304 [id] = { AFMT_DCN3_REG_LIST(id) }305 306static const struct dcn30_afmt_registers afmt_regs[] = {307 afmt_regs(0),308 afmt_regs(1),309 afmt_regs(2)310};311 312static const struct dcn30_afmt_shift afmt_shift = {313 DCN3_AFMT_MASK_SH_LIST(__SHIFT)314};315 316static const struct dcn30_afmt_mask afmt_mask = {317 DCN3_AFMT_MASK_SH_LIST(_MASK)318};319 320static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)321{322 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);323 324 if (!afmt3)325 return NULL;326 327 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);328 329 return &afmt3->base;330}331 332#define audio_regs(id)\333 [id] = { AUD_COMMON_REG_LIST(id) }334 335static const struct dce_audio_registers audio_regs[] = {336 audio_regs(0),337 audio_regs(1),338 audio_regs(2),339 audio_regs(3),340 audio_regs(4),341 audio_regs(5),342 audio_regs(6)343};344 345#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\348 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)349 350static const struct dce_audio_shift audio_shift = {351 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)352};353 354static const struct dce_audio_mask audio_mask = {355 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)356};357 358static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)359{360 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);361}362 363#define stream_enc_regs(id)\364 [id] = { SE_DCN3_REG_LIST(id) }365 366static const struct dcn10_stream_enc_registers stream_enc_regs[] = {367 stream_enc_regs(0),368 stream_enc_regs(1)369};370 371static const struct dcn10_stream_encoder_shift se_shift = {372 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)373};374 375static const struct dcn10_stream_encoder_mask se_mask = {376 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)377};378 379static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)380{381 struct dcn10_stream_encoder *enc1;382 struct vpg *vpg;383 struct afmt *afmt;384 int vpg_inst;385 int afmt_inst;386 387 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */388 if (eng_id <= ENGINE_ID_DIGB) {389 vpg_inst = eng_id;390 afmt_inst = eng_id;391 } else392 return NULL;393 394 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);395 vpg = dcn303_vpg_create(ctx, vpg_inst);396 afmt = dcn303_afmt_create(ctx, afmt_inst);397 398 if (!enc1 || !vpg || !afmt) {399 kfree(enc1);400 kfree(vpg);401 kfree(afmt);402 return NULL;403 }404 405 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],406 &se_shift, &se_mask);407 408 return &enc1->base;409}410 411#define clk_src_regs(index, pllid)\412 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }413 414static const struct dce110_clk_src_regs clk_src_regs[] = {415 clk_src_regs(0, A),416 clk_src_regs(1, B)417};418 419static const struct dce110_clk_src_shift cs_shift = {420 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)421};422 423static const struct dce110_clk_src_mask cs_mask = {424 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)425};426 427static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,428 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)429{430 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);431 432 if (!clk_src)433 return NULL;434 435 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {436 clk_src->base.dp_clk_src = dp_clk_src;437 return &clk_src->base;438 }439 440 kfree(clk_src);441 BREAK_TO_DEBUGGER();442 return NULL;443}444 445static const struct dce_hwseq_registers hwseq_reg = {446 HWSEQ_DCN303_REG_LIST()447};448 449static const struct dce_hwseq_shift hwseq_shift = {450 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)451};452 453static const struct dce_hwseq_mask hwseq_mask = {454 HWSEQ_DCN303_MASK_SH_LIST(_MASK)455};456 457static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)458{459 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);460 461 if (hws) {462 hws->ctx = ctx;463 hws->regs = &hwseq_reg;464 hws->shifts = &hwseq_shift;465 hws->masks = &hwseq_mask;466 }467 return hws;468}469 470#define hubp_regs(id)\471 [id] = { HUBP_REG_LIST_DCN30(id) }472 473static const struct dcn_hubp2_registers hubp_regs[] = {474 hubp_regs(0),475 hubp_regs(1)476};477 478static const struct dcn_hubp2_shift hubp_shift = {479 HUBP_MASK_SH_LIST_DCN30(__SHIFT)480};481 482static const struct dcn_hubp2_mask hubp_mask = {483 HUBP_MASK_SH_LIST_DCN30(_MASK)484};485 486static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)487{488 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);489 490 if (!hubp2)491 return NULL;492 493 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))494 return &hubp2->base;495 496 BREAK_TO_DEBUGGER();497 kfree(hubp2);498 return NULL;499}500 501#define dpp_regs(id)\502 [id] = { DPP_REG_LIST_DCN30(id) }503 504static const struct dcn3_dpp_registers dpp_regs[] = {505 dpp_regs(0),506 dpp_regs(1)507};508 509static const struct dcn3_dpp_shift tf_shift = {510 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)511};512 513static const struct dcn3_dpp_mask tf_mask = {514 DPP_REG_LIST_SH_MASK_DCN30(_MASK)515};516 517static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)518{519 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);520 521 if (!dpp)522 return NULL;523 524 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))525 return &dpp->base;526 527 BREAK_TO_DEBUGGER();528 kfree(dpp);529 return NULL;530}531 532#define opp_regs(id)\533 [id] = { OPP_REG_LIST_DCN30(id) }534 535static const struct dcn20_opp_registers opp_regs[] = {536 opp_regs(0),537 opp_regs(1)538};539 540static const struct dcn20_opp_shift opp_shift = {541 OPP_MASK_SH_LIST_DCN20(__SHIFT)542};543 544static const struct dcn20_opp_mask opp_mask = {545 OPP_MASK_SH_LIST_DCN20(_MASK)546};547 548static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)549{550 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);551 552 if (!opp) {553 BREAK_TO_DEBUGGER();554 return NULL;555 }556 557 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);558 return &opp->base;559}560 561#define optc_regs(id)\562 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }563 564static const struct dcn_optc_registers optc_regs[] = {565 optc_regs(0),566 optc_regs(1)567};568 569static const struct dcn_optc_shift optc_shift = {570 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)571};572 573static const struct dcn_optc_mask optc_mask = {574 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)575};576 577static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)578{579 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);580 581 if (!tgn10)582 return NULL;583 584 tgn10->base.inst = instance;585 tgn10->base.ctx = ctx;586 587 tgn10->tg_regs = &optc_regs[instance];588 tgn10->tg_shift = &optc_shift;589 tgn10->tg_mask = &optc_mask;590 591 dcn30_timing_generator_init(tgn10);592 593 return &tgn10->base;594}595 596static const struct dcn30_mpc_registers mpc_regs = {597 MPC_REG_LIST_DCN3_0(0),598 MPC_REG_LIST_DCN3_0(1),599 MPC_OUT_MUX_REG_LIST_DCN3_0(0),600 MPC_OUT_MUX_REG_LIST_DCN3_0(1),601 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,602 MPC_RMU_REG_LIST_DCN3AG(0),603 MPC_DWB_MUX_REG_LIST_DCN3_0(0),604};605 606static const struct dcn30_mpc_shift mpc_shift = {607 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)608};609 610static const struct dcn30_mpc_mask mpc_mask = {611 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)612};613 614static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)615{616 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);617 618 if (!mpc30)619 return NULL;620 621 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);622 623 return &mpc30->base;624}625 626#define dsc_regsDCN20(id)\627[id] = { DSC_REG_LIST_DCN20(id) }628 629static const struct dcn20_dsc_registers dsc_regs[] = {630 dsc_regsDCN20(0),631 dsc_regsDCN20(1)632};633 634static const struct dcn20_dsc_shift dsc_shift = {635 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)636};637 638static const struct dcn20_dsc_mask dsc_mask = {639 DSC_REG_LIST_SH_MASK_DCN20(_MASK)640};641 642static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)643{644 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);645 646 if (!dsc) {647 BREAK_TO_DEBUGGER();648 return NULL;649 }650 651 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);652 return &dsc->base;653}654 655#define dwbc_regs_dcn3(id)\656[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }657 658static const struct dcn30_dwbc_registers dwbc30_regs[] = {659 dwbc_regs_dcn3(0)660};661 662static const struct dcn30_dwbc_shift dwbc30_shift = {663 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)664};665 666static const struct dcn30_dwbc_mask dwbc30_mask = {667 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)668};669 670static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)671{672 int i;673 uint32_t pipe_count = pool->res_cap->num_dwb;674 675 for (i = 0; i < pipe_count; i++) {676 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);677 678 if (!dwbc30) {679 dm_error("DC: failed to create dwbc30!\n");680 return false;681 }682 683 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);684 685 pool->dwbc[i] = &dwbc30->base;686 }687 return true;688}689 690#define mcif_wb_regs_dcn3(id)\691[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }692 693static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {694 mcif_wb_regs_dcn3(0)695};696 697static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {698 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)699};700 701static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {702 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)703};704 705static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)706{707 int i;708 uint32_t pipe_count = pool->res_cap->num_dwb;709 710 for (i = 0; i < pipe_count; i++) {711 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);712 713 if (!mcif_wb30) {714 dm_error("DC: failed to create mcif_wb30!\n");715 return false;716 }717 718 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);719 720 pool->mcif_wb[i] = &mcif_wb30->base;721 }722 return true;723}724 725#define aux_engine_regs(id)\726[id] = {\727 AUX_COMMON_REG_LIST0(id), \728 .AUXN_IMPCAL = 0, \729 .AUXP_IMPCAL = 0, \730 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \731}732 733static const struct dce110_aux_registers aux_engine_regs[] = {734 aux_engine_regs(0),735 aux_engine_regs(1)736};737 738static const struct dce110_aux_registers_shift aux_shift = {739 DCN_AUX_MASK_SH_LIST(__SHIFT)740};741 742static const struct dce110_aux_registers_mask aux_mask = {743 DCN_AUX_MASK_SH_LIST(_MASK)744};745 746static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)747{748 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);749 750 if (!aux_engine)751 return NULL;752 753 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,754 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);755 756 return &aux_engine->base;757}758 759#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }760 761static const struct dce_i2c_registers i2c_hw_regs[] = {762 i2c_inst_regs(1),763 i2c_inst_regs(2)764};765 766static const struct dce_i2c_shift i2c_shifts = {767 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)768};769 770static const struct dce_i2c_mask i2c_masks = {771 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)772};773 774static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)775{776 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);777 778 if (!dce_i2c_hw)779 return NULL;780 781 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);782 783 return dce_i2c_hw;784}785 786static const struct encoder_feature_support link_enc_feature = {787 .max_hdmi_deep_color = COLOR_DEPTH_121212,788 .max_hdmi_pixel_clock = 600000,789 .hdmi_ycbcr420_supported = true,790 .dp_ycbcr420_supported = true,791 .fec_supported = true,792 .flags.bits.IS_HBR2_CAPABLE = true,793 .flags.bits.IS_HBR3_CAPABLE = true,794 .flags.bits.IS_TPS3_CAPABLE = true,795 .flags.bits.IS_TPS4_CAPABLE = true796};797 798#define link_regs(id, phyid)\799 [id] = {\800 LE_DCN3_REG_LIST(id), \801 UNIPHY_DCN2_REG_LIST(phyid), \802 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \803 }804 805static const struct dcn10_link_enc_registers link_enc_regs[] = {806 link_regs(0, A),807 link_regs(1, B)808};809 810static const struct dcn10_link_enc_shift le_shift = {811 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),812 DPCS_DCN2_MASK_SH_LIST(__SHIFT)813};814 815static const struct dcn10_link_enc_mask le_mask = {816 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),817 DPCS_DCN2_MASK_SH_LIST(_MASK)818};819 820#define aux_regs(id)\821 [id] = { DCN2_AUX_REG_LIST(id) }822 823static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {824 aux_regs(0),825 aux_regs(1)826};827 828#define hpd_regs(id)\829 [id] = { HPD_REG_LIST(id) }830 831static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {832 hpd_regs(0),833 hpd_regs(1)834};835 836static struct link_encoder *dcn303_link_encoder_create(837 struct dc_context *ctx,838 const struct encoder_init_data *enc_init_data)839{840 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);841 842 if (!enc20)843 return NULL;844 845 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,846 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],847 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);848 849 return &enc20->enc10.base;850}851 852static const struct dce_panel_cntl_registers panel_cntl_regs[] = {853 { DCN_PANEL_CNTL_REG_LIST() }854};855 856static const struct dce_panel_cntl_shift panel_cntl_shift = {857 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)858};859 860static const struct dce_panel_cntl_mask panel_cntl_mask = {861 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)862};863 864static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)865{866 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);867 868 if (!panel_cntl)869 return NULL;870 871 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],872 &panel_cntl_shift, &panel_cntl_mask);873 874 return &panel_cntl->base;875}876 877static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)878{879 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),880 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);881}882 883static const struct resource_create_funcs res_create_funcs = {884 .read_dce_straps = read_dce_straps,885 .create_audio = dcn303_create_audio,886 .create_stream_encoder = dcn303_stream_encoder_create,887 .create_hwseq = dcn303_hwseq_create,888};889 890static bool is_soc_bounding_box_valid(struct dc *dc)891{892 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;893 894 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))895 return true;896 897 return false;898}899 900static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)901{902 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;903 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;904 905 DC_LOGGER_INIT(dc->ctx->logger);906 907 if (!is_soc_bounding_box_valid(dc)) {908 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);909 return false;910 }911 912 loaded_ip->max_num_otg = pool->pipe_count;913 loaded_ip->max_num_dpp = pool->pipe_count;914 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;915 DC_FP_START();916 dcn20_patch_bounding_box(dc, loaded_bb);917 DC_FP_END();918 919 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {920 struct bp_soc_bb_info bb_info = { 0 };921 922 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(923 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {924 DC_FP_START();925 dcn303_fpu_init_soc_bounding_box(bb_info);926 DC_FP_END();927 }928 }929 930 return true;931}932 933static void dcn303_resource_destruct(struct resource_pool *pool)934{935 unsigned int i;936 937 for (i = 0; i < pool->stream_enc_count; i++) {938 if (pool->stream_enc[i] != NULL) {939 if (pool->stream_enc[i]->vpg != NULL) {940 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));941 pool->stream_enc[i]->vpg = NULL;942 }943 if (pool->stream_enc[i]->afmt != NULL) {944 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));945 pool->stream_enc[i]->afmt = NULL;946 }947 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));948 pool->stream_enc[i] = NULL;949 }950 }951 952 for (i = 0; i < pool->res_cap->num_dsc; i++) {953 if (pool->dscs[i] != NULL)954 dcn20_dsc_destroy(&pool->dscs[i]);955 }956 957 if (pool->mpc != NULL) {958 kfree(TO_DCN20_MPC(pool->mpc));959 pool->mpc = NULL;960 }961 962 if (pool->hubbub != NULL) {963 kfree(pool->hubbub);964 pool->hubbub = NULL;965 }966 967 for (i = 0; i < pool->pipe_count; i++) {968 if (pool->dpps[i] != NULL) {969 kfree(TO_DCN20_DPP(pool->dpps[i]));970 pool->dpps[i] = NULL;971 }972 973 if (pool->hubps[i] != NULL) {974 kfree(TO_DCN20_HUBP(pool->hubps[i]));975 pool->hubps[i] = NULL;976 }977 978 if (pool->irqs != NULL)979 dal_irq_service_destroy(&pool->irqs);980 }981 982 for (i = 0; i < pool->res_cap->num_ddc; i++) {983 if (pool->engines[i] != NULL)984 dce110_engine_destroy(&pool->engines[i]);985 if (pool->hw_i2cs[i] != NULL) {986 kfree(pool->hw_i2cs[i]);987 pool->hw_i2cs[i] = NULL;988 }989 if (pool->sw_i2cs[i] != NULL) {990 kfree(pool->sw_i2cs[i]);991 pool->sw_i2cs[i] = NULL;992 }993 }994 995 for (i = 0; i < pool->res_cap->num_opp; i++) {996 if (pool->opps[i] != NULL)997 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);998 }999 1000 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {1001 if (pool->timing_generators[i] != NULL) {1002 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));1003 pool->timing_generators[i] = NULL;1004 }1005 }1006 1007 for (i = 0; i < pool->res_cap->num_dwb; i++) {1008 if (pool->dwbc[i] != NULL) {1009 kfree(TO_DCN30_DWBC(pool->dwbc[i]));1010 pool->dwbc[i] = NULL;1011 }1012 if (pool->mcif_wb[i] != NULL) {1013 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));1014 pool->mcif_wb[i] = NULL;1015 }1016 }1017 1018 for (i = 0; i < pool->audio_count; i++) {1019 if (pool->audios[i])1020 dce_aud_destroy(&pool->audios[i]);1021 }1022 1023 for (i = 0; i < pool->clk_src_count; i++) {1024 if (pool->clock_sources[i] != NULL)1025 dcn20_clock_source_destroy(&pool->clock_sources[i]);1026 }1027 1028 if (pool->dp_clock_source != NULL)1029 dcn20_clock_source_destroy(&pool->dp_clock_source);1030 1031 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {1032 if (pool->mpc_lut[i] != NULL) {1033 dc_3dlut_func_release(pool->mpc_lut[i]);1034 pool->mpc_lut[i] = NULL;1035 }1036 if (pool->mpc_shaper[i] != NULL) {1037 dc_transfer_func_release(pool->mpc_shaper[i]);1038 pool->mpc_shaper[i] = NULL;1039 }1040 }1041 1042 for (i = 0; i < pool->pipe_count; i++) {1043 if (pool->multiple_abms[i] != NULL)1044 dce_abm_destroy(&pool->multiple_abms[i]);1045 }1046 1047 if (pool->psr != NULL)1048 dmub_psr_destroy(&pool->psr);1049 1050 if (pool->dccg != NULL)1051 dcn_dccg_destroy(&pool->dccg);1052 1053 if (pool->oem_device != NULL) {1054 struct dc *dc = pool->oem_device->ctx->dc;1055 1056 dc->link_srv->destroy_ddc_service(&pool->oem_device);1057 }1058}1059 1060static void dcn303_destroy_resource_pool(struct resource_pool **pool)1061{1062 dcn303_resource_destruct(*pool);1063 kfree(*pool);1064 *pool = NULL;1065}1066 1067static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)1068{1069 *panel_config = panel_config_defaults;1070}1071 1072void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)1073{1074 DC_FP_START();1075 dcn303_fpu_update_bw_bounding_box(dc, bw_params);1076 DC_FP_END();1077}1078 1079static struct resource_funcs dcn303_res_pool_funcs = {1080 .destroy = dcn303_destroy_resource_pool,1081 .link_enc_create = dcn303_link_encoder_create,1082 .panel_cntl_create = dcn303_panel_cntl_create,1083 .validate_bandwidth = dcn30_validate_bandwidth,1084 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,1085 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,1086 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,1087 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,1088 .release_pipe = dcn20_release_pipe,1089 .add_stream_to_ctx = dcn30_add_stream_to_ctx,1090 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1091 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1092 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,1093 .set_mcif_arb_params = dcn30_set_mcif_arb_params,1094 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1095 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,1096 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,1097 .update_bw_bounding_box = dcn303_update_bw_bounding_box,1098 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,1099 .get_panel_config_defaults = dcn303_get_panel_config_defaults,1100};1101 1102static struct dc_cap_funcs cap_funcs = {1103 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap1104};1105 1106static const struct bios_registers bios_regs = {1107 NBIO_SR(BIOS_SCRATCH_3),1108 NBIO_SR(BIOS_SCRATCH_6)1109};1110 1111static const struct dccg_registers dccg_regs = {1112 DCCG_REG_LIST_DCN3_03()1113};1114 1115static const struct dccg_shift dccg_shift = {1116 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)1117};1118 1119static const struct dccg_mask dccg_mask = {1120 DCCG_MASK_SH_LIST_DCN3_03(_MASK)1121};1122 1123#define abm_regs(id)\1124 [id] = { ABM_DCN302_REG_LIST(id) }1125 1126static const struct dce_abm_registers abm_regs[] = {1127 abm_regs(0),1128 abm_regs(1)1129};1130 1131static const struct dce_abm_shift abm_shift = {1132 ABM_MASK_SH_LIST_DCN30(__SHIFT)1133};1134 1135static const struct dce_abm_mask abm_mask = {1136 ABM_MASK_SH_LIST_DCN30(_MASK)1137};1138 1139static bool dcn303_resource_construct(1140 uint8_t num_virtual_links,1141 struct dc *dc,1142 struct resource_pool *pool)1143{1144 int i;1145 struct dc_context *ctx = dc->ctx;1146 struct irq_service_init_data init_data;1147 struct ddc_service_init_data ddc_init_data = {0};1148 1149 ctx->dc_bios->regs = &bios_regs;1150 1151 pool->res_cap = &res_cap_dcn303;1152 1153 pool->funcs = &dcn303_res_pool_funcs;1154 1155 /*************************************************1156 * Resource + asic cap harcoding *1157 *************************************************/1158 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;1159 pool->pipe_count = pool->res_cap->num_timing_generator;1160 pool->mpcc_count = pool->res_cap->num_timing_generator;1161 dc->caps.max_downscale_ratio = 600;1162 dc->caps.i2c_speed_in_khz = 100;1163 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/1164 dc->caps.max_cursor_size = 256;1165 dc->caps.min_horizontal_blanking_period = 80;1166 dc->caps.dmdata_alloc_size = 2048;1167 dc->caps.mall_size_per_mem_channel = 4;1168 /* total size = mall per channel * num channels * 1024 * 1024 */1169 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *1170 dc->ctx->dc_bios->vram_info.num_chans *1171 1024 * 1024;1172 dc->caps.cursor_cache_size =1173 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;1174 dc->caps.max_slave_planes = 1;1175 dc->caps.max_slave_yuv_planes = 1;1176 dc->caps.max_slave_rgb_planes = 1;1177 dc->caps.post_blend_color_processing = true;1178 dc->caps.force_dp_tps4_for_cp2520 = true;1179 dc->caps.extended_aux_timeout_support = true;1180 dc->caps.dmcub_support = true;1181 dc->caps.max_v_total = (1 << 15) - 1;1182 1183 /* Color pipeline capabilities */1184 dc->caps.color.dpp.dcn_arch = 1;1185 dc->caps.color.dpp.input_lut_shared = 0;1186 dc->caps.color.dpp.icsc = 1;1187 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr1188 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1189 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1190 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;1191 dc->caps.color.dpp.dgam_rom_caps.pq = 1;1192 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;1193 dc->caps.color.dpp.post_csc = 1;1194 dc->caps.color.dpp.gamma_corr = 1;1195 dc->caps.color.dpp.dgam_rom_for_yuv = 0;1196 1197 dc->caps.color.dpp.hw_3d_lut = 1;1198 dc->caps.color.dpp.ogam_ram = 1;1199 // no OGAM ROM on DCN31200 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1201 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1202 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1203 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1204 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1205 dc->caps.color.dpp.ocsc = 0;1206 1207 dc->caps.color.mpc.gamut_remap = 1;1208 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //31209 dc->caps.color.mpc.ogam_ram = 1;1210 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1211 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1212 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1213 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1214 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1215 dc->caps.color.mpc.ocsc = 1;1216 1217 dc->caps.dp_hdmi21_pcon_support = true;1218 1219 dc->config.dc_mode_clk_limit_support = true;1220 /* read VBIOS LTTPR caps */1221 if (ctx->dc_bios->funcs->get_lttpr_caps) {1222 enum bp_result bp_query_result;1223 uint8_t is_vbios_lttpr_enable = 0;1224 1225 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);1226 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;1227 }1228 1229 if (ctx->dc_bios->funcs->get_lttpr_interop) {1230 enum bp_result bp_query_result;1231 uint8_t is_vbios_interop_enabled = 0;1232 1233 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);1234 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;1235 }1236 1237 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1238 dc->debug = debug_defaults_drv;1239 1240 // Init the vm_helper1241 if (dc->vm_helper)1242 vm_helper_init(dc->vm_helper, 16);1243 1244 /*************************************************1245 * Create resources *1246 *************************************************/1247 1248 /* Clock Sources for Pixel Clock*/1249 pool->clock_sources[DCN303_CLK_SRC_PLL0] =1250 dcn303_clock_source_create(ctx, ctx->dc_bios,1251 CLOCK_SOURCE_COMBO_PHY_PLL0,1252 &clk_src_regs[0], false);1253 pool->clock_sources[DCN303_CLK_SRC_PLL1] =1254 dcn303_clock_source_create(ctx, ctx->dc_bios,1255 CLOCK_SOURCE_COMBO_PHY_PLL1,1256 &clk_src_regs[1], false);1257 1258 pool->clk_src_count = DCN303_CLK_SRC_TOTAL;1259 1260 /* todo: not reuse phy_pll registers */1261 pool->dp_clock_source =1262 dcn303_clock_source_create(ctx, ctx->dc_bios,1263 CLOCK_SOURCE_ID_DP_DTO,1264 &clk_src_regs[0], true);1265 1266 for (i = 0; i < pool->clk_src_count; i++) {1267 if (pool->clock_sources[i] == NULL) {1268 dm_error("DC: failed to create clock sources!\n");1269 BREAK_TO_DEBUGGER();1270 goto create_fail;1271 }1272 }1273 1274 /* DCCG */1275 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1276 if (pool->dccg == NULL) {1277 dm_error("DC: failed to create dccg!\n");1278 BREAK_TO_DEBUGGER();1279 goto create_fail;1280 }1281 1282 /* PP Lib and SMU interfaces */1283 init_soc_bounding_box(dc, pool);1284 1285 /* DML */1286 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);1287 1288 /* IRQ */1289 init_data.ctx = dc->ctx;1290 pool->irqs = dal_irq_service_dcn303_create(&init_data);1291 if (!pool->irqs)1292 goto create_fail;1293 1294 /* HUBBUB */1295 pool->hubbub = dcn303_hubbub_create(ctx);1296 if (pool->hubbub == NULL) {1297 BREAK_TO_DEBUGGER();1298 dm_error("DC: failed to create hubbub!\n");1299 goto create_fail;1300 }1301 1302 /* HUBPs, DPPs, OPPs and TGs */1303 for (i = 0; i < pool->pipe_count; i++) {1304 pool->hubps[i] = dcn303_hubp_create(ctx, i);1305 if (pool->hubps[i] == NULL) {1306 BREAK_TO_DEBUGGER();1307 dm_error("DC: failed to create hubps!\n");1308 goto create_fail;1309 }1310 1311 pool->dpps[i] = dcn303_dpp_create(ctx, i);1312 if (pool->dpps[i] == NULL) {1313 BREAK_TO_DEBUGGER();1314 dm_error("DC: failed to create dpps!\n");1315 goto create_fail;1316 }1317 }1318 1319 for (i = 0; i < pool->res_cap->num_opp; i++) {1320 pool->opps[i] = dcn303_opp_create(ctx, i);1321 if (pool->opps[i] == NULL) {1322 BREAK_TO_DEBUGGER();1323 dm_error("DC: failed to create output pixel processor!\n");1324 goto create_fail;1325 }1326 }1327 1328 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {1329 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);1330 if (pool->timing_generators[i] == NULL) {1331 BREAK_TO_DEBUGGER();1332 dm_error("DC: failed to create tg!\n");1333 goto create_fail;1334 }1335 }1336 pool->timing_generator_count = i;1337 1338 /* PSR */1339 pool->psr = dmub_psr_create(ctx);1340 if (pool->psr == NULL) {1341 dm_error("DC: failed to create psr!\n");1342 BREAK_TO_DEBUGGER();1343 goto create_fail;1344 }1345 1346 /* ABM */1347 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {1348 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);1349 if (pool->multiple_abms[i] == NULL) {1350 dm_error("DC: failed to create abm for pipe %d!\n", i);1351 BREAK_TO_DEBUGGER();1352 goto create_fail;1353 }1354 }1355 1356 /* MPC and DSC */1357 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);1358 if (pool->mpc == NULL) {1359 BREAK_TO_DEBUGGER();1360 dm_error("DC: failed to create mpc!\n");1361 goto create_fail;1362 }1363 1364 for (i = 0; i < pool->res_cap->num_dsc; i++) {1365 pool->dscs[i] = dcn303_dsc_create(ctx, i);1366 if (pool->dscs[i] == NULL) {1367 BREAK_TO_DEBUGGER();1368 dm_error("DC: failed to create display stream compressor %d!\n", i);1369 goto create_fail;1370 }1371 }1372 1373 /* DWB and MMHUBBUB */1374 if (!dcn303_dwbc_create(ctx, pool)) {1375 BREAK_TO_DEBUGGER();1376 dm_error("DC: failed to create dwbc!\n");1377 goto create_fail;1378 }1379 1380 if (!dcn303_mmhubbub_create(ctx, pool)) {1381 BREAK_TO_DEBUGGER();1382 dm_error("DC: failed to create mcif_wb!\n");1383 goto create_fail;1384 }1385 1386 /* AUX and I2C */1387 for (i = 0; i < pool->res_cap->num_ddc; i++) {1388 pool->engines[i] = dcn303_aux_engine_create(ctx, i);1389 if (pool->engines[i] == NULL) {1390 BREAK_TO_DEBUGGER();1391 dm_error("DC:failed to create aux engine!!\n");1392 goto create_fail;1393 }1394 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);1395 if (pool->hw_i2cs[i] == NULL) {1396 BREAK_TO_DEBUGGER();1397 dm_error("DC:failed to create hw i2c!!\n");1398 goto create_fail;1399 }1400 pool->sw_i2cs[i] = NULL;1401 }1402 1403 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */1404 if (!resource_construct(num_virtual_links, dc, pool,1405 &res_create_funcs))1406 goto create_fail;1407 1408 /* HW Sequencer and Plane caps */1409 dcn303_hw_sequencer_construct(dc);1410 1411 dc->caps.max_planes = pool->pipe_count;1412 1413 for (i = 0; i < dc->caps.max_planes; ++i)1414 dc->caps.planes[i] = plane_cap;1415 1416 dc->cap_funcs = cap_funcs;1417 1418 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {1419 ddc_init_data.ctx = dc->ctx;1420 ddc_init_data.link = NULL;1421 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;1422 ddc_init_data.id.enum_id = 0;1423 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;1424 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);1425 } else {1426 pool->oem_device = NULL;1427 }1428 1429 return true;1430 1431create_fail:1432 1433 dcn303_resource_destruct(pool);1434 1435 return false;1436}1437 1438struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)1439{1440 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);1441 1442 if (!pool)1443 return NULL;1444 1445 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))1446 return pool;1447 1448 BREAK_TO_DEBUGGER();1449 kfree(pool);1450 return NULL;1451}1452