2145 lines · c
1// SPDX-License-Identifier: MIT2/*3 * Copyright 2022 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27 28#include "dm_services.h"29#include "dc.h"30 31#include "dcn31/dcn31_init.h"32#include "dcn314/dcn314_init.h"33 34#include "resource.h"35#include "include/irq_service_interface.h"36#include "dcn314_resource.h"37 38#include "dcn20/dcn20_resource.h"39#include "dcn30/dcn30_resource.h"40#include "dcn31/dcn31_resource.h"41 42#include "dcn10/dcn10_ipp.h"43#include "dcn30/dcn30_hubbub.h"44#include "dcn31/dcn31_hubbub.h"45#include "dcn30/dcn30_mpc.h"46#include "dcn31/dcn31_hubp.h"47#include "irq/dcn31/irq_service_dcn31.h"48#include "irq/dcn314/irq_service_dcn314.h"49#include "dcn30/dcn30_dpp.h"50#include "dcn314/dcn314_optc.h"51#include "dcn20/dcn20_hwseq.h"52#include "dcn30/dcn30_hwseq.h"53#include "dce110/dce110_hwseq.h"54#include "dcn30/dcn30_opp.h"55#include "dcn20/dcn20_dsc.h"56#include "dcn30/dcn30_vpg.h"57#include "dcn30/dcn30_afmt.h"58#include "dcn31/dcn31_dio_link_encoder.h"59#include "dcn314/dcn314_dio_stream_encoder.h"60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"61#include "dcn31/dcn31_hpo_dp_link_encoder.h"62#include "dcn31/dcn31_apg.h"63#include "dcn31/dcn31_vpg.h"64#include "dcn31/dcn31_afmt.h"65#include "dce/dce_clock_source.h"66#include "dce/dce_audio.h"67#include "dce/dce_hwseq.h"68#include "clk_mgr.h"69#include "virtual/virtual_stream_encoder.h"70#include "dce110/dce110_resource.h"71#include "dml/display_mode_vba.h"72#include "dml/dcn31/dcn31_fpu.h"73#include "dml/dcn314/dcn314_fpu.h"74#include "dcn314/dcn314_dccg.h"75#include "dcn10/dcn10_resource.h"76#include "dcn31/dcn31_panel_cntl.h"77#include "dcn314/dcn314_hwseq.h"78 79#include "dcn30/dcn30_dwb.h"80#include "dcn30/dcn30_mmhubbub.h"81 82#include "dcn/dcn_3_1_4_offset.h"83#include "dcn/dcn_3_1_4_sh_mask.h"84#include "dpcs/dpcs_3_1_4_offset.h"85#include "dpcs/dpcs_3_1_4_sh_mask.h"86 87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x1088#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L89 90#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x091#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL92 93#include "reg_helper.h"94#include "dce/dmub_abm.h"95#include "dce/dmub_psr.h"96#include "dce/dmub_replay.h"97#include "dce/dce_aux.h"98#include "dce/dce_i2c.h"99#include "dml/dcn314/display_mode_vba_314.h"100#include "vm_helper.h"101#include "dcn20/dcn20_vmid.h"102 103#include "link_enc_cfg.h"104 105#define DCN_BASE__INST0_SEG1 0x000000C0106#define DCN_BASE__INST0_SEG2 0x000034C0107#define DCN_BASE__INST0_SEG3 0x00009000108 109#define NBIO_BASE__INST0_SEG1 0x00000014110 111#define MAX_INSTANCE 7112#define MAX_SEGMENT 8113 114#define regBIF_BX2_BIOS_SCRATCH_2 0x003a115#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1116#define regBIF_BX2_BIOS_SCRATCH_3 0x003b117#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1118#define regBIF_BX2_BIOS_SCRATCH_6 0x003e119#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1120 121#define DC_LOGGER \122 dc->ctx->logger123#define DC_LOGGER_INIT(logger)124 125enum dcn31_clk_src_array_id {126 DCN31_CLK_SRC_PLL0,127 DCN31_CLK_SRC_PLL1,128 DCN31_CLK_SRC_PLL2,129 DCN31_CLK_SRC_PLL3,130 DCN31_CLK_SRC_PLL4,131 DCN30_CLK_SRC_TOTAL132};133 134/* begin *********************135 * macros to expend register list macro defined in HW object header file136 */137 138/* DCN */139/* TODO awful hack. fixup dcn20_dwb.h */140#undef BASE_INNER141#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg142 143#define BASE(seg) BASE_INNER(seg)144 145#define SR(reg_name)\146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \147 reg ## reg_name148 149#define SRI(reg_name, block, id)\150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \151 reg ## block ## id ## _ ## reg_name152 153#define SRI2(reg_name, block, id)\154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \155 reg ## reg_name156 157#define SRIR(var_name, reg_name, block, id)\158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \159 reg ## block ## id ## _ ## reg_name160 161#define SRII(reg_name, block, id)\162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \163 reg ## block ## id ## _ ## reg_name164 165#define SRII_MPC_RMU(reg_name, block, id)\166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \167 reg ## block ## id ## _ ## reg_name168 169#define SRII_DWB(reg_name, temp_name, block, id)\170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \171 reg ## block ## id ## _ ## temp_name172 173#define SF_DWB2(reg_name, block, id, field_name, post_fix) \174 .field_name = reg_name ## __ ## field_name ## post_fix175 176#define DCCG_SRII(reg_name, block, id)\177 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \178 reg ## block ## id ## _ ## reg_name179 180#define VUPDATE_SRII(reg_name, block, id)\181 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \182 reg ## reg_name ## _ ## block ## id183 184/* NBIO */185#define NBIO_BASE_INNER(seg) \186 NBIO_BASE__INST0_SEG ## seg187 188#define NBIO_BASE(seg) \189 NBIO_BASE_INNER(seg)190 191#define NBIO_SR(reg_name)\192 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \193 regBIF_BX2_ ## reg_name194 195/* MMHUB */196#define MMHUB_BASE_INNER(seg) \197 MMHUB_BASE__INST0_SEG ## seg198 199#define MMHUB_BASE(seg) \200 MMHUB_BASE_INNER(seg)201 202#define MMHUB_SR(reg_name)\203 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \204 reg ## reg_name205 206/* CLOCK */207#define CLK_BASE_INNER(seg) \208 CLK_BASE__INST0_SEG ## seg209 210#define CLK_BASE(seg) \211 CLK_BASE_INNER(seg)212 213#define CLK_SRI(reg_name, block, inst)\214 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \215 reg ## block ## _ ## inst ## _ ## reg_name216 217 218static const struct bios_registers bios_regs = {219 NBIO_SR(BIOS_SCRATCH_3),220 NBIO_SR(BIOS_SCRATCH_6)221};222 223#define clk_src_regs(index, pllid)\224[index] = {\225 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\226}227 228static const struct dce110_clk_src_regs clk_src_regs[] = {229 clk_src_regs(0, A),230 clk_src_regs(1, B),231 clk_src_regs(2, C),232 clk_src_regs(3, D),233 clk_src_regs(4, E)234};235 236static const struct dce110_clk_src_shift cs_shift = {237 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)238};239 240static const struct dce110_clk_src_mask cs_mask = {241 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)242};243 244#define abm_regs(id)\245[id] = {\246 ABM_DCN302_REG_LIST(id)\247}248 249static const struct dce_abm_registers abm_regs[] = {250 abm_regs(0),251 abm_regs(1),252 abm_regs(2),253 abm_regs(3),254};255 256static const struct dce_abm_shift abm_shift = {257 ABM_MASK_SH_LIST_DCN30(__SHIFT)258};259 260static const struct dce_abm_mask abm_mask = {261 ABM_MASK_SH_LIST_DCN30(_MASK)262};263 264#define audio_regs(id)\265[id] = {\266 AUD_COMMON_REG_LIST(id)\267}268 269static const struct dce_audio_registers audio_regs[] = {270 audio_regs(0),271 audio_regs(1),272 audio_regs(2),273 audio_regs(3),274 audio_regs(4),275 audio_regs(5),276 audio_regs(6)277};278 279#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\280 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\281 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\282 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)283 284static const struct dce_audio_shift audio_shift = {285 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)286};287 288static const struct dce_audio_mask audio_mask = {289 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)290};291 292#define vpg_regs(id)\293[id] = {\294 VPG_DCN31_REG_LIST(id)\295}296 297static const struct dcn31_vpg_registers vpg_regs[] = {298 vpg_regs(0),299 vpg_regs(1),300 vpg_regs(2),301 vpg_regs(3),302 vpg_regs(4),303 vpg_regs(5),304 vpg_regs(6),305 vpg_regs(7),306 vpg_regs(8),307 vpg_regs(9),308};309 310static const struct dcn31_vpg_shift vpg_shift = {311 DCN31_VPG_MASK_SH_LIST(__SHIFT)312};313 314static const struct dcn31_vpg_mask vpg_mask = {315 DCN31_VPG_MASK_SH_LIST(_MASK)316};317 318#define afmt_regs(id)\319[id] = {\320 AFMT_DCN31_REG_LIST(id)\321}322 323static const struct dcn31_afmt_registers afmt_regs[] = {324 afmt_regs(0),325 afmt_regs(1),326 afmt_regs(2),327 afmt_regs(3),328 afmt_regs(4),329 afmt_regs(5)330};331 332static const struct dcn31_afmt_shift afmt_shift = {333 DCN31_AFMT_MASK_SH_LIST(__SHIFT)334};335 336static const struct dcn31_afmt_mask afmt_mask = {337 DCN31_AFMT_MASK_SH_LIST(_MASK)338};339 340#define apg_regs(id)\341[id] = {\342 APG_DCN31_REG_LIST(id)\343}344 345static const struct dcn31_apg_registers apg_regs[] = {346 apg_regs(0),347 apg_regs(1),348 apg_regs(2),349 apg_regs(3)350};351 352static const struct dcn31_apg_shift apg_shift = {353 DCN31_APG_MASK_SH_LIST(__SHIFT)354};355 356static const struct dcn31_apg_mask apg_mask = {357 DCN31_APG_MASK_SH_LIST(_MASK)358};359 360#define stream_enc_regs(id)\361[id] = {\362 SE_DCN314_REG_LIST(id)\363}364 365static const struct dcn10_stream_enc_registers stream_enc_regs[] = {366 stream_enc_regs(0),367 stream_enc_regs(1),368 stream_enc_regs(2),369 stream_enc_regs(3),370 stream_enc_regs(4)371};372 373static const struct dcn10_stream_encoder_shift se_shift = {374 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)375};376 377static const struct dcn10_stream_encoder_mask se_mask = {378 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)379};380 381 382#define aux_regs(id)\383[id] = {\384 DCN2_AUX_REG_LIST(id)\385}386 387static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {388 aux_regs(0),389 aux_regs(1),390 aux_regs(2),391 aux_regs(3),392 aux_regs(4)393};394 395#define hpd_regs(id)\396[id] = {\397 HPD_REG_LIST(id)\398}399 400static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {401 hpd_regs(0),402 hpd_regs(1),403 hpd_regs(2),404 hpd_regs(3),405 hpd_regs(4)406};407 408#define link_regs(id, phyid)\409[id] = {\410 LE_DCN31_REG_LIST(id), \411 UNIPHY_DCN2_REG_LIST(phyid), \412}413 414static const struct dce110_aux_registers_shift aux_shift = {415 DCN_AUX_MASK_SH_LIST(__SHIFT)416};417 418static const struct dce110_aux_registers_mask aux_mask = {419 DCN_AUX_MASK_SH_LIST(_MASK)420};421 422static const struct dcn10_link_enc_registers link_enc_regs[] = {423 link_regs(0, A),424 link_regs(1, B),425 link_regs(2, C),426 link_regs(3, D),427 link_regs(4, E)428};429 430static const struct dcn10_link_enc_shift le_shift = {431 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),432 DPCS_DCN31_MASK_SH_LIST(__SHIFT)433};434 435static const struct dcn10_link_enc_mask le_mask = {436 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),437 DPCS_DCN31_MASK_SH_LIST(_MASK)438};439 440#define hpo_dp_stream_encoder_reg_list(id)\441[id] = {\442 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\443}444 445static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {446 hpo_dp_stream_encoder_reg_list(0),447 hpo_dp_stream_encoder_reg_list(1),448 hpo_dp_stream_encoder_reg_list(2),449 hpo_dp_stream_encoder_reg_list(3)450};451 452static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {453 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)454};455 456static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {457 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)458};459 460 461#define hpo_dp_link_encoder_reg_list(id)\462[id] = {\463 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\464 DCN3_1_RDPCSTX_REG_LIST(0),\465 DCN3_1_RDPCSTX_REG_LIST(1),\466 DCN3_1_RDPCSTX_REG_LIST(2),\467}468 469static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {470 hpo_dp_link_encoder_reg_list(0),471 hpo_dp_link_encoder_reg_list(1),472};473 474static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {475 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)476};477 478static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {479 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)480};481 482#define dpp_regs(id)\483[id] = {\484 DPP_REG_LIST_DCN30(id),\485}486 487static const struct dcn3_dpp_registers dpp_regs[] = {488 dpp_regs(0),489 dpp_regs(1),490 dpp_regs(2),491 dpp_regs(3)492};493 494static const struct dcn3_dpp_shift tf_shift = {495 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)496};497 498static const struct dcn3_dpp_mask tf_mask = {499 DPP_REG_LIST_SH_MASK_DCN30(_MASK)500};501 502#define opp_regs(id)\503[id] = {\504 OPP_REG_LIST_DCN30(id),\505}506 507static const struct dcn20_opp_registers opp_regs[] = {508 opp_regs(0),509 opp_regs(1),510 opp_regs(2),511 opp_regs(3)512};513 514static const struct dcn20_opp_shift opp_shift = {515 OPP_MASK_SH_LIST_DCN20(__SHIFT)516};517 518static const struct dcn20_opp_mask opp_mask = {519 OPP_MASK_SH_LIST_DCN20(_MASK)520};521 522#define aux_engine_regs(id)\523[id] = {\524 AUX_COMMON_REG_LIST0(id), \525 .AUXN_IMPCAL = 0, \526 .AUXP_IMPCAL = 0, \527 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \528}529 530static const struct dce110_aux_registers aux_engine_regs[] = {531 aux_engine_regs(0),532 aux_engine_regs(1),533 aux_engine_regs(2),534 aux_engine_regs(3),535 aux_engine_regs(4)536};537 538#define dwbc_regs_dcn3(id)\539[id] = {\540 DWBC_COMMON_REG_LIST_DCN30(id),\541}542 543static const struct dcn30_dwbc_registers dwbc30_regs[] = {544 dwbc_regs_dcn3(0),545};546 547static const struct dcn30_dwbc_shift dwbc30_shift = {548 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)549};550 551static const struct dcn30_dwbc_mask dwbc30_mask = {552 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)553};554 555#define mcif_wb_regs_dcn3(id)\556[id] = {\557 MCIF_WB_COMMON_REG_LIST_DCN30(id),\558}559 560static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {561 mcif_wb_regs_dcn3(0)562};563 564static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {565 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)566};567 568static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {569 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)570};571 572#define dsc_regsDCN314(id)\573[id] = {\574 DSC_REG_LIST_DCN20(id)\575}576 577static const struct dcn20_dsc_registers dsc_regs[] = {578 dsc_regsDCN314(0),579 dsc_regsDCN314(1),580 dsc_regsDCN314(2),581 dsc_regsDCN314(3)582};583 584static const struct dcn20_dsc_shift dsc_shift = {585 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)586};587 588static const struct dcn20_dsc_mask dsc_mask = {589 DSC_REG_LIST_SH_MASK_DCN20(_MASK)590};591 592static const struct dcn30_mpc_registers mpc_regs = {593 MPC_REG_LIST_DCN3_0(0),594 MPC_REG_LIST_DCN3_0(1),595 MPC_REG_LIST_DCN3_0(2),596 MPC_REG_LIST_DCN3_0(3),597 MPC_OUT_MUX_REG_LIST_DCN3_0(0),598 MPC_OUT_MUX_REG_LIST_DCN3_0(1),599 MPC_OUT_MUX_REG_LIST_DCN3_0(2),600 MPC_OUT_MUX_REG_LIST_DCN3_0(3),601 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,602 MPC_RMU_REG_LIST_DCN3AG(0),603 MPC_RMU_REG_LIST_DCN3AG(1),604 //MPC_RMU_REG_LIST_DCN3AG(2),605 MPC_DWB_MUX_REG_LIST_DCN3_0(0),606};607 608static const struct dcn30_mpc_shift mpc_shift = {609 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)610};611 612static const struct dcn30_mpc_mask mpc_mask = {613 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)614};615 616#define optc_regs(id)\617[id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}618 619static const struct dcn_optc_registers optc_regs[] = {620 optc_regs(0),621 optc_regs(1),622 optc_regs(2),623 optc_regs(3)624};625 626static const struct dcn_optc_shift optc_shift = {627 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)628};629 630static const struct dcn_optc_mask optc_mask = {631 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)632};633 634#define hubp_regs(id)\635[id] = {\636 HUBP_REG_LIST_DCN30(id)\637}638 639static const struct dcn_hubp2_registers hubp_regs[] = {640 hubp_regs(0),641 hubp_regs(1),642 hubp_regs(2),643 hubp_regs(3)644};645 646 647static const struct dcn_hubp2_shift hubp_shift = {648 HUBP_MASK_SH_LIST_DCN31(__SHIFT)649};650 651static const struct dcn_hubp2_mask hubp_mask = {652 HUBP_MASK_SH_LIST_DCN31(_MASK)653};654static const struct dcn_hubbub_registers hubbub_reg = {655 HUBBUB_REG_LIST_DCN31(0)656};657 658static const struct dcn_hubbub_shift hubbub_shift = {659 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)660};661 662static const struct dcn_hubbub_mask hubbub_mask = {663 HUBBUB_MASK_SH_LIST_DCN31(_MASK)664};665 666static const struct dccg_registers dccg_regs = {667 DCCG_REG_LIST_DCN314()668};669 670static const struct dccg_shift dccg_shift = {671 DCCG_MASK_SH_LIST_DCN314(__SHIFT)672};673 674static const struct dccg_mask dccg_mask = {675 DCCG_MASK_SH_LIST_DCN314(_MASK)676};677 678 679#define SRII2(reg_name_pre, reg_name_post, id)\680 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \681 ## id ## _ ## reg_name_post ## _BASE_IDX) + \682 reg ## reg_name_pre ## id ## _ ## reg_name_post683 684 685#define HWSEQ_DCN31_REG_LIST()\686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \688 SR(DIO_MEM_PWR_CTRL), \689 SR(ODM_MEM_PWR_CTRL3), \690 SR(DMU_MEM_PWR_CNTL), \691 SR(MMHUBBUB_MEM_PWR_CNTL), \692 SR(DCCG_GATE_DISABLE_CNTL), \693 SR(DCCG_GATE_DISABLE_CNTL2), \694 SR(DCFCLK_CNTL),\695 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \696 SRII(PIXEL_RATE_CNTL, OTG, 0), \697 SRII(PIXEL_RATE_CNTL, OTG, 1),\698 SRII(PIXEL_RATE_CNTL, OTG, 2),\699 SRII(PIXEL_RATE_CNTL, OTG, 3),\700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\704 SR(MICROSECOND_TIME_BASE_DIV), \705 SR(MILLISECOND_TIME_BASE_DIV), \706 SR(DISPCLK_FREQ_CHANGE_CNTL), \707 SR(RBBMIF_TIMEOUT_DIS), \708 SR(RBBMIF_TIMEOUT_DIS_2), \709 SR(DCHUBBUB_CRC_CTRL), \710 SR(DPP_TOP0_DPP_CRC_CTRL), \711 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \712 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \713 SR(MPC_CRC_CTRL), \714 SR(MPC_CRC_RESULT_GB), \715 SR(MPC_CRC_RESULT_C), \716 SR(MPC_CRC_RESULT_AR), \717 SR(DOMAIN0_PG_CONFIG), \718 SR(DOMAIN1_PG_CONFIG), \719 SR(DOMAIN2_PG_CONFIG), \720 SR(DOMAIN3_PG_CONFIG), \721 SR(DOMAIN16_PG_CONFIG), \722 SR(DOMAIN17_PG_CONFIG), \723 SR(DOMAIN18_PG_CONFIG), \724 SR(DOMAIN19_PG_CONFIG), \725 SR(DOMAIN0_PG_STATUS), \726 SR(DOMAIN1_PG_STATUS), \727 SR(DOMAIN2_PG_STATUS), \728 SR(DOMAIN3_PG_STATUS), \729 SR(DOMAIN16_PG_STATUS), \730 SR(DOMAIN17_PG_STATUS), \731 SR(DOMAIN18_PG_STATUS), \732 SR(DOMAIN19_PG_STATUS), \733 SR(D1VGA_CONTROL), \734 SR(D2VGA_CONTROL), \735 SR(D3VGA_CONTROL), \736 SR(D4VGA_CONTROL), \737 SR(D5VGA_CONTROL), \738 SR(D6VGA_CONTROL), \739 SR(DC_IP_REQUEST_CNTL), \740 SR(AZALIA_AUDIO_DTO), \741 SR(AZALIA_CONTROLLER_CLOCK_GATING), \742 SR(HPO_TOP_HW_CONTROL)743 744static const struct dce_hwseq_registers hwseq_reg = {745 HWSEQ_DCN31_REG_LIST()746};747 748#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\749 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \750 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \751 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \752 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \753 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \754 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \755 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \756 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \757 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \758 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \759 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \760 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \761 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \762 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \763 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \764 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \765 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \766 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \767 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \768 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \769 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \770 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \771 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \772 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \773 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \774 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \775 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \776 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \777 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \778 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \779 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \780 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \781 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \782 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \783 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \784 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)785 786static const struct dce_hwseq_shift hwseq_shift = {787 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)788};789 790static const struct dce_hwseq_mask hwseq_mask = {791 HWSEQ_DCN31_MASK_SH_LIST(_MASK)792};793#define vmid_regs(id)\794[id] = {\795 DCN20_VMID_REG_LIST(id)\796}797 798static const struct dcn_vmid_registers vmid_regs[] = {799 vmid_regs(0),800 vmid_regs(1),801 vmid_regs(2),802 vmid_regs(3),803 vmid_regs(4),804 vmid_regs(5),805 vmid_regs(6),806 vmid_regs(7),807 vmid_regs(8),808 vmid_regs(9),809 vmid_regs(10),810 vmid_regs(11),811 vmid_regs(12),812 vmid_regs(13),813 vmid_regs(14),814 vmid_regs(15)815};816 817static const struct dcn20_vmid_shift vmid_shifts = {818 DCN20_VMID_MASK_SH_LIST(__SHIFT)819};820 821static const struct dcn20_vmid_mask vmid_masks = {822 DCN20_VMID_MASK_SH_LIST(_MASK)823};824 825static const struct resource_caps res_cap_dcn314 = {826 .num_timing_generator = 4,827 .num_opp = 4,828 .num_video_plane = 4,829 .num_audio = 5,830 .num_stream_encoder = 5,831 .num_dig_link_enc = 5,832 .num_hpo_dp_stream_encoder = 4,833 .num_hpo_dp_link_encoder = 2,834 .num_pll = 5,835 .num_dwb = 1,836 .num_ddc = 5,837 .num_vmid = 16,838 .num_mpc_3dlut = 2,839 .num_dsc = 4,840};841 842static const struct dc_plane_cap plane_cap = {843 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,844 .per_pixel_alpha = true,845 846 .pixel_format_support = {847 .argb8888 = true,848 .nv12 = true,849 .fp16 = true,850 .p010 = true,851 .ayuv = false,852 },853 854 .max_upscale_factor = {855 .argb8888 = 16000,856 .nv12 = 16000,857 .fp16 = 16000858 },859 860 // 6:1 downscaling ratio: 1000/6 = 166.666861 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250862 .max_downscale_factor = {863 .argb8888 = 250,864 .nv12 = 167,865 .fp16 = 167866 },867 64,868 64869};870 871static const struct dc_debug_options debug_defaults_drv = {872 .disable_z10 = false,873 .enable_z9_disable_interface = true,874 .minimum_z8_residency_time = 2100,875 .psr_skip_crtc_disable = true,876 .replay_skip_crtc_disabled = true,877 .disable_dmcu = true,878 .force_abm_enable = false,879 .timing_trace = false,880 .clock_trace = true,881 .disable_dpp_power_gate = false,882 .disable_hubp_power_gate = false,883 .disable_pplib_clock_request = false,884 .pipe_split_policy = MPC_SPLIT_DYNAMIC,885 .force_single_disp_pipe_split = false,886 .disable_dcc = DCC_ENABLE,887 .vsr_support = true,888 .performance_trace = false,889 .max_downscale_src_width = 4096,/*upto true 4k*/890 .disable_pplib_wm_range = false,891 .scl_reset_length10 = true,892 .sanity_checks = true,893 .underflow_assert_delay_us = 0xFFFFFFFF,894 .dwb_fi_phase = -1, // -1 = disable,895 .dmub_command_table = true,896 .pstate_enabled = true,897 .use_max_lb = true,898 .enable_mem_low_power = {899 .bits = {900 .vga = true,901 .i2c = true,902 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled903 .dscl = true,904 .cm = true,905 .mpc = true,906 .optc = true,907 .vpg = true,908 .afmt = true,909 }910 },911 912 .root_clock_optimization = {913 .bits = {914 .dpp = true,915 .dsc = true,916 .hdmistream = true,917 .hdmichar = true,918 .dpstream = true,919 .symclk32_se = false,920 .symclk32_le = true,921 .symclk_fe = true,922 .physymclk = true,923 .dpiasymclk = true,924 }925 },926 927 .seamless_boot_odm_combine = true,928 .enable_legacy_fast_update = true,929 .using_dml2 = false,930};931 932static const struct dc_panel_config panel_config_defaults = {933 .psr = {934 .disable_psr = false,935 .disallow_psrsu = false,936 .disallow_replay = false,937 },938 .ilr = {939 .optimize_edp_link_rate = true,940 },941};942 943static void dcn31_dpp_destroy(struct dpp **dpp)944{945 kfree(TO_DCN20_DPP(*dpp));946 *dpp = NULL;947}948 949static struct dpp *dcn31_dpp_create(950 struct dc_context *ctx,951 uint32_t inst)952{953 struct dcn3_dpp *dpp =954 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);955 956 if (!dpp)957 return NULL;958 959 if (dpp3_construct(dpp, ctx, inst,960 &dpp_regs[inst], &tf_shift, &tf_mask))961 return &dpp->base;962 963 BREAK_TO_DEBUGGER();964 kfree(dpp);965 return NULL;966}967 968static struct output_pixel_processor *dcn31_opp_create(969 struct dc_context *ctx, uint32_t inst)970{971 struct dcn20_opp *opp =972 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);973 974 if (!opp) {975 BREAK_TO_DEBUGGER();976 return NULL;977 }978 979 dcn20_opp_construct(opp, ctx, inst,980 &opp_regs[inst], &opp_shift, &opp_mask);981 return &opp->base;982}983 984static struct dce_aux *dcn31_aux_engine_create(985 struct dc_context *ctx,986 uint32_t inst)987{988 struct aux_engine_dce110 *aux_engine =989 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);990 991 if (!aux_engine)992 return NULL;993 994 dce110_aux_engine_construct(aux_engine, ctx, inst,995 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,996 &aux_engine_regs[inst],997 &aux_mask,998 &aux_shift,999 ctx->dc->caps.extended_aux_timeout_support);1000 1001 return &aux_engine->base;1002}1003#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }1004 1005static const struct dce_i2c_registers i2c_hw_regs[] = {1006 i2c_inst_regs(1),1007 i2c_inst_regs(2),1008 i2c_inst_regs(3),1009 i2c_inst_regs(4),1010 i2c_inst_regs(5),1011};1012 1013static const struct dce_i2c_shift i2c_shifts = {1014 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)1015};1016 1017static const struct dce_i2c_mask i2c_masks = {1018 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)1019};1020 1021/* ========================================================== */1022 1023/*1024 * DPIA index | Preferred Encoder | Host Router1025 * 0 | C | 01026 * 1 | First Available | 01027 * 2 | D | 11028 * 3 | First Available | 11029 */1030/* ========================================================== */1031static const enum engine_id dpia_to_preferred_enc_id_table[] = {1032 ENGINE_ID_DIGC,1033 ENGINE_ID_DIGC,1034 ENGINE_ID_DIGD,1035 ENGINE_ID_DIGD1036};1037 1038static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)1039{1040 return dpia_to_preferred_enc_id_table[dpia_index];1041}1042 1043static struct dce_i2c_hw *dcn31_i2c_hw_create(1044 struct dc_context *ctx,1045 uint32_t inst)1046{1047 struct dce_i2c_hw *dce_i2c_hw =1048 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);1049 1050 if (!dce_i2c_hw)1051 return NULL;1052 1053 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,1054 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);1055 1056 return dce_i2c_hw;1057}1058static struct mpc *dcn31_mpc_create(1059 struct dc_context *ctx,1060 int num_mpcc,1061 int num_rmu)1062{1063 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),1064 GFP_KERNEL);1065 1066 if (!mpc30)1067 return NULL;1068 1069 dcn30_mpc_construct(mpc30, ctx,1070 &mpc_regs,1071 &mpc_shift,1072 &mpc_mask,1073 num_mpcc,1074 num_rmu);1075 1076 return &mpc30->base;1077}1078 1079static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)1080{1081 int i;1082 1083 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),1084 GFP_KERNEL);1085 1086 if (!hubbub3)1087 return NULL;1088 1089 hubbub31_construct(hubbub3, ctx,1090 &hubbub_reg,1091 &hubbub_shift,1092 &hubbub_mask,1093 dcn3_14_ip.det_buffer_size_kbytes,1094 dcn3_14_ip.pixel_chunk_size_kbytes,1095 dcn3_14_ip.config_return_buffer_size_in_kbytes);1096 1097 1098 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {1099 struct dcn20_vmid *vmid = &hubbub3->vmid[i];1100 1101 vmid->ctx = ctx;1102 1103 vmid->regs = &vmid_regs[i];1104 vmid->shifts = &vmid_shifts;1105 vmid->masks = &vmid_masks;1106 }1107 1108 return &hubbub3->base;1109}1110 1111static struct timing_generator *dcn31_timing_generator_create(1112 struct dc_context *ctx,1113 uint32_t instance)1114{1115 struct optc *tgn10 =1116 kzalloc(sizeof(struct optc), GFP_KERNEL);1117 1118 if (!tgn10)1119 return NULL;1120 1121 tgn10->base.inst = instance;1122 tgn10->base.ctx = ctx;1123 1124 tgn10->tg_regs = &optc_regs[instance];1125 tgn10->tg_shift = &optc_shift;1126 tgn10->tg_mask = &optc_mask;1127 1128 dcn314_timing_generator_init(tgn10);1129 1130 return &tgn10->base;1131}1132 1133static const struct encoder_feature_support link_enc_feature = {1134 .max_hdmi_deep_color = COLOR_DEPTH_121212,1135 .max_hdmi_pixel_clock = 600000,1136 .hdmi_ycbcr420_supported = true,1137 .dp_ycbcr420_supported = true,1138 .fec_supported = true,1139 .flags.bits.IS_HBR2_CAPABLE = true,1140 .flags.bits.IS_HBR3_CAPABLE = true,1141 .flags.bits.IS_TPS3_CAPABLE = true,1142 .flags.bits.IS_TPS4_CAPABLE = true1143};1144 1145static struct link_encoder *dcn31_link_encoder_create(1146 struct dc_context *ctx,1147 const struct encoder_init_data *enc_init_data)1148{1149 struct dcn20_link_encoder *enc20 =1150 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1151 1152 if (!enc20)1153 return NULL;1154 1155 dcn31_link_encoder_construct(enc20,1156 enc_init_data,1157 &link_enc_feature,1158 &link_enc_regs[enc_init_data->transmitter],1159 &link_enc_aux_regs[enc_init_data->channel - 1],1160 &link_enc_hpd_regs[enc_init_data->hpd_source],1161 &le_shift,1162 &le_mask);1163 1164 return &enc20->enc10.base;1165}1166 1167/* Create a minimal link encoder object not associated with a particular1168 * physical connector.1169 * resource_funcs.link_enc_create_minimal1170 */1171static struct link_encoder *dcn31_link_enc_create_minimal(1172 struct dc_context *ctx, enum engine_id eng_id)1173{1174 struct dcn20_link_encoder *enc20;1175 1176 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)1177 return NULL;1178 1179 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1180 if (!enc20)1181 return NULL;1182 1183 dcn31_link_encoder_construct_minimal(1184 enc20,1185 ctx,1186 &link_enc_feature,1187 &link_enc_regs[eng_id - ENGINE_ID_DIGA],1188 eng_id);1189 1190 return &enc20->enc10.base;1191}1192 1193static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)1194{1195 struct dcn31_panel_cntl *panel_cntl =1196 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);1197 1198 if (!panel_cntl)1199 return NULL;1200 1201 dcn31_panel_cntl_construct(panel_cntl, init_data);1202 1203 return &panel_cntl->base;1204}1205 1206static void read_dce_straps(1207 struct dc_context *ctx,1208 struct resource_straps *straps)1209{1210 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),1211 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);1212 1213}1214 1215static struct audio *dcn31_create_audio(1216 struct dc_context *ctx, unsigned int inst)1217{1218 return dce_audio_create(ctx, inst,1219 &audio_regs[inst], &audio_shift, &audio_mask);1220}1221 1222static struct vpg *dcn31_vpg_create(1223 struct dc_context *ctx,1224 uint32_t inst)1225{1226 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);1227 1228 if (!vpg31)1229 return NULL;1230 1231 vpg31_construct(vpg31, ctx, inst,1232 &vpg_regs[inst],1233 &vpg_shift,1234 &vpg_mask);1235 1236 return &vpg31->base;1237}1238 1239static struct afmt *dcn31_afmt_create(1240 struct dc_context *ctx,1241 uint32_t inst)1242{1243 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);1244 1245 if (!afmt31)1246 return NULL;1247 1248 afmt31_construct(afmt31, ctx, inst,1249 &afmt_regs[inst],1250 &afmt_shift,1251 &afmt_mask);1252 1253 // Light sleep by default, no need to power down here1254 1255 return &afmt31->base;1256}1257 1258static struct apg *dcn31_apg_create(1259 struct dc_context *ctx,1260 uint32_t inst)1261{1262 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);1263 1264 if (!apg31)1265 return NULL;1266 1267 apg31_construct(apg31, ctx, inst,1268 &apg_regs[inst],1269 &apg_shift,1270 &apg_mask);1271 1272 return &apg31->base;1273}1274 1275static struct stream_encoder *dcn314_stream_encoder_create(1276 enum engine_id eng_id,1277 struct dc_context *ctx)1278{1279 struct dcn10_stream_encoder *enc1;1280 struct vpg *vpg;1281 struct afmt *afmt;1282 int vpg_inst;1283 int afmt_inst;1284 1285 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */1286 if (eng_id < ENGINE_ID_DIGF) {1287 vpg_inst = eng_id;1288 afmt_inst = eng_id;1289 } else1290 return NULL;1291 1292 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1293 vpg = dcn31_vpg_create(ctx, vpg_inst);1294 afmt = dcn31_afmt_create(ctx, afmt_inst);1295 1296 if (!enc1 || !vpg || !afmt) {1297 kfree(enc1);1298 kfree(vpg);1299 kfree(afmt);1300 return NULL;1301 }1302 1303 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,1304 eng_id, vpg, afmt,1305 &stream_enc_regs[eng_id],1306 &se_shift, &se_mask);1307 1308 return &enc1->base;1309}1310 1311static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(1312 enum engine_id eng_id,1313 struct dc_context *ctx)1314{1315 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;1316 struct vpg *vpg;1317 struct apg *apg;1318 uint32_t hpo_dp_inst;1319 uint32_t vpg_inst;1320 uint32_t apg_inst;1321 1322 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));1323 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;1324 1325 /* Mapping of VPG register blocks to HPO DP block instance:1326 * VPG[6] -> HPO_DP[0]1327 * VPG[7] -> HPO_DP[1]1328 * VPG[8] -> HPO_DP[2]1329 * VPG[9] -> HPO_DP[3]1330 */1331 //Uses offset index 5-8, but actually maps to vpg_inst 6-91332 vpg_inst = hpo_dp_inst + 5;1333 1334 /* Mapping of APG register blocks to HPO DP block instance:1335 * APG[0] -> HPO_DP[0]1336 * APG[1] -> HPO_DP[1]1337 * APG[2] -> HPO_DP[2]1338 * APG[3] -> HPO_DP[3]1339 */1340 apg_inst = hpo_dp_inst;1341 1342 /* allocate HPO stream encoder and create VPG sub-block */1343 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);1344 vpg = dcn31_vpg_create(ctx, vpg_inst);1345 apg = dcn31_apg_create(ctx, apg_inst);1346 1347 if (!hpo_dp_enc31 || !vpg || !apg) {1348 kfree(hpo_dp_enc31);1349 kfree(vpg);1350 kfree(apg);1351 return NULL;1352 }1353 1354 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,1355 hpo_dp_inst, eng_id, vpg, apg,1356 &hpo_dp_stream_enc_regs[hpo_dp_inst],1357 &hpo_dp_se_shift, &hpo_dp_se_mask);1358 1359 return &hpo_dp_enc31->base;1360}1361 1362static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(1363 uint8_t inst,1364 struct dc_context *ctx)1365{1366 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;1367 1368 /* allocate HPO link encoder */1369 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);1370 if (!hpo_dp_enc31)1371 return NULL; /* out of memory */1372 1373 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,1374 &hpo_dp_link_enc_regs[inst],1375 &hpo_dp_le_shift, &hpo_dp_le_mask);1376 1377 return &hpo_dp_enc31->base;1378}1379 1380static struct dce_hwseq *dcn314_hwseq_create(1381 struct dc_context *ctx)1382{1383 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1384 1385 if (hws) {1386 hws->ctx = ctx;1387 hws->regs = &hwseq_reg;1388 hws->shifts = &hwseq_shift;1389 hws->masks = &hwseq_mask;1390 }1391 return hws;1392}1393static const struct resource_create_funcs res_create_funcs = {1394 .read_dce_straps = read_dce_straps,1395 .create_audio = dcn31_create_audio,1396 .create_stream_encoder = dcn314_stream_encoder_create,1397 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,1398 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,1399 .create_hwseq = dcn314_hwseq_create,1400};1401 1402static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)1403{1404 unsigned int i;1405 1406 for (i = 0; i < pool->base.stream_enc_count; i++) {1407 if (pool->base.stream_enc[i] != NULL) {1408 if (pool->base.stream_enc[i]->vpg != NULL) {1409 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));1410 pool->base.stream_enc[i]->vpg = NULL;1411 }1412 if (pool->base.stream_enc[i]->afmt != NULL) {1413 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));1414 pool->base.stream_enc[i]->afmt = NULL;1415 }1416 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));1417 pool->base.stream_enc[i] = NULL;1418 }1419 }1420 1421 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {1422 if (pool->base.hpo_dp_stream_enc[i] != NULL) {1423 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {1424 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));1425 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;1426 }1427 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {1428 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));1429 pool->base.hpo_dp_stream_enc[i]->apg = NULL;1430 }1431 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));1432 pool->base.hpo_dp_stream_enc[i] = NULL;1433 }1434 }1435 1436 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {1437 if (pool->base.hpo_dp_link_enc[i] != NULL) {1438 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));1439 pool->base.hpo_dp_link_enc[i] = NULL;1440 }1441 }1442 1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1444 if (pool->base.dscs[i] != NULL)1445 dcn20_dsc_destroy(&pool->base.dscs[i]);1446 }1447 1448 if (pool->base.mpc != NULL) {1449 kfree(TO_DCN20_MPC(pool->base.mpc));1450 pool->base.mpc = NULL;1451 }1452 if (pool->base.hubbub != NULL) {1453 kfree(pool->base.hubbub);1454 pool->base.hubbub = NULL;1455 }1456 for (i = 0; i < pool->base.pipe_count; i++) {1457 if (pool->base.dpps[i] != NULL)1458 dcn31_dpp_destroy(&pool->base.dpps[i]);1459 1460 if (pool->base.ipps[i] != NULL)1461 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);1462 1463 if (pool->base.hubps[i] != NULL) {1464 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));1465 pool->base.hubps[i] = NULL;1466 }1467 1468 if (pool->base.irqs != NULL)1469 dal_irq_service_destroy(&pool->base.irqs);1470 }1471 1472 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1473 if (pool->base.engines[i] != NULL)1474 dce110_engine_destroy(&pool->base.engines[i]);1475 if (pool->base.hw_i2cs[i] != NULL) {1476 kfree(pool->base.hw_i2cs[i]);1477 pool->base.hw_i2cs[i] = NULL;1478 }1479 if (pool->base.sw_i2cs[i] != NULL) {1480 kfree(pool->base.sw_i2cs[i]);1481 pool->base.sw_i2cs[i] = NULL;1482 }1483 }1484 1485 for (i = 0; i < pool->base.res_cap->num_opp; i++) {1486 if (pool->base.opps[i] != NULL)1487 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);1488 }1489 1490 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1491 if (pool->base.timing_generators[i] != NULL) {1492 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));1493 pool->base.timing_generators[i] = NULL;1494 }1495 }1496 1497 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {1498 if (pool->base.dwbc[i] != NULL) {1499 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));1500 pool->base.dwbc[i] = NULL;1501 }1502 if (pool->base.mcif_wb[i] != NULL) {1503 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));1504 pool->base.mcif_wb[i] = NULL;1505 }1506 }1507 1508 for (i = 0; i < pool->base.audio_count; i++) {1509 if (pool->base.audios[i])1510 dce_aud_destroy(&pool->base.audios[i]);1511 }1512 1513 for (i = 0; i < pool->base.clk_src_count; i++) {1514 if (pool->base.clock_sources[i] != NULL) {1515 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);1516 pool->base.clock_sources[i] = NULL;1517 }1518 }1519 1520 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {1521 if (pool->base.mpc_lut[i] != NULL) {1522 dc_3dlut_func_release(pool->base.mpc_lut[i]);1523 pool->base.mpc_lut[i] = NULL;1524 }1525 if (pool->base.mpc_shaper[i] != NULL) {1526 dc_transfer_func_release(pool->base.mpc_shaper[i]);1527 pool->base.mpc_shaper[i] = NULL;1528 }1529 }1530 1531 if (pool->base.dp_clock_source != NULL) {1532 dcn20_clock_source_destroy(&pool->base.dp_clock_source);1533 pool->base.dp_clock_source = NULL;1534 }1535 1536 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1537 if (pool->base.multiple_abms[i] != NULL)1538 dce_abm_destroy(&pool->base.multiple_abms[i]);1539 }1540 1541 if (pool->base.psr != NULL)1542 dmub_psr_destroy(&pool->base.psr);1543 1544 if (pool->base.replay != NULL)1545 dmub_replay_destroy(&pool->base.replay);1546 1547 if (pool->base.dccg != NULL)1548 dcn_dccg_destroy(&pool->base.dccg);1549}1550 1551static struct hubp *dcn31_hubp_create(1552 struct dc_context *ctx,1553 uint32_t inst)1554{1555 struct dcn20_hubp *hubp2 =1556 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);1557 1558 if (!hubp2)1559 return NULL;1560 1561 if (hubp31_construct(hubp2, ctx, inst,1562 &hubp_regs[inst], &hubp_shift, &hubp_mask))1563 return &hubp2->base;1564 1565 BREAK_TO_DEBUGGER();1566 kfree(hubp2);1567 return NULL;1568}1569 1570static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)1571{1572 int i;1573 uint32_t pipe_count = pool->res_cap->num_dwb;1574 1575 for (i = 0; i < pipe_count; i++) {1576 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),1577 GFP_KERNEL);1578 1579 if (!dwbc30) {1580 dm_error("DC: failed to create dwbc30!\n");1581 return false;1582 }1583 1584 dcn30_dwbc_construct(dwbc30, ctx,1585 &dwbc30_regs[i],1586 &dwbc30_shift,1587 &dwbc30_mask,1588 i);1589 1590 pool->dwbc[i] = &dwbc30->base;1591 }1592 return true;1593}1594 1595static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)1596{1597 int i;1598 uint32_t pipe_count = pool->res_cap->num_dwb;1599 1600 for (i = 0; i < pipe_count; i++) {1601 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),1602 GFP_KERNEL);1603 1604 if (!mcif_wb30) {1605 dm_error("DC: failed to create mcif_wb30!\n");1606 return false;1607 }1608 1609 dcn30_mmhubbub_construct(mcif_wb30, ctx,1610 &mcif_wb30_regs[i],1611 &mcif_wb30_shift,1612 &mcif_wb30_mask,1613 i);1614 1615 pool->mcif_wb[i] = &mcif_wb30->base;1616 }1617 return true;1618}1619 1620static struct display_stream_compressor *dcn314_dsc_create(1621 struct dc_context *ctx, uint32_t inst)1622{1623 struct dcn20_dsc *dsc =1624 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);1625 1626 if (!dsc) {1627 BREAK_TO_DEBUGGER();1628 return NULL;1629 }1630 1631 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1632 return &dsc->base;1633}1634 1635static void dcn314_destroy_resource_pool(struct resource_pool **pool)1636{1637 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);1638 1639 dcn314_resource_destruct(dcn314_pool);1640 kfree(dcn314_pool);1641 *pool = NULL;1642}1643 1644static struct clock_source *dcn31_clock_source_create(1645 struct dc_context *ctx,1646 struct dc_bios *bios,1647 enum clock_source_id id,1648 const struct dce110_clk_src_regs *regs,1649 bool dp_clk_src)1650{1651 struct dce110_clk_src *clk_src =1652 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);1653 1654 if (!clk_src)1655 return NULL;1656 1657 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,1658 regs, &cs_shift, &cs_mask)) {1659 clk_src->base.dp_clk_src = dp_clk_src;1660 return &clk_src->base;1661 }1662 1663 kfree(clk_src);1664 BREAK_TO_DEBUGGER();1665 return NULL;1666}1667 1668static int dcn314_populate_dml_pipes_from_context(1669 struct dc *dc, struct dc_state *context,1670 display_e2e_pipe_params_st *pipes,1671 bool fast_validate)1672{1673 int pipe_cnt;1674 1675 DC_FP_START();1676 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);1677 DC_FP_END();1678 1679 return pipe_cnt;1680}1681 1682static struct dc_cap_funcs cap_funcs = {1683 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap1684};1685 1686static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)1687{1688 DC_FP_START();1689 dcn314_update_bw_bounding_box_fpu(dc, bw_params);1690 DC_FP_END();1691}1692 1693static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)1694{1695 *panel_config = panel_config_defaults;1696}1697 1698bool dcn314_validate_bandwidth(struct dc *dc,1699 struct dc_state *context,1700 bool fast_validate)1701{1702 bool out = false;1703 1704 BW_VAL_TRACE_SETUP();1705 1706 int vlevel = 0;1707 int pipe_cnt = 0;1708 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);1709 DC_LOGGER_INIT(dc->ctx->logger);1710 1711 BW_VAL_TRACE_COUNT();1712 1713 if (!pipes)1714 goto validate_fail;1715 1716 DC_FP_START();1717 // do not support self refresh only1718 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);1719 DC_FP_END();1720 1721 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg1722 if (pipe_cnt == 0)1723 fast_validate = false;1724 1725 if (!out)1726 goto validate_fail;1727 1728 BW_VAL_TRACE_END_VOLTAGE_LEVEL();1729 1730 if (fast_validate) {1731 BW_VAL_TRACE_SKIP(fast);1732 goto validate_out;1733 }1734 if (dc->res_pool->funcs->calculate_wm_and_dlg)1735 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);1736 1737 BW_VAL_TRACE_END_WATERMARKS();1738 1739 goto validate_out;1740 1741validate_fail:1742 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",1743 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));1744 1745 BW_VAL_TRACE_SKIP(fail);1746 out = false;1747 1748validate_out:1749 kfree(pipes);1750 1751 BW_VAL_TRACE_FINISH();1752 1753 return out;1754}1755 1756static struct resource_funcs dcn314_res_pool_funcs = {1757 .destroy = dcn314_destroy_resource_pool,1758 .link_enc_create = dcn31_link_encoder_create,1759 .link_enc_create_minimal = dcn31_link_enc_create_minimal,1760 .link_encs_assign = link_enc_cfg_link_encs_assign,1761 .link_enc_unassign = link_enc_cfg_link_enc_unassign,1762 .panel_cntl_create = dcn31_panel_cntl_create,1763 .validate_bandwidth = dcn314_validate_bandwidth,1764 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,1765 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,1766 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,1767 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,1768 .release_pipe = dcn20_release_pipe,1769 .add_stream_to_ctx = dcn30_add_stream_to_ctx,1770 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1771 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1772 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,1773 .set_mcif_arb_params = dcn30_set_mcif_arb_params,1774 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1775 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,1776 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,1777 .update_bw_bounding_box = dcn314_update_bw_bounding_box,1778 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,1779 .get_panel_config_defaults = dcn314_get_panel_config_defaults,1780 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,1781};1782 1783static struct clock_source *dcn30_clock_source_create(1784 struct dc_context *ctx,1785 struct dc_bios *bios,1786 enum clock_source_id id,1787 const struct dce110_clk_src_regs *regs,1788 bool dp_clk_src)1789{1790 struct dce110_clk_src *clk_src =1791 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);1792 1793 if (!clk_src)1794 return NULL;1795 1796 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,1797 regs, &cs_shift, &cs_mask)) {1798 clk_src->base.dp_clk_src = dp_clk_src;1799 return &clk_src->base;1800 }1801 1802 kfree(clk_src);1803 BREAK_TO_DEBUGGER();1804 return NULL;1805}1806 1807static bool dcn314_resource_construct(1808 uint8_t num_virtual_links,1809 struct dc *dc,1810 struct dcn314_resource_pool *pool)1811{1812 int i;1813 struct dc_context *ctx = dc->ctx;1814 struct irq_service_init_data init_data;1815 1816 ctx->dc_bios->regs = &bios_regs;1817 1818 pool->base.res_cap = &res_cap_dcn314;1819 pool->base.funcs = &dcn314_res_pool_funcs;1820 1821 /*************************************************1822 * Resource + asic cap harcoding *1823 *************************************************/1824 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;1825 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;1826 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;1827 dc->caps.max_downscale_ratio = 400;1828 dc->caps.i2c_speed_in_khz = 100;1829 dc->caps.i2c_speed_in_khz_hdcp = 100;1830 dc->caps.max_cursor_size = 256;1831 dc->caps.min_horizontal_blanking_period = 80;1832 dc->caps.dmdata_alloc_size = 2048;1833 dc->caps.max_slave_planes = 2;1834 dc->caps.max_slave_yuv_planes = 2;1835 dc->caps.max_slave_rgb_planes = 2;1836 dc->caps.post_blend_color_processing = true;1837 dc->caps.force_dp_tps4_for_cp2520 = true;1838 if (dc->config.forceHBR2CP2520)1839 dc->caps.force_dp_tps4_for_cp2520 = false;1840 dc->caps.dp_hpo = true;1841 dc->caps.dp_hdmi21_pcon_support = true;1842 dc->caps.edp_dsc_support = true;1843 dc->caps.extended_aux_timeout_support = true;1844 dc->caps.dmcub_support = true;1845 dc->caps.is_apu = true;1846 dc->caps.seamless_odm = true;1847 1848 dc->caps.zstate_support = true;1849 1850 /* Color pipeline capabilities */1851 dc->caps.color.dpp.dcn_arch = 1;1852 dc->caps.color.dpp.input_lut_shared = 0;1853 dc->caps.color.dpp.icsc = 1;1854 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr1855 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1856 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1857 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;1858 dc->caps.color.dpp.dgam_rom_caps.pq = 1;1859 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;1860 dc->caps.color.dpp.post_csc = 1;1861 dc->caps.color.dpp.gamma_corr = 1;1862 dc->caps.color.dpp.dgam_rom_for_yuv = 0;1863 1864 dc->caps.color.dpp.hw_3d_lut = 1;1865 dc->caps.color.dpp.ogam_ram = 1;1866 // no OGAM ROM on DCN3011867 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1868 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1869 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1870 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1871 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1872 dc->caps.color.dpp.ocsc = 0;1873 1874 dc->caps.color.mpc.gamut_remap = 1;1875 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //21876 dc->caps.color.mpc.ogam_ram = 1;1877 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1878 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1879 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1880 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1881 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1882 dc->caps.color.mpc.ocsc = 1;1883 1884 dc->caps.max_disp_clock_khz_at_vmin = 650000;1885 1886 /* Use pipe context based otg sync logic */1887 dc->config.use_pipe_ctx_sync_logic = true;1888 1889 /* read VBIOS LTTPR caps */1890 {1891 if (ctx->dc_bios->funcs->get_lttpr_caps) {1892 enum bp_result bp_query_result;1893 uint8_t is_vbios_lttpr_enable = 0;1894 1895 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);1896 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;1897 }1898 1899 /* interop bit is implicit */1900 {1901 dc->caps.vbios_lttpr_aware = true;1902 }1903 }1904 1905 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1906 dc->debug = debug_defaults_drv;1907 1908 /* Disable pipe power gating */1909 dc->debug.disable_dpp_power_gate = true;1910 dc->debug.disable_hubp_power_gate = true;1911 1912 /* Disable root clock optimization */1913 dc->debug.root_clock_optimization.u32All = 0;1914 1915 // Init the vm_helper1916 if (dc->vm_helper)1917 vm_helper_init(dc->vm_helper, 16);1918 1919 /*************************************************1920 * Create resources *1921 *************************************************/1922 1923 /* Clock Sources for Pixel Clock*/1924 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =1925 dcn30_clock_source_create(ctx, ctx->dc_bios,1926 CLOCK_SOURCE_COMBO_PHY_PLL0,1927 &clk_src_regs[0], false);1928 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =1929 dcn30_clock_source_create(ctx, ctx->dc_bios,1930 CLOCK_SOURCE_COMBO_PHY_PLL1,1931 &clk_src_regs[1], false);1932 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =1933 dcn30_clock_source_create(ctx, ctx->dc_bios,1934 CLOCK_SOURCE_COMBO_PHY_PLL2,1935 &clk_src_regs[2], false);1936 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =1937 dcn30_clock_source_create(ctx, ctx->dc_bios,1938 CLOCK_SOURCE_COMBO_PHY_PLL3,1939 &clk_src_regs[3], false);1940 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =1941 dcn30_clock_source_create(ctx, ctx->dc_bios,1942 CLOCK_SOURCE_COMBO_PHY_PLL4,1943 &clk_src_regs[4], false);1944 1945 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;1946 1947 /* todo: not reuse phy_pll registers */1948 pool->base.dp_clock_source =1949 dcn31_clock_source_create(ctx, ctx->dc_bios,1950 CLOCK_SOURCE_ID_DP_DTO,1951 &clk_src_regs[0], true);1952 1953 for (i = 0; i < pool->base.clk_src_count; i++) {1954 if (pool->base.clock_sources[i] == NULL) {1955 dm_error("DC: failed to create clock sources!\n");1956 BREAK_TO_DEBUGGER();1957 goto create_fail;1958 }1959 }1960 1961 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1962 if (pool->base.dccg == NULL) {1963 dm_error("DC: failed to create dccg!\n");1964 BREAK_TO_DEBUGGER();1965 goto create_fail;1966 }1967 1968 init_data.ctx = dc->ctx;1969 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);1970 if (!pool->base.irqs)1971 goto create_fail;1972 1973 /* HUBBUB */1974 pool->base.hubbub = dcn31_hubbub_create(ctx);1975 if (pool->base.hubbub == NULL) {1976 BREAK_TO_DEBUGGER();1977 dm_error("DC: failed to create hubbub!\n");1978 goto create_fail;1979 }1980 1981 /* HUBPs, DPPs, OPPs and TGs */1982 for (i = 0; i < pool->base.pipe_count; i++) {1983 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);1984 if (pool->base.hubps[i] == NULL) {1985 BREAK_TO_DEBUGGER();1986 dm_error(1987 "DC: failed to create hubps!\n");1988 goto create_fail;1989 }1990 1991 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);1992 if (pool->base.dpps[i] == NULL) {1993 BREAK_TO_DEBUGGER();1994 dm_error(1995 "DC: failed to create dpps!\n");1996 goto create_fail;1997 }1998 }1999 2000 for (i = 0; i < pool->base.res_cap->num_opp; i++) {2001 pool->base.opps[i] = dcn31_opp_create(ctx, i);2002 if (pool->base.opps[i] == NULL) {2003 BREAK_TO_DEBUGGER();2004 dm_error(2005 "DC: failed to create output pixel processor!\n");2006 goto create_fail;2007 }2008 }2009 2010 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2011 pool->base.timing_generators[i] = dcn31_timing_generator_create(2012 ctx, i);2013 if (pool->base.timing_generators[i] == NULL) {2014 BREAK_TO_DEBUGGER();2015 dm_error("DC: failed to create tg!\n");2016 goto create_fail;2017 }2018 }2019 pool->base.timing_generator_count = i;2020 2021 /* PSR */2022 pool->base.psr = dmub_psr_create(ctx);2023 if (pool->base.psr == NULL) {2024 dm_error("DC: failed to create psr obj!\n");2025 BREAK_TO_DEBUGGER();2026 goto create_fail;2027 }2028 2029 /* Replay */2030 pool->base.replay = dmub_replay_create(ctx);2031 if (pool->base.replay == NULL) {2032 dm_error("DC: failed to create replay obj!\n");2033 BREAK_TO_DEBUGGER();2034 goto create_fail;2035 }2036 2037 /* ABM */2038 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2039 pool->base.multiple_abms[i] = dmub_abm_create(ctx,2040 &abm_regs[i],2041 &abm_shift,2042 &abm_mask);2043 if (pool->base.multiple_abms[i] == NULL) {2044 dm_error("DC: failed to create abm for pipe %d!\n", i);2045 BREAK_TO_DEBUGGER();2046 goto create_fail;2047 }2048 }2049 2050 /* MPC and DSC */2051 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);2052 if (pool->base.mpc == NULL) {2053 BREAK_TO_DEBUGGER();2054 dm_error("DC: failed to create mpc!\n");2055 goto create_fail;2056 }2057 2058 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {2059 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);2060 if (pool->base.dscs[i] == NULL) {2061 BREAK_TO_DEBUGGER();2062 dm_error("DC: failed to create display stream compressor %d!\n", i);2063 goto create_fail;2064 }2065 }2066 2067 /* DWB and MMHUBBUB */2068 if (!dcn31_dwbc_create(ctx, &pool->base)) {2069 BREAK_TO_DEBUGGER();2070 dm_error("DC: failed to create dwbc!\n");2071 goto create_fail;2072 }2073 2074 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {2075 BREAK_TO_DEBUGGER();2076 dm_error("DC: failed to create mcif_wb!\n");2077 goto create_fail;2078 }2079 2080 /* AUX and I2C */2081 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {2082 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);2083 if (pool->base.engines[i] == NULL) {2084 BREAK_TO_DEBUGGER();2085 dm_error(2086 "DC:failed to create aux engine!!\n");2087 goto create_fail;2088 }2089 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);2090 if (pool->base.hw_i2cs[i] == NULL) {2091 BREAK_TO_DEBUGGER();2092 dm_error(2093 "DC:failed to create hw i2c!!\n");2094 goto create_fail;2095 }2096 pool->base.sw_i2cs[i] = NULL;2097 }2098 2099 /* DCN314 has 4 DPIA */2100 pool->base.usb4_dpia_count = 4;2101 2102 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */2103 if (!resource_construct(num_virtual_links, dc, &pool->base,2104 &res_create_funcs))2105 goto create_fail;2106 2107 /* HW Sequencer and Plane caps */2108 dcn314_hw_sequencer_construct(dc);2109 2110 dc->caps.max_planes = pool->base.pipe_count;2111 2112 for (i = 0; i < dc->caps.max_planes; ++i)2113 dc->caps.planes[i] = plane_cap;2114 2115 dc->cap_funcs = cap_funcs;2116 2117 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;2118 2119 return true;2120 2121create_fail:2122 2123 dcn314_resource_destruct(pool);2124 2125 return false;2126}2127 2128struct resource_pool *dcn314_create_resource_pool(2129 const struct dc_init_data *init_data,2130 struct dc *dc)2131{2132 struct dcn314_resource_pool *pool =2133 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);2134 2135 if (!pool)2136 return NULL;2137 2138 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))2139 return &pool->base;2140 2141 BREAK_TO_DEBUGGER();2142 kfree(pool);2143 return NULL;2144}2145