2168 lines · c
1/*2 * Copyright 2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26 27#include "dm_services.h"28#include "dc.h"29 30#include "dcn31/dcn31_init.h"31 32#include "resource.h"33#include "include/irq_service_interface.h"34#include "dcn315_resource.h"35 36#include "dcn20/dcn20_resource.h"37#include "dcn30/dcn30_resource.h"38#include "dcn31/dcn31_resource.h"39 40#include "dcn10/dcn10_ipp.h"41#include "dcn30/dcn30_hubbub.h"42#include "dcn31/dcn31_hubbub.h"43#include "dcn30/dcn30_mpc.h"44#include "dcn31/dcn31_hubp.h"45#include "irq/dcn315/irq_service_dcn315.h"46#include "dcn30/dcn30_dpp.h"47#include "dcn31/dcn31_optc.h"48#include "dcn20/dcn20_hwseq.h"49#include "dcn30/dcn30_hwseq.h"50#include "dce110/dce110_hwseq.h"51#include "dcn30/dcn30_opp.h"52#include "dcn20/dcn20_dsc.h"53#include "dcn30/dcn30_vpg.h"54#include "dcn30/dcn30_afmt.h"55#include "dcn30/dcn30_dio_stream_encoder.h"56#include "dcn31/dcn31_hpo_dp_stream_encoder.h"57#include "dcn31/dcn31_hpo_dp_link_encoder.h"58#include "dcn31/dcn31_apg.h"59#include "dcn31/dcn31_dio_link_encoder.h"60#include "dcn31/dcn31_vpg.h"61#include "dcn31/dcn31_afmt.h"62#include "dce/dce_clock_source.h"63#include "dce/dce_audio.h"64#include "dce/dce_hwseq.h"65#include "clk_mgr.h"66#include "virtual/virtual_stream_encoder.h"67#include "dce110/dce110_resource.h"68#include "dml/display_mode_vba.h"69#include "dml/dcn31/dcn31_fpu.h"70#include "dcn31/dcn31_dccg.h"71#include "dcn10/dcn10_resource.h"72#include "dcn31/dcn31_panel_cntl.h"73 74#include "dcn30/dcn30_dwb.h"75#include "dcn30/dcn30_mmhubbub.h"76 77#include "dcn/dcn_3_1_5_offset.h"78#include "dcn/dcn_3_1_5_sh_mask.h"79#include "dpcs/dpcs_4_2_2_offset.h"80#include "dpcs/dpcs_4_2_2_sh_mask.h"81 82#define NBIO_BASE__INST0_SEG0 0x0000000083#define NBIO_BASE__INST0_SEG1 0x0000001484#define NBIO_BASE__INST0_SEG2 0x00000D2085#define NBIO_BASE__INST0_SEG3 0x0001040086#define NBIO_BASE__INST0_SEG4 0x0241B00087#define NBIO_BASE__INST0_SEG5 0x0404000088 89#define DPCS_BASE__INST0_SEG0 0x0000001290#define DPCS_BASE__INST0_SEG1 0x000000C091#define DPCS_BASE__INST0_SEG2 0x000034C092#define DPCS_BASE__INST0_SEG3 0x0000900093#define DPCS_BASE__INST0_SEG4 0x02403C0094#define DPCS_BASE__INST0_SEG5 095 96#define DCN_BASE__INST0_SEG0 0x0000001297#define DCN_BASE__INST0_SEG1 0x000000C098#define DCN_BASE__INST0_SEG2 0x000034C099#define DCN_BASE__INST0_SEG3 0x00009000100#define DCN_BASE__INST0_SEG4 0x02403C00101#define DCN_BASE__INST0_SEG5 0102 103#define regBIF_BX_PF2_RSMU_INDEX 0x0000104#define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1105#define regBIF_BX_PF2_RSMU_DATA 0x0001106#define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1107#define regBIF_BX2_BIOS_SCRATCH_6 0x003e108#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1109#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0110#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL111#define regBIF_BX2_BIOS_SCRATCH_2 0x003a112#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1113#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0114#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL115#define regBIF_BX2_BIOS_SCRATCH_3 0x003b116#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1117#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0118#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL119 120#define regDCHUBBUB_DEBUG_CTRL_0 0x04d6121#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2122#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10123#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L124 125#include "reg_helper.h"126#include "dce/dmub_abm.h"127#include "dce/dmub_psr.h"128#include "dce/dmub_replay.h"129#include "dce/dce_aux.h"130#include "dce/dce_i2c.h"131 132#include "dml/dcn30/display_mode_vba_30.h"133#include "vm_helper.h"134#include "dcn20/dcn20_vmid.h"135 136#include "link_enc_cfg.h"137 138#define DCN3_15_MAX_DET_SIZE 384139#define DCN3_15_CRB_SEGMENT_SIZE_KB 64140#define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB)141/* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */142#define MIN_RESERVED_DET_SEGS 3143 144enum dcn31_clk_src_array_id {145 DCN31_CLK_SRC_PLL0,146 DCN31_CLK_SRC_PLL1,147 DCN31_CLK_SRC_PLL2,148 DCN31_CLK_SRC_PLL3,149 DCN31_CLK_SRC_PLL4,150 DCN30_CLK_SRC_TOTAL151};152 153/* begin *********************154 * macros to expend register list macro defined in HW object header file155 */156 157/* DCN */158#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg159 160#define BASE(seg) BASE_INNER(seg)161 162#define SR(reg_name)\163 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \164 reg ## reg_name165 166#define SRI(reg_name, block, id)\167 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \168 reg ## block ## id ## _ ## reg_name169 170#define SRI2(reg_name, block, id)\171 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \172 reg ## reg_name173 174#define SRIR(var_name, reg_name, block, id)\175 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \176 reg ## block ## id ## _ ## reg_name177 178#define SRII(reg_name, block, id)\179 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \180 reg ## block ## id ## _ ## reg_name181 182#define SRII_MPC_RMU(reg_name, block, id)\183 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \184 reg ## block ## id ## _ ## reg_name185 186#define SRII_DWB(reg_name, temp_name, block, id)\187 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \188 reg ## block ## id ## _ ## temp_name189 190#define SF_DWB2(reg_name, block, id, field_name, post_fix) \191 .field_name = reg_name ## __ ## field_name ## post_fix192 193#define DCCG_SRII(reg_name, block, id)\194 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \195 reg ## block ## id ## _ ## reg_name196 197#define VUPDATE_SRII(reg_name, block, id)\198 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \199 reg ## reg_name ## _ ## block ## id200 201/* NBIO */202#define NBIO_BASE_INNER(seg) \203 NBIO_BASE__INST0_SEG ## seg204 205#define NBIO_BASE(seg) \206 NBIO_BASE_INNER(seg)207 208#define NBIO_SR(reg_name)\209 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \210 regBIF_BX2_ ## reg_name211 212static const struct bios_registers bios_regs = {213 NBIO_SR(BIOS_SCRATCH_3),214 NBIO_SR(BIOS_SCRATCH_6)215};216 217#define clk_src_regs(index, pllid)\218[index] = {\219 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\220}221 222static const struct dce110_clk_src_regs clk_src_regs[] = {223 clk_src_regs(0, A),224 clk_src_regs(1, B),225 clk_src_regs(2, C),226 clk_src_regs(3, D),227 clk_src_regs(4, E)228};229 230static const struct dce110_clk_src_shift cs_shift = {231 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)232};233 234static const struct dce110_clk_src_mask cs_mask = {235 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)236};237 238#define abm_regs(id)\239[id] = {\240 ABM_DCN302_REG_LIST(id)\241}242 243static const struct dce_abm_registers abm_regs[] = {244 abm_regs(0),245 abm_regs(1),246 abm_regs(2),247 abm_regs(3),248};249 250static const struct dce_abm_shift abm_shift = {251 ABM_MASK_SH_LIST_DCN30(__SHIFT)252};253 254static const struct dce_abm_mask abm_mask = {255 ABM_MASK_SH_LIST_DCN30(_MASK)256};257 258#define audio_regs(id)\259[id] = {\260 AUD_COMMON_REG_LIST(id)\261}262 263static const struct dce_audio_registers audio_regs[] = {264 audio_regs(0),265 audio_regs(1),266 audio_regs(2),267 audio_regs(3),268 audio_regs(4),269 audio_regs(5),270 audio_regs(6)271};272 273#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\274 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\275 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\276 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)277 278static const struct dce_audio_shift audio_shift = {279 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)280};281 282static const struct dce_audio_mask audio_mask = {283 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)284};285 286#define vpg_regs(id)\287[id] = {\288 VPG_DCN31_REG_LIST(id)\289}290 291static const struct dcn31_vpg_registers vpg_regs[] = {292 vpg_regs(0),293 vpg_regs(1),294 vpg_regs(2),295 vpg_regs(3),296 vpg_regs(4),297 vpg_regs(5),298 vpg_regs(6),299 vpg_regs(7),300 vpg_regs(8),301 vpg_regs(9),302};303 304static const struct dcn31_vpg_shift vpg_shift = {305 DCN31_VPG_MASK_SH_LIST(__SHIFT)306};307 308static const struct dcn31_vpg_mask vpg_mask = {309 DCN31_VPG_MASK_SH_LIST(_MASK)310};311 312#define afmt_regs(id)\313[id] = {\314 AFMT_DCN31_REG_LIST(id)\315}316 317static const struct dcn31_afmt_registers afmt_regs[] = {318 afmt_regs(0),319 afmt_regs(1),320 afmt_regs(2),321 afmt_regs(3),322 afmt_regs(4),323 afmt_regs(5)324};325 326static const struct dcn31_afmt_shift afmt_shift = {327 DCN31_AFMT_MASK_SH_LIST(__SHIFT)328};329 330static const struct dcn31_afmt_mask afmt_mask = {331 DCN31_AFMT_MASK_SH_LIST(_MASK)332};333 334#define apg_regs(id)\335[id] = {\336 APG_DCN31_REG_LIST(id)\337}338 339static const struct dcn31_apg_registers apg_regs[] = {340 apg_regs(0),341 apg_regs(1),342 apg_regs(2),343 apg_regs(3)344};345 346static const struct dcn31_apg_shift apg_shift = {347 DCN31_APG_MASK_SH_LIST(__SHIFT)348};349 350static const struct dcn31_apg_mask apg_mask = {351 DCN31_APG_MASK_SH_LIST(_MASK)352};353 354#define stream_enc_regs(id)\355[id] = {\356 SE_DCN3_REG_LIST(id)\357}358 359static const struct dcn10_stream_enc_registers stream_enc_regs[] = {360 stream_enc_regs(0),361 stream_enc_regs(1),362 stream_enc_regs(2),363 stream_enc_regs(3),364 stream_enc_regs(4)365};366 367static const struct dcn10_stream_encoder_shift se_shift = {368 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)369};370 371static const struct dcn10_stream_encoder_mask se_mask = {372 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)373};374 375 376#define aux_regs(id)\377[id] = {\378 DCN2_AUX_REG_LIST(id)\379}380 381static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {382 aux_regs(0),383 aux_regs(1),384 aux_regs(2),385 aux_regs(3),386 aux_regs(4)387};388 389#define hpd_regs(id)\390[id] = {\391 HPD_REG_LIST(id)\392}393 394static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {395 hpd_regs(0),396 hpd_regs(1),397 hpd_regs(2),398 hpd_regs(3),399 hpd_regs(4)400};401 402#define link_regs(id, phyid)\403[id] = {\404 LE_DCN31_REG_LIST(id), \405 UNIPHY_DCN2_REG_LIST(phyid), \406 DPCS_DCN31_REG_LIST(id), \407}408 409static const struct dce110_aux_registers_shift aux_shift = {410 DCN_AUX_MASK_SH_LIST(__SHIFT)411};412 413static const struct dce110_aux_registers_mask aux_mask = {414 DCN_AUX_MASK_SH_LIST(_MASK)415};416 417static const struct dcn10_link_enc_registers link_enc_regs[] = {418 link_regs(0, A),419 link_regs(1, B),420 link_regs(2, C),421 link_regs(3, D),422 link_regs(4, E)423};424 425static const struct dcn10_link_enc_shift le_shift = {426 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \427 DPCS_DCN31_MASK_SH_LIST(__SHIFT)428};429 430static const struct dcn10_link_enc_mask le_mask = {431 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \432 DPCS_DCN31_MASK_SH_LIST(_MASK)433};434 435#define hpo_dp_stream_encoder_reg_list(id)\436[id] = {\437 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\438}439 440static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {441 hpo_dp_stream_encoder_reg_list(0),442 hpo_dp_stream_encoder_reg_list(1),443 hpo_dp_stream_encoder_reg_list(2),444 hpo_dp_stream_encoder_reg_list(3),445};446 447static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {448 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)449};450 451static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {452 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)453};454 455 456#define hpo_dp_link_encoder_reg_list(id)\457[id] = {\458 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\459 DCN3_1_RDPCSTX_REG_LIST(0),\460 DCN3_1_RDPCSTX_REG_LIST(1),\461 DCN3_1_RDPCSTX_REG_LIST(2),\462 DCN3_1_RDPCSTX_REG_LIST(3),\463 DCN3_1_RDPCSTX_REG_LIST(4)\464}465 466static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {467 hpo_dp_link_encoder_reg_list(0),468 hpo_dp_link_encoder_reg_list(1),469};470 471static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)473};474 475static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {476 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)477};478 479#define dpp_regs(id)\480[id] = {\481 DPP_REG_LIST_DCN30(id),\482}483 484static const struct dcn3_dpp_registers dpp_regs[] = {485 dpp_regs(0),486 dpp_regs(1),487 dpp_regs(2),488 dpp_regs(3)489};490 491static const struct dcn3_dpp_shift tf_shift = {492 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)493};494 495static const struct dcn3_dpp_mask tf_mask = {496 DPP_REG_LIST_SH_MASK_DCN30(_MASK)497};498 499#define opp_regs(id)\500[id] = {\501 OPP_REG_LIST_DCN30(id),\502}503 504static const struct dcn20_opp_registers opp_regs[] = {505 opp_regs(0),506 opp_regs(1),507 opp_regs(2),508 opp_regs(3)509};510 511static const struct dcn20_opp_shift opp_shift = {512 OPP_MASK_SH_LIST_DCN20(__SHIFT)513};514 515static const struct dcn20_opp_mask opp_mask = {516 OPP_MASK_SH_LIST_DCN20(_MASK)517};518 519#define aux_engine_regs(id)\520[id] = {\521 AUX_COMMON_REG_LIST0(id), \522 .AUXN_IMPCAL = 0, \523 .AUXP_IMPCAL = 0, \524 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \525}526 527static const struct dce110_aux_registers aux_engine_regs[] = {528 aux_engine_regs(0),529 aux_engine_regs(1),530 aux_engine_regs(2),531 aux_engine_regs(3),532 aux_engine_regs(4)533};534 535#define dwbc_regs_dcn3(id)\536[id] = {\537 DWBC_COMMON_REG_LIST_DCN30(id),\538}539 540static const struct dcn30_dwbc_registers dwbc30_regs[] = {541 dwbc_regs_dcn3(0),542};543 544static const struct dcn30_dwbc_shift dwbc30_shift = {545 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)546};547 548static const struct dcn30_dwbc_mask dwbc30_mask = {549 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)550};551 552#define mcif_wb_regs_dcn3(id)\553[id] = {\554 MCIF_WB_COMMON_REG_LIST_DCN30(id),\555}556 557static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {558 mcif_wb_regs_dcn3(0)559};560 561static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)563};564 565static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {566 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)567};568 569#define dsc_regsDCN20(id)\570[id] = {\571 DSC_REG_LIST_DCN20(id)\572}573 574static const struct dcn20_dsc_registers dsc_regs[] = {575 dsc_regsDCN20(0),576 dsc_regsDCN20(1),577 dsc_regsDCN20(2)578};579 580static const struct dcn20_dsc_shift dsc_shift = {581 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)582};583 584static const struct dcn20_dsc_mask dsc_mask = {585 DSC_REG_LIST_SH_MASK_DCN20(_MASK)586};587 588static const struct dcn30_mpc_registers mpc_regs = {589 MPC_REG_LIST_DCN3_0(0),590 MPC_REG_LIST_DCN3_0(1),591 MPC_REG_LIST_DCN3_0(2),592 MPC_REG_LIST_DCN3_0(3),593 MPC_OUT_MUX_REG_LIST_DCN3_0(0),594 MPC_OUT_MUX_REG_LIST_DCN3_0(1),595 MPC_OUT_MUX_REG_LIST_DCN3_0(2),596 MPC_OUT_MUX_REG_LIST_DCN3_0(3),597 MPC_DWB_MUX_REG_LIST_DCN3_0(0),598};599 600static const struct dcn30_mpc_shift mpc_shift = {601 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)602};603 604static const struct dcn30_mpc_mask mpc_mask = {605 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)606};607 608#define optc_regs(id)\609[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}610 611static const struct dcn_optc_registers optc_regs[] = {612 optc_regs(0),613 optc_regs(1),614 optc_regs(2),615 optc_regs(3)616};617 618static const struct dcn_optc_shift optc_shift = {619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)620};621 622static const struct dcn_optc_mask optc_mask = {623 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)624};625 626#define hubp_regs(id)\627[id] = {\628 HUBP_REG_LIST_DCN30(id)\629}630 631static const struct dcn_hubp2_registers hubp_regs[] = {632 hubp_regs(0),633 hubp_regs(1),634 hubp_regs(2),635 hubp_regs(3)636};637 638 639static const struct dcn_hubp2_shift hubp_shift = {640 HUBP_MASK_SH_LIST_DCN31(__SHIFT)641};642 643static const struct dcn_hubp2_mask hubp_mask = {644 HUBP_MASK_SH_LIST_DCN31(_MASK)645};646static const struct dcn_hubbub_registers hubbub_reg = {647 HUBBUB_REG_LIST_DCN31(0)648};649 650static const struct dcn_hubbub_shift hubbub_shift = {651 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)652};653 654static const struct dcn_hubbub_mask hubbub_mask = {655 HUBBUB_MASK_SH_LIST_DCN31(_MASK)656};657 658static const struct dccg_registers dccg_regs = {659 DCCG_REG_LIST_DCN31()660};661 662static const struct dccg_shift dccg_shift = {663 DCCG_MASK_SH_LIST_DCN31(__SHIFT)664};665 666static const struct dccg_mask dccg_mask = {667 DCCG_MASK_SH_LIST_DCN31(_MASK)668};669 670 671#define SRII2(reg_name_pre, reg_name_post, id)\672 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \673 ## id ## _ ## reg_name_post ## _BASE_IDX) + \674 reg ## reg_name_pre ## id ## _ ## reg_name_post675 676 677#define HWSEQ_DCN31_REG_LIST()\678 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \679 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \680 SR(DIO_MEM_PWR_CTRL), \681 SR(ODM_MEM_PWR_CTRL3), \682 SR(DMU_MEM_PWR_CNTL), \683 SR(MMHUBBUB_MEM_PWR_CNTL), \684 SR(DCCG_GATE_DISABLE_CNTL), \685 SR(DCCG_GATE_DISABLE_CNTL2), \686 SR(DCFCLK_CNTL),\687 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \688 SRII(PIXEL_RATE_CNTL, OTG, 0), \689 SRII(PIXEL_RATE_CNTL, OTG, 1),\690 SRII(PIXEL_RATE_CNTL, OTG, 2),\691 SRII(PIXEL_RATE_CNTL, OTG, 3),\692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\696 SR(MICROSECOND_TIME_BASE_DIV), \697 SR(MILLISECOND_TIME_BASE_DIV), \698 SR(DISPCLK_FREQ_CHANGE_CNTL), \699 SR(RBBMIF_TIMEOUT_DIS), \700 SR(RBBMIF_TIMEOUT_DIS_2), \701 SR(DCHUBBUB_CRC_CTRL), \702 SR(DPP_TOP0_DPP_CRC_CTRL), \703 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \704 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \705 SR(MPC_CRC_CTRL), \706 SR(MPC_CRC_RESULT_GB), \707 SR(MPC_CRC_RESULT_C), \708 SR(MPC_CRC_RESULT_AR), \709 SR(DOMAIN0_PG_CONFIG), \710 SR(DOMAIN1_PG_CONFIG), \711 SR(DOMAIN2_PG_CONFIG), \712 SR(DOMAIN3_PG_CONFIG), \713 SR(DOMAIN16_PG_CONFIG), \714 SR(DOMAIN17_PG_CONFIG), \715 SR(DOMAIN18_PG_CONFIG), \716 SR(DOMAIN0_PG_STATUS), \717 SR(DOMAIN1_PG_STATUS), \718 SR(DOMAIN2_PG_STATUS), \719 SR(DOMAIN3_PG_STATUS), \720 SR(DOMAIN16_PG_STATUS), \721 SR(DOMAIN17_PG_STATUS), \722 SR(DOMAIN18_PG_STATUS), \723 SR(D1VGA_CONTROL), \724 SR(D2VGA_CONTROL), \725 SR(D3VGA_CONTROL), \726 SR(D4VGA_CONTROL), \727 SR(D5VGA_CONTROL), \728 SR(D6VGA_CONTROL), \729 SR(DC_IP_REQUEST_CNTL), \730 SR(AZALIA_AUDIO_DTO), \731 SR(AZALIA_CONTROLLER_CLOCK_GATING), \732 SR(HPO_TOP_HW_CONTROL)733 734static const struct dce_hwseq_registers hwseq_reg = {735 HWSEQ_DCN31_REG_LIST()736};737 738#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\739 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \740 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \741 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \751 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \753 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \755 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \756 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \757 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \758 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \759 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \760 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \761 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \762 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \764 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \765 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \766 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \768 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \769 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \770 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \771 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)772 773static const struct dce_hwseq_shift hwseq_shift = {774 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)775};776 777static const struct dce_hwseq_mask hwseq_mask = {778 HWSEQ_DCN31_MASK_SH_LIST(_MASK)779};780#define vmid_regs(id)\781[id] = {\782 DCN20_VMID_REG_LIST(id)\783}784 785static const struct dcn_vmid_registers vmid_regs[] = {786 vmid_regs(0),787 vmid_regs(1),788 vmid_regs(2),789 vmid_regs(3),790 vmid_regs(4),791 vmid_regs(5),792 vmid_regs(6),793 vmid_regs(7),794 vmid_regs(8),795 vmid_regs(9),796 vmid_regs(10),797 vmid_regs(11),798 vmid_regs(12),799 vmid_regs(13),800 vmid_regs(14),801 vmid_regs(15)802};803 804static const struct dcn20_vmid_shift vmid_shifts = {805 DCN20_VMID_MASK_SH_LIST(__SHIFT)806};807 808static const struct dcn20_vmid_mask vmid_masks = {809 DCN20_VMID_MASK_SH_LIST(_MASK)810};811 812static const struct resource_caps res_cap_dcn31 = {813 .num_timing_generator = 4,814 .num_opp = 4,815 .num_video_plane = 4,816 .num_audio = 5,817 .num_stream_encoder = 5,818 .num_dig_link_enc = 5,819 .num_hpo_dp_stream_encoder = 4,820 .num_hpo_dp_link_encoder = 2,821 .num_pll = 5,822 .num_dwb = 1,823 .num_ddc = 5,824 .num_vmid = 16,825 .num_mpc_3dlut = 2,826 .num_dsc = 3,827};828 829static const struct dc_plane_cap plane_cap = {830 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,831 .per_pixel_alpha = true,832 833 .pixel_format_support = {834 .argb8888 = true,835 .nv12 = true,836 .fp16 = true,837 .p010 = true,838 .ayuv = false,839 },840 841 .max_upscale_factor = {842 .argb8888 = 16000,843 .nv12 = 16000,844 .fp16 = 16000845 },846 847 // 6:1 downscaling ratio: 1000/6 = 166.666848 .max_downscale_factor = {849 .argb8888 = 167,850 .nv12 = 167,851 .fp16 = 167852 },853 64,854 64855};856 857static const struct dc_debug_options debug_defaults_drv = {858 .disable_z10 = true, /*hw not support it*/859 .disable_dmcu = true,860 .force_abm_enable = false,861 .timing_trace = false,862 .clock_trace = true,863 .disable_pplib_clock_request = false,864 .pipe_split_policy = MPC_SPLIT_DYNAMIC,865 .force_single_disp_pipe_split = false,866 .disable_dcc = DCC_ENABLE,867 .vsr_support = true,868 .performance_trace = false,869 .max_downscale_src_width = 4096,/*upto true 4k*/870 .disable_pplib_wm_range = false,871 .scl_reset_length10 = true,872 .sanity_checks = false,873 .underflow_assert_delay_us = 0xFFFFFFFF,874 .dwb_fi_phase = -1, // -1 = disable,875 .dmub_command_table = true,876 .pstate_enabled = true,877 .use_max_lb = true,878 .enable_mem_low_power = {879 .bits = {880 .vga = true,881 .i2c = true,882 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled883 .dscl = true,884 .cm = true,885 .mpc = true,886 .optc = true,887 .vpg = true,888 .afmt = true,889 }890 },891 .enable_legacy_fast_update = true,892 .psr_power_use_phy_fsm = 0,893 .using_dml2 = false,894};895 896static const struct dc_panel_config panel_config_defaults = {897 .psr = {898 .disable_psr = false,899 .disallow_psrsu = false,900 .disallow_replay = false,901 },902 .ilr = {903 .optimize_edp_link_rate = true,904 },905};906 907static void dcn31_dpp_destroy(struct dpp **dpp)908{909 kfree(TO_DCN20_DPP(*dpp));910 *dpp = NULL;911}912 913static struct dpp *dcn31_dpp_create(914 struct dc_context *ctx,915 uint32_t inst)916{917 struct dcn3_dpp *dpp =918 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);919 920 if (!dpp)921 return NULL;922 923 if (dpp3_construct(dpp, ctx, inst,924 &dpp_regs[inst], &tf_shift, &tf_mask))925 return &dpp->base;926 927 BREAK_TO_DEBUGGER();928 kfree(dpp);929 return NULL;930}931 932static struct output_pixel_processor *dcn31_opp_create(933 struct dc_context *ctx, uint32_t inst)934{935 struct dcn20_opp *opp =936 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);937 938 if (!opp) {939 BREAK_TO_DEBUGGER();940 return NULL;941 }942 943 dcn20_opp_construct(opp, ctx, inst,944 &opp_regs[inst], &opp_shift, &opp_mask);945 return &opp->base;946}947 948static struct dce_aux *dcn31_aux_engine_create(949 struct dc_context *ctx,950 uint32_t inst)951{952 struct aux_engine_dce110 *aux_engine =953 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);954 955 if (!aux_engine)956 return NULL;957 958 dce110_aux_engine_construct(aux_engine, ctx, inst,959 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,960 &aux_engine_regs[inst],961 &aux_mask,962 &aux_shift,963 ctx->dc->caps.extended_aux_timeout_support);964 965 return &aux_engine->base;966}967#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }968 969static const struct dce_i2c_registers i2c_hw_regs[] = {970 i2c_inst_regs(1),971 i2c_inst_regs(2),972 i2c_inst_regs(3),973 i2c_inst_regs(4),974 i2c_inst_regs(5),975};976 977static const struct dce_i2c_shift i2c_shifts = {978 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)979};980 981static const struct dce_i2c_mask i2c_masks = {982 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)983};984 985static struct dce_i2c_hw *dcn31_i2c_hw_create(986 struct dc_context *ctx,987 uint32_t inst)988{989 struct dce_i2c_hw *dce_i2c_hw =990 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);991 992 if (!dce_i2c_hw)993 return NULL;994 995 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,996 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);997 998 return dce_i2c_hw;999}1000static struct mpc *dcn31_mpc_create(1001 struct dc_context *ctx,1002 int num_mpcc,1003 int num_rmu)1004{1005 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),1006 GFP_KERNEL);1007 1008 if (!mpc30)1009 return NULL;1010 1011 dcn30_mpc_construct(mpc30, ctx,1012 &mpc_regs,1013 &mpc_shift,1014 &mpc_mask,1015 num_mpcc,1016 num_rmu);1017 1018 return &mpc30->base;1019}1020 1021static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)1022{1023 int i;1024 1025 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),1026 GFP_KERNEL);1027 1028 if (!hubbub3)1029 return NULL;1030 1031 hubbub31_construct(hubbub3, ctx,1032 &hubbub_reg,1033 &hubbub_shift,1034 &hubbub_mask,1035 dcn3_15_ip.det_buffer_size_kbytes,1036 dcn3_15_ip.pixel_chunk_size_kbytes,1037 dcn3_15_ip.config_return_buffer_size_in_kbytes);1038 1039 1040 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {1041 struct dcn20_vmid *vmid = &hubbub3->vmid[i];1042 1043 vmid->ctx = ctx;1044 1045 vmid->regs = &vmid_regs[i];1046 vmid->shifts = &vmid_shifts;1047 vmid->masks = &vmid_masks;1048 }1049 1050 return &hubbub3->base;1051}1052 1053static struct timing_generator *dcn31_timing_generator_create(1054 struct dc_context *ctx,1055 uint32_t instance)1056{1057 struct optc *tgn10 =1058 kzalloc(sizeof(struct optc), GFP_KERNEL);1059 1060 if (!tgn10)1061 return NULL;1062 1063 tgn10->base.inst = instance;1064 tgn10->base.ctx = ctx;1065 1066 tgn10->tg_regs = &optc_regs[instance];1067 tgn10->tg_shift = &optc_shift;1068 tgn10->tg_mask = &optc_mask;1069 1070 dcn31_timing_generator_init(tgn10);1071 1072 return &tgn10->base;1073}1074 1075static const struct encoder_feature_support link_enc_feature = {1076 .max_hdmi_deep_color = COLOR_DEPTH_121212,1077 .max_hdmi_pixel_clock = 600000,1078 .hdmi_ycbcr420_supported = true,1079 .dp_ycbcr420_supported = true,1080 .fec_supported = true,1081 .flags.bits.IS_HBR2_CAPABLE = true,1082 .flags.bits.IS_HBR3_CAPABLE = true,1083 .flags.bits.IS_TPS3_CAPABLE = true,1084 .flags.bits.IS_TPS4_CAPABLE = true1085};1086 1087static struct link_encoder *dcn31_link_encoder_create(1088 struct dc_context *ctx,1089 const struct encoder_init_data *enc_init_data)1090{1091 struct dcn20_link_encoder *enc20 =1092 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1093 1094 if (!enc20)1095 return NULL;1096 1097 dcn31_link_encoder_construct(enc20,1098 enc_init_data,1099 &link_enc_feature,1100 &link_enc_regs[enc_init_data->transmitter],1101 &link_enc_aux_regs[enc_init_data->channel - 1],1102 &link_enc_hpd_regs[enc_init_data->hpd_source],1103 &le_shift,1104 &le_mask);1105 1106 return &enc20->enc10.base;1107}1108 1109/* Create a minimal link encoder object not associated with a particular1110 * physical connector.1111 * resource_funcs.link_enc_create_minimal1112 */1113static struct link_encoder *dcn31_link_enc_create_minimal(1114 struct dc_context *ctx, enum engine_id eng_id)1115{1116 struct dcn20_link_encoder *enc20;1117 1118 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)1119 return NULL;1120 1121 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1122 if (!enc20)1123 return NULL;1124 1125 dcn31_link_encoder_construct_minimal(1126 enc20,1127 ctx,1128 &link_enc_feature,1129 &link_enc_regs[eng_id - ENGINE_ID_DIGA],1130 eng_id);1131 1132 return &enc20->enc10.base;1133}1134 1135static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)1136{1137 struct dcn31_panel_cntl *panel_cntl =1138 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);1139 1140 if (!panel_cntl)1141 return NULL;1142 1143 dcn31_panel_cntl_construct(panel_cntl, init_data);1144 1145 return &panel_cntl->base;1146}1147 1148static void read_dce_straps(1149 struct dc_context *ctx,1150 struct resource_straps *straps)1151{1152 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),1153 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);1154 1155}1156 1157static struct audio *dcn31_create_audio(1158 struct dc_context *ctx, unsigned int inst)1159{1160 return dce_audio_create(ctx, inst,1161 &audio_regs[inst], &audio_shift, &audio_mask);1162}1163 1164static struct vpg *dcn31_vpg_create(1165 struct dc_context *ctx,1166 uint32_t inst)1167{1168 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);1169 1170 if (!vpg31)1171 return NULL;1172 1173 vpg31_construct(vpg31, ctx, inst,1174 &vpg_regs[inst],1175 &vpg_shift,1176 &vpg_mask);1177 1178 return &vpg31->base;1179}1180 1181static struct afmt *dcn31_afmt_create(1182 struct dc_context *ctx,1183 uint32_t inst)1184{1185 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);1186 1187 if (!afmt31)1188 return NULL;1189 1190 afmt31_construct(afmt31, ctx, inst,1191 &afmt_regs[inst],1192 &afmt_shift,1193 &afmt_mask);1194 1195 // Light sleep by default, no need to power down here1196 1197 return &afmt31->base;1198}1199 1200static struct apg *dcn31_apg_create(1201 struct dc_context *ctx,1202 uint32_t inst)1203{1204 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);1205 1206 if (!apg31)1207 return NULL;1208 1209 apg31_construct(apg31, ctx, inst,1210 &apg_regs[inst],1211 &apg_shift,1212 &apg_mask);1213 1214 return &apg31->base;1215}1216 1217static struct stream_encoder *dcn315_stream_encoder_create(1218 enum engine_id eng_id,1219 struct dc_context *ctx)1220{1221 struct dcn10_stream_encoder *enc1;1222 struct vpg *vpg;1223 struct afmt *afmt;1224 int vpg_inst;1225 int afmt_inst;1226 1227 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/1228 1229 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */1230 if (eng_id <= ENGINE_ID_DIGF) {1231 vpg_inst = eng_id;1232 afmt_inst = eng_id;1233 } else1234 return NULL;1235 1236 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1237 vpg = dcn31_vpg_create(ctx, vpg_inst);1238 afmt = dcn31_afmt_create(ctx, afmt_inst);1239 1240 if (!enc1 || !vpg || !afmt) {1241 kfree(enc1);1242 kfree(vpg);1243 kfree(afmt);1244 return NULL;1245 }1246 1247 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,1248 eng_id, vpg, afmt,1249 &stream_enc_regs[eng_id],1250 &se_shift, &se_mask);1251 1252 return &enc1->base;1253}1254 1255static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(1256 enum engine_id eng_id,1257 struct dc_context *ctx)1258{1259 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;1260 struct vpg *vpg;1261 struct apg *apg;1262 uint32_t hpo_dp_inst;1263 uint32_t vpg_inst;1264 uint32_t apg_inst;1265 1266 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));1267 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;1268 1269 /* Mapping of VPG register blocks to HPO DP block instance:1270 * VPG[6] -> HPO_DP[0]1271 * VPG[7] -> HPO_DP[1]1272 * VPG[8] -> HPO_DP[2]1273 * VPG[9] -> HPO_DP[3]1274 */1275 vpg_inst = hpo_dp_inst + 6;1276 1277 /* Mapping of APG register blocks to HPO DP block instance:1278 * APG[0] -> HPO_DP[0]1279 * APG[1] -> HPO_DP[1]1280 * APG[2] -> HPO_DP[2]1281 * APG[3] -> HPO_DP[3]1282 */1283 apg_inst = hpo_dp_inst;1284 1285 /* allocate HPO stream encoder and create VPG sub-block */1286 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);1287 vpg = dcn31_vpg_create(ctx, vpg_inst);1288 apg = dcn31_apg_create(ctx, apg_inst);1289 1290 if (!hpo_dp_enc31 || !vpg || !apg) {1291 kfree(hpo_dp_enc31);1292 kfree(vpg);1293 kfree(apg);1294 return NULL;1295 }1296 1297 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,1298 hpo_dp_inst, eng_id, vpg, apg,1299 &hpo_dp_stream_enc_regs[hpo_dp_inst],1300 &hpo_dp_se_shift, &hpo_dp_se_mask);1301 1302 return &hpo_dp_enc31->base;1303}1304 1305static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(1306 uint8_t inst,1307 struct dc_context *ctx)1308{1309 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;1310 1311 /* allocate HPO link encoder */1312 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);1313 if (!hpo_dp_enc31)1314 return NULL; /* out of memory */1315 1316 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,1317 &hpo_dp_link_enc_regs[inst],1318 &hpo_dp_le_shift, &hpo_dp_le_mask);1319 1320 return &hpo_dp_enc31->base;1321}1322 1323static struct dce_hwseq *dcn31_hwseq_create(1324 struct dc_context *ctx)1325{1326 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1327 1328 if (hws) {1329 hws->ctx = ctx;1330 hws->regs = &hwseq_reg;1331 hws->shifts = &hwseq_shift;1332 hws->masks = &hwseq_mask;1333 }1334 return hws;1335}1336static const struct resource_create_funcs res_create_funcs = {1337 .read_dce_straps = read_dce_straps,1338 .create_audio = dcn31_create_audio,1339 .create_stream_encoder = dcn315_stream_encoder_create,1340 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,1341 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,1342 .create_hwseq = dcn31_hwseq_create,1343};1344 1345static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)1346{1347 unsigned int i;1348 1349 for (i = 0; i < pool->base.stream_enc_count; i++) {1350 if (pool->base.stream_enc[i] != NULL) {1351 if (pool->base.stream_enc[i]->vpg != NULL) {1352 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));1353 pool->base.stream_enc[i]->vpg = NULL;1354 }1355 if (pool->base.stream_enc[i]->afmt != NULL) {1356 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));1357 pool->base.stream_enc[i]->afmt = NULL;1358 }1359 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));1360 pool->base.stream_enc[i] = NULL;1361 }1362 }1363 1364 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {1365 if (pool->base.hpo_dp_stream_enc[i] != NULL) {1366 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {1367 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));1368 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;1369 }1370 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {1371 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));1372 pool->base.hpo_dp_stream_enc[i]->apg = NULL;1373 }1374 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));1375 pool->base.hpo_dp_stream_enc[i] = NULL;1376 }1377 }1378 1379 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {1380 if (pool->base.hpo_dp_link_enc[i] != NULL) {1381 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));1382 pool->base.hpo_dp_link_enc[i] = NULL;1383 }1384 }1385 1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1387 if (pool->base.dscs[i] != NULL)1388 dcn20_dsc_destroy(&pool->base.dscs[i]);1389 }1390 1391 if (pool->base.mpc != NULL) {1392 kfree(TO_DCN20_MPC(pool->base.mpc));1393 pool->base.mpc = NULL;1394 }1395 if (pool->base.hubbub != NULL) {1396 kfree(pool->base.hubbub);1397 pool->base.hubbub = NULL;1398 }1399 for (i = 0; i < pool->base.pipe_count; i++) {1400 if (pool->base.dpps[i] != NULL)1401 dcn31_dpp_destroy(&pool->base.dpps[i]);1402 1403 if (pool->base.ipps[i] != NULL)1404 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);1405 1406 if (pool->base.hubps[i] != NULL) {1407 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));1408 pool->base.hubps[i] = NULL;1409 }1410 1411 if (pool->base.irqs != NULL) {1412 dal_irq_service_destroy(&pool->base.irqs);1413 }1414 }1415 1416 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1417 if (pool->base.engines[i] != NULL)1418 dce110_engine_destroy(&pool->base.engines[i]);1419 if (pool->base.hw_i2cs[i] != NULL) {1420 kfree(pool->base.hw_i2cs[i]);1421 pool->base.hw_i2cs[i] = NULL;1422 }1423 if (pool->base.sw_i2cs[i] != NULL) {1424 kfree(pool->base.sw_i2cs[i]);1425 pool->base.sw_i2cs[i] = NULL;1426 }1427 }1428 1429 for (i = 0; i < pool->base.res_cap->num_opp; i++) {1430 if (pool->base.opps[i] != NULL)1431 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);1432 }1433 1434 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1435 if (pool->base.timing_generators[i] != NULL) {1436 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));1437 pool->base.timing_generators[i] = NULL;1438 }1439 }1440 1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {1442 if (pool->base.dwbc[i] != NULL) {1443 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));1444 pool->base.dwbc[i] = NULL;1445 }1446 if (pool->base.mcif_wb[i] != NULL) {1447 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));1448 pool->base.mcif_wb[i] = NULL;1449 }1450 }1451 1452 for (i = 0; i < pool->base.audio_count; i++) {1453 if (pool->base.audios[i])1454 dce_aud_destroy(&pool->base.audios[i]);1455 }1456 1457 for (i = 0; i < pool->base.clk_src_count; i++) {1458 if (pool->base.clock_sources[i] != NULL) {1459 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);1460 pool->base.clock_sources[i] = NULL;1461 }1462 }1463 1464 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {1465 if (pool->base.mpc_lut[i] != NULL) {1466 dc_3dlut_func_release(pool->base.mpc_lut[i]);1467 pool->base.mpc_lut[i] = NULL;1468 }1469 if (pool->base.mpc_shaper[i] != NULL) {1470 dc_transfer_func_release(pool->base.mpc_shaper[i]);1471 pool->base.mpc_shaper[i] = NULL;1472 }1473 }1474 1475 if (pool->base.dp_clock_source != NULL) {1476 dcn20_clock_source_destroy(&pool->base.dp_clock_source);1477 pool->base.dp_clock_source = NULL;1478 }1479 1480 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1481 if (pool->base.multiple_abms[i] != NULL)1482 dce_abm_destroy(&pool->base.multiple_abms[i]);1483 }1484 1485 if (pool->base.psr != NULL)1486 dmub_psr_destroy(&pool->base.psr);1487 1488 if (pool->base.replay != NULL)1489 dmub_replay_destroy(&pool->base.replay);1490 1491 if (pool->base.dccg != NULL)1492 dcn_dccg_destroy(&pool->base.dccg);1493}1494 1495static struct hubp *dcn31_hubp_create(1496 struct dc_context *ctx,1497 uint32_t inst)1498{1499 struct dcn20_hubp *hubp2 =1500 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);1501 1502 if (!hubp2)1503 return NULL;1504 1505 if (hubp31_construct(hubp2, ctx, inst,1506 &hubp_regs[inst], &hubp_shift, &hubp_mask))1507 return &hubp2->base;1508 1509 BREAK_TO_DEBUGGER();1510 kfree(hubp2);1511 return NULL;1512}1513 1514static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)1515{1516 int i;1517 uint32_t pipe_count = pool->res_cap->num_dwb;1518 1519 for (i = 0; i < pipe_count; i++) {1520 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),1521 GFP_KERNEL);1522 1523 if (!dwbc30) {1524 dm_error("DC: failed to create dwbc30!\n");1525 return false;1526 }1527 1528 dcn30_dwbc_construct(dwbc30, ctx,1529 &dwbc30_regs[i],1530 &dwbc30_shift,1531 &dwbc30_mask,1532 i);1533 1534 pool->dwbc[i] = &dwbc30->base;1535 }1536 return true;1537}1538 1539static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)1540{1541 int i;1542 uint32_t pipe_count = pool->res_cap->num_dwb;1543 1544 for (i = 0; i < pipe_count; i++) {1545 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),1546 GFP_KERNEL);1547 1548 if (!mcif_wb30) {1549 dm_error("DC: failed to create mcif_wb30!\n");1550 return false;1551 }1552 1553 dcn30_mmhubbub_construct(mcif_wb30, ctx,1554 &mcif_wb30_regs[i],1555 &mcif_wb30_shift,1556 &mcif_wb30_mask,1557 i);1558 1559 pool->mcif_wb[i] = &mcif_wb30->base;1560 }1561 return true;1562}1563 1564static struct display_stream_compressor *dcn31_dsc_create(1565 struct dc_context *ctx, uint32_t inst)1566{1567 struct dcn20_dsc *dsc =1568 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);1569 1570 if (!dsc) {1571 BREAK_TO_DEBUGGER();1572 return NULL;1573 }1574 1575 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1576 return &dsc->base;1577}1578 1579static void dcn315_destroy_resource_pool(struct resource_pool **pool)1580{1581 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);1582 1583 dcn315_resource_destruct(dcn31_pool);1584 kfree(dcn31_pool);1585 *pool = NULL;1586}1587 1588static struct clock_source *dcn31_clock_source_create(1589 struct dc_context *ctx,1590 struct dc_bios *bios,1591 enum clock_source_id id,1592 const struct dce110_clk_src_regs *regs,1593 bool dp_clk_src)1594{1595 struct dce110_clk_src *clk_src =1596 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);1597 1598 if (!clk_src)1599 return NULL;1600 1601 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,1602 regs, &cs_shift, &cs_mask)) {1603 clk_src->base.dp_clk_src = dp_clk_src;1604 return &clk_src->base;1605 }1606 1607 kfree(clk_src);1608 BREAK_TO_DEBUGGER();1609 return NULL;1610}1611 1612static bool is_dual_plane(enum surface_pixel_format format)1613{1614 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;1615}1616 1617static int source_format_to_bpp (enum source_format_class SourcePixelFormat)1618{1619 if (SourcePixelFormat == dm_444_64)1620 return 8;1621 else if (SourcePixelFormat == dm_444_16)1622 return 2;1623 else if (SourcePixelFormat == dm_444_8)1624 return 1;1625 else if (SourcePixelFormat == dm_rgbe_alpha)1626 return 5;1627 else if (SourcePixelFormat == dm_420_8)1628 return 3;1629 else if (SourcePixelFormat == dm_420_12)1630 return 6;1631 else1632 return 4;1633}1634 1635static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)1636{1637 int i;1638 struct resource_context *res_ctx = &context->res_ctx;1639 1640 /* Only apply for dual stream scenarios with edp*/1641 if (context->stream_count != 2)1642 return false;1643 if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP)1644 return false;1645 1646 for (i = 0; i < dc->res_pool->pipe_count; i++) {1647 if (!res_ctx->pipe_ctx[i].stream)1648 continue;1649 1650 /*Don't apply if scaling*/1651 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||1652 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||1653 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width1654 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||1655 res_ctx->pipe_ctx[i].plane_state->src_rect.height1656 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))1657 return false;1658 /*Don't apply if MPO to avoid transition issues*/1659 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)1660 return false;1661 }1662 return true;1663}1664 1665static int dcn315_populate_dml_pipes_from_context(1666 struct dc *dc, struct dc_state *context,1667 display_e2e_pipe_params_st *pipes,1668 bool fast_validate)1669{1670 int i, pipe_cnt, crb_idx, crb_pipes;1671 struct resource_context *res_ctx = &context->res_ctx;1672 struct pipe_ctx *pipe = NULL;1673 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;1674 int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;1675 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);1676 1677 DC_FP_START();1678 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);1679 DC_FP_END();1680 1681 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {1682 struct dc_crtc_timing *timing;1683 1684 if (!res_ctx->pipe_ctx[i].stream)1685 continue;1686 pipe = &res_ctx->pipe_ctx[i];1687 timing = &pipe->stream->timing;1688 1689 /*1690 * Immediate flip can be set dynamically after enabling the plane.1691 * We need to require support for immediate flip or underflow can be1692 * intermittently experienced depending on peak b/w requirements.1693 */1694 pipes[pipe_cnt].pipe.src.immediate_flip = true;1695 1696 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;1697 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;1698 pipes[pipe_cnt].pipe.src.dcc_rate = 3;1699 pipes[pipe_cnt].dout.dsc_input_bpc = 0;1700 DC_FP_START();1701 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);1702 if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) {1703 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);1704 /* Ceil to crb segment size */1705 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate(1706 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);1707 1708 if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {1709 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;1710 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);1711 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);1712 1713 /* Minimum 2 segments to allow mpc/odm combine if its used later */1714 if (approx_det_segs_required_for_pstate < 2)1715 approx_det_segs_required_for_pstate = 2;1716 if (split_required)1717 approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2;1718 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate;1719 remaining_det_segs -= approx_det_segs_required_for_pstate;1720 } else1721 remaining_det_segs = -1;1722 crb_pipes++;1723 }1724 DC_FP_END();1725 1726 if (pipes[pipe_cnt].dout.dsc_enable) {1727 switch (timing->display_color_depth) {1728 case COLOR_DEPTH_888:1729 pipes[pipe_cnt].dout.dsc_input_bpc = 8;1730 break;1731 case COLOR_DEPTH_101010:1732 pipes[pipe_cnt].dout.dsc_input_bpc = 10;1733 break;1734 case COLOR_DEPTH_121212:1735 pipes[pipe_cnt].dout.dsc_input_bpc = 12;1736 break;1737 default:1738 ASSERT(0);1739 break;1740 }1741 }1742 pipe_cnt++;1743 }1744 1745 /* Spread remaining unreserved crb evenly among all pipes*/1746 if (pixel_rate_crb) {1747 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {1748 pipe = &res_ctx->pipe_ctx[i];1749 if (!pipe->stream)1750 continue;1751 1752 /* Do not use asymetric crb if not enough for pstate support */1753 if (remaining_det_segs < 0) {1754 pipes[pipe_cnt].pipe.src.det_size_override = 0;1755 pipe_cnt++;1756 continue;1757 }1758 1759 if (!pipe->top_pipe && !pipe->prev_odm_pipe) {1760 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)1761 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);1762 1763 if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0)1764 pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +1765 (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);1766 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) {1767 /* Clamp to 2 pipe split max det segments */1768 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);1769 pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;1770 }1771 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) {1772 /* If we are splitting we must have an even number of segments */1773 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;1774 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;1775 }1776 /* Convert segments into size for DML use */1777 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;1778 1779 crb_idx++;1780 }1781 pipe_cnt++;1782 }1783 }1784 1785 if (pipe_cnt)1786 context->bw_ctx.dml.ip.det_buffer_size_kbytes =1787 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB;1788 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)1789 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;1790 1791 dc->config.enable_4to1MPC = false;1792 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {1793 if (is_dual_plane(pipe->plane_state->format)1794 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {1795 dc->config.enable_4to1MPC = true;1796 context->bw_ctx.dml.ip.det_buffer_size_kbytes =1797 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;1798 } else if (!is_dual_plane(pipe->plane_state->format)1799 && pipe->plane_state->src_rect.width <= 51201800 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {1801 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */1802 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;1803 pipes[0].pipe.src.unbounded_req_mode = true;1804 }1805 }1806 1807 return pipe_cnt;1808}1809 1810static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config)1811{1812 *panel_config = panel_config_defaults;1813}1814 1815static struct dc_cap_funcs cap_funcs = {1816 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap1817};1818 1819static struct resource_funcs dcn315_res_pool_funcs = {1820 .destroy = dcn315_destroy_resource_pool,1821 .link_enc_create = dcn31_link_encoder_create,1822 .link_enc_create_minimal = dcn31_link_enc_create_minimal,1823 .link_encs_assign = link_enc_cfg_link_encs_assign,1824 .link_enc_unassign = link_enc_cfg_link_enc_unassign,1825 .panel_cntl_create = dcn31_panel_cntl_create,1826 .validate_bandwidth = dcn31_validate_bandwidth,1827 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,1828 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a,1829 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context,1830 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,1831 .release_pipe = dcn20_release_pipe,1832 .add_stream_to_ctx = dcn30_add_stream_to_ctx,1833 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1834 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1835 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,1836 .set_mcif_arb_params = dcn31_set_mcif_arb_params,1837 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1838 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,1839 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,1840 .update_bw_bounding_box = dcn315_update_bw_bounding_box,1841 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,1842 .get_panel_config_defaults = dcn315_get_panel_config_defaults,1843};1844 1845static bool dcn315_resource_construct(1846 uint8_t num_virtual_links,1847 struct dc *dc,1848 struct dcn315_resource_pool *pool)1849{1850 int i;1851 struct dc_context *ctx = dc->ctx;1852 struct irq_service_init_data init_data;1853 1854 ctx->dc_bios->regs = &bios_regs;1855 1856 pool->base.res_cap = &res_cap_dcn31;1857 1858 pool->base.funcs = &dcn315_res_pool_funcs;1859 1860 /*************************************************1861 * Resource + asic cap harcoding *1862 *************************************************/1863 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;1864 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;1865 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;1866 dc->caps.max_downscale_ratio = 600;1867 dc->caps.i2c_speed_in_khz = 100;1868 dc->caps.i2c_speed_in_khz_hdcp = 100;1869 dc->caps.max_cursor_size = 256;1870 dc->caps.min_horizontal_blanking_period = 80;1871 dc->caps.dmdata_alloc_size = 2048;1872 dc->caps.max_slave_planes = 2;1873 dc->caps.max_slave_yuv_planes = 2;1874 dc->caps.max_slave_rgb_planes = 2;1875 dc->caps.post_blend_color_processing = true;1876 dc->caps.force_dp_tps4_for_cp2520 = true;1877 if (dc->config.forceHBR2CP2520)1878 dc->caps.force_dp_tps4_for_cp2520 = false;1879 dc->caps.dp_hpo = true;1880 dc->caps.dp_hdmi21_pcon_support = true;1881 dc->caps.edp_dsc_support = true;1882 dc->caps.extended_aux_timeout_support = true;1883 dc->caps.dmcub_support = true;1884 dc->caps.is_apu = true;1885 1886 /* Color pipeline capabilities */1887 dc->caps.color.dpp.dcn_arch = 1;1888 dc->caps.color.dpp.input_lut_shared = 0;1889 dc->caps.color.dpp.icsc = 1;1890 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr1891 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1892 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1893 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;1894 dc->caps.color.dpp.dgam_rom_caps.pq = 1;1895 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;1896 dc->caps.color.dpp.post_csc = 1;1897 dc->caps.color.dpp.gamma_corr = 1;1898 dc->caps.color.dpp.dgam_rom_for_yuv = 0;1899 1900 dc->caps.color.dpp.hw_3d_lut = 1;1901 dc->caps.color.dpp.ogam_ram = 1;1902 // no OGAM ROM on DCN3011903 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1904 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1905 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1906 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1907 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1908 dc->caps.color.dpp.ocsc = 0;1909 1910 dc->caps.color.mpc.gamut_remap = 1;1911 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //21912 dc->caps.color.mpc.ogam_ram = 1;1913 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1914 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1915 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1916 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1917 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1918 dc->caps.color.mpc.ocsc = 1;1919 1920 /* read VBIOS LTTPR caps */1921 {1922 if (ctx->dc_bios->funcs->get_lttpr_caps) {1923 enum bp_result bp_query_result;1924 uint8_t is_vbios_lttpr_enable = 0;1925 1926 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);1927 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;1928 }1929 1930 /* interop bit is implicit */1931 {1932 dc->caps.vbios_lttpr_aware = true;1933 }1934 }1935 1936 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1937 dc->debug = debug_defaults_drv;1938 1939 // Init the vm_helper1940 if (dc->vm_helper)1941 vm_helper_init(dc->vm_helper, 16);1942 1943 /*************************************************1944 * Create resources *1945 *************************************************/1946 1947 /* Clock Sources for Pixel Clock*/1948 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =1949 dcn31_clock_source_create(ctx, ctx->dc_bios,1950 CLOCK_SOURCE_COMBO_PHY_PLL0,1951 &clk_src_regs[0], false);1952 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =1953 dcn31_clock_source_create(ctx, ctx->dc_bios,1954 CLOCK_SOURCE_COMBO_PHY_PLL1,1955 &clk_src_regs[1], false);1956 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =1957 dcn31_clock_source_create(ctx, ctx->dc_bios,1958 CLOCK_SOURCE_COMBO_PHY_PLL2,1959 &clk_src_regs[2], false);1960 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =1961 dcn31_clock_source_create(ctx, ctx->dc_bios,1962 CLOCK_SOURCE_COMBO_PHY_PLL3,1963 &clk_src_regs[3], false);1964 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =1965 dcn31_clock_source_create(ctx, ctx->dc_bios,1966 CLOCK_SOURCE_COMBO_PHY_PLL4,1967 &clk_src_regs[4], false);1968 1969 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;1970 1971 /* todo: not reuse phy_pll registers */1972 pool->base.dp_clock_source =1973 dcn31_clock_source_create(ctx, ctx->dc_bios,1974 CLOCK_SOURCE_ID_DP_DTO,1975 &clk_src_regs[0], true);1976 1977 for (i = 0; i < pool->base.clk_src_count; i++) {1978 if (pool->base.clock_sources[i] == NULL) {1979 dm_error("DC: failed to create clock sources!\n");1980 BREAK_TO_DEBUGGER();1981 goto create_fail;1982 }1983 }1984 1985 /* TODO: DCCG */1986 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1987 if (pool->base.dccg == NULL) {1988 dm_error("DC: failed to create dccg!\n");1989 BREAK_TO_DEBUGGER();1990 goto create_fail;1991 }1992 1993 /* TODO: IRQ */1994 init_data.ctx = dc->ctx;1995 pool->base.irqs = dal_irq_service_dcn315_create(&init_data);1996 if (!pool->base.irqs)1997 goto create_fail;1998 1999 /* HUBBUB */2000 pool->base.hubbub = dcn31_hubbub_create(ctx);2001 if (pool->base.hubbub == NULL) {2002 BREAK_TO_DEBUGGER();2003 dm_error("DC: failed to create hubbub!\n");2004 goto create_fail;2005 }2006 2007 /* HUBPs, DPPs, OPPs and TGs */2008 for (i = 0; i < pool->base.pipe_count; i++) {2009 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);2010 if (pool->base.hubps[i] == NULL) {2011 BREAK_TO_DEBUGGER();2012 dm_error(2013 "DC: failed to create hubps!\n");2014 goto create_fail;2015 }2016 2017 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);2018 if (pool->base.dpps[i] == NULL) {2019 BREAK_TO_DEBUGGER();2020 dm_error(2021 "DC: failed to create dpps!\n");2022 goto create_fail;2023 }2024 }2025 2026 for (i = 0; i < pool->base.res_cap->num_opp; i++) {2027 pool->base.opps[i] = dcn31_opp_create(ctx, i);2028 if (pool->base.opps[i] == NULL) {2029 BREAK_TO_DEBUGGER();2030 dm_error(2031 "DC: failed to create output pixel processor!\n");2032 goto create_fail;2033 }2034 }2035 2036 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2037 pool->base.timing_generators[i] = dcn31_timing_generator_create(2038 ctx, i);2039 if (pool->base.timing_generators[i] == NULL) {2040 BREAK_TO_DEBUGGER();2041 dm_error("DC: failed to create tg!\n");2042 goto create_fail;2043 }2044 }2045 pool->base.timing_generator_count = i;2046 2047 /* PSR */2048 pool->base.psr = dmub_psr_create(ctx);2049 if (pool->base.psr == NULL) {2050 dm_error("DC: failed to create psr obj!\n");2051 BREAK_TO_DEBUGGER();2052 goto create_fail;2053 }2054 2055 /* Replay */2056 pool->base.replay = dmub_replay_create(ctx);2057 if (pool->base.replay == NULL) {2058 dm_error("DC: failed to create replay obj!\n");2059 BREAK_TO_DEBUGGER();2060 goto create_fail;2061 }2062 2063 /* ABM */2064 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2065 pool->base.multiple_abms[i] = dmub_abm_create(ctx,2066 &abm_regs[i],2067 &abm_shift,2068 &abm_mask);2069 if (pool->base.multiple_abms[i] == NULL) {2070 dm_error("DC: failed to create abm for pipe %d!\n", i);2071 BREAK_TO_DEBUGGER();2072 goto create_fail;2073 }2074 }2075 2076 /* MPC and DSC */2077 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);2078 if (pool->base.mpc == NULL) {2079 BREAK_TO_DEBUGGER();2080 dm_error("DC: failed to create mpc!\n");2081 goto create_fail;2082 }2083 2084 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {2085 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);2086 if (pool->base.dscs[i] == NULL) {2087 BREAK_TO_DEBUGGER();2088 dm_error("DC: failed to create display stream compressor %d!\n", i);2089 goto create_fail;2090 }2091 }2092 2093 /* DWB and MMHUBBUB */2094 if (!dcn31_dwbc_create(ctx, &pool->base)) {2095 BREAK_TO_DEBUGGER();2096 dm_error("DC: failed to create dwbc!\n");2097 goto create_fail;2098 }2099 2100 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {2101 BREAK_TO_DEBUGGER();2102 dm_error("DC: failed to create mcif_wb!\n");2103 goto create_fail;2104 }2105 2106 /* AUX and I2C */2107 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {2108 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);2109 if (pool->base.engines[i] == NULL) {2110 BREAK_TO_DEBUGGER();2111 dm_error(2112 "DC:failed to create aux engine!!\n");2113 goto create_fail;2114 }2115 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);2116 if (pool->base.hw_i2cs[i] == NULL) {2117 BREAK_TO_DEBUGGER();2118 dm_error(2119 "DC:failed to create hw i2c!!\n");2120 goto create_fail;2121 }2122 pool->base.sw_i2cs[i] = NULL;2123 }2124 2125 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */2126 if (!resource_construct(num_virtual_links, dc, &pool->base,2127 &res_create_funcs))2128 goto create_fail;2129 2130 /* HW Sequencer and Plane caps */2131 dcn31_hw_sequencer_construct(dc);2132 2133 dc->caps.max_planes = pool->base.pipe_count;2134 2135 for (i = 0; i < dc->caps.max_planes; ++i)2136 dc->caps.planes[i] = plane_cap;2137 2138 dc->cap_funcs = cap_funcs;2139 2140 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;2141 2142 return true;2143 2144create_fail:2145 2146 dcn315_resource_destruct(pool);2147 2148 return false;2149}2150 2151struct resource_pool *dcn315_create_resource_pool(2152 const struct dc_init_data *init_data,2153 struct dc *dc)2154{2155 struct dcn315_resource_pool *pool =2156 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL);2157 2158 if (!pool)2159 return NULL;2160 2161 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))2162 return &pool->base;2163 2164 BREAK_TO_DEBUGGER();2165 kfree(pool);2166 return NULL;2167}2168