2072 lines · c
1// SPDX-License-Identifier: MIT2/*3 * Copyright 2019 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dm_services.h"28#include "dc.h"29 30#include "dcn32/dcn32_init.h"31 32#include "resource.h"33#include "include/irq_service_interface.h"34#include "dcn32/dcn32_resource.h"35#include "dcn321_resource.h"36 37#include "dcn20/dcn20_resource.h"38#include "dcn30/dcn30_resource.h"39 40#include "dml/dcn321/dcn321_fpu.h"41 42#include "dcn10/dcn10_ipp.h"43#include "dcn30/dcn30_hubbub.h"44#include "dcn31/dcn31_hubbub.h"45#include "dcn32/dcn32_hubbub.h"46#include "dcn32/dcn32_mpc.h"47#include "dcn32/dcn32_hubp.h"48#include "irq/dcn32/irq_service_dcn32.h"49#include "dcn32/dcn32_dpp.h"50#include "dcn32/dcn32_optc.h"51#include "dcn20/dcn20_hwseq.h"52#include "dcn30/dcn30_hwseq.h"53#include "dce110/dce110_hwseq.h"54#include "dcn30/dcn30_opp.h"55#include "dcn20/dcn20_dsc.h"56#include "dcn30/dcn30_vpg.h"57#include "dcn30/dcn30_afmt.h"58#include "dcn30/dcn30_dio_stream_encoder.h"59#include "dcn32/dcn32_dio_stream_encoder.h"60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"61#include "dcn31/dcn31_hpo_dp_link_encoder.h"62#include "dcn32/dcn32_hpo_dp_link_encoder.h"63#include "dcn31/dcn31_apg.h"64#include "dcn31/dcn31_dio_link_encoder.h"65#include "dcn32/dcn32_dio_link_encoder.h"66#include "dcn321/dcn321_dio_link_encoder.h"67#include "dce/dce_clock_source.h"68#include "dce/dce_audio.h"69#include "dce/dce_hwseq.h"70#include "clk_mgr.h"71#include "virtual/virtual_stream_encoder.h"72#include "dml/display_mode_vba.h"73#include "dcn32/dcn32_dccg.h"74#include "dcn10/dcn10_resource.h"75#include "link.h"76#include "dcn31/dcn31_panel_cntl.h"77 78#include "dcn30/dcn30_dwb.h"79#include "dcn32/dcn32_mmhubbub.h"80 81#include "dcn/dcn_3_2_1_offset.h"82#include "dcn/dcn_3_2_1_sh_mask.h"83#include "nbio/nbio_4_3_0_offset.h"84 85#include "reg_helper.h"86#include "dce/dmub_abm.h"87#include "dce/dmub_psr.h"88#include "dce/dce_aux.h"89#include "dce/dce_i2c.h"90 91#include "dml/dcn30/display_mode_vba_30.h"92#include "vm_helper.h"93#include "dcn20/dcn20_vmid.h"94 95#include "dc_state_priv.h"96 97#define DC_LOGGER_INIT(logger)98 99enum dcn321_clk_src_array_id {100 DCN321_CLK_SRC_PLL0,101 DCN321_CLK_SRC_PLL1,102 DCN321_CLK_SRC_PLL2,103 DCN321_CLK_SRC_PLL3,104 DCN321_CLK_SRC_PLL4,105 DCN321_CLK_SRC_TOTAL106};107 108/* begin *********************109 * macros to expend register list macro defined in HW object header file110 */111 112/* DCN */113#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]114 115#define BASE(seg) BASE_INNER(seg)116 117#define SR(reg_name)\118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \119 reg ## reg_name120#define SR_ARR(reg_name, id)\121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \122 reg ## reg_name123#define SR_ARR_INIT(reg_name, id, value)\124 REG_STRUCT[id].reg_name = value125 126#define SRI(reg_name, block, id)\127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \128 reg ## block ## id ## _ ## reg_name129 130#define SRI_ARR(reg_name, block, id)\131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \132 reg ## block ## id ## _ ## reg_name133 134#define SR_ARR_I2C(reg_name, id) \135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name136 137#define SRI_ARR_I2C(reg_name, block, id)\138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \139 reg ## block ## id ## _ ## reg_name140 141#define SRI_ARR_ALPHABET(reg_name, block, index, id)\142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \143 reg ## block ## id ## _ ## reg_name144 145#define SRI2(reg_name, block, id)\146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \147 reg ## reg_name148#define SRI2_ARR(reg_name, block, id)\149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \150 reg ## reg_name151 152#define SRIR(var_name, reg_name, block, id)\153 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \154 reg ## block ## id ## _ ## reg_name155 156#define SRII(reg_name, block, id)\157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \158 reg ## block ## id ## _ ## reg_name159 160#define SRII_ARR_2(reg_name, block, id, inst)\161 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \162 reg ## block ## id ## _ ## reg_name163 164#define SRII_MPC_RMU(reg_name, block, id)\165 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \166 reg ## block ## id ## _ ## reg_name167 168#define SRII_DWB(reg_name, temp_name, block, id)\169 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \170 reg ## block ## id ## _ ## temp_name171 172#define DCCG_SRII(reg_name, block, id)\173 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \174 reg ## block ## id ## _ ## reg_name175 176#define SF_DWB2(reg_name, block, id, field_name, post_fix) \177 .field_name = reg_name ## __ ## field_name ## post_fix178 179#define VUPDATE_SRII(reg_name, block, id)\180 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \181 reg ## reg_name ## _ ## block ## id182 183/* NBIO */184#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]185 186#define NBIO_BASE(seg) \187 NBIO_BASE_INNER(seg)188 189#define NBIO_SR(reg_name)\190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \191 regBIF_BX0_ ## reg_name192#define NBIO_SR_ARR(reg_name, id)\193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \194 regBIF_BX0_ ## reg_name195 196#define CTX ctx197#define REG(reg_name) \198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)199 200static struct bios_registers bios_regs;201 202#define bios_regs_init() \203 ( \204 NBIO_SR(BIOS_SCRATCH_3),\205 NBIO_SR(BIOS_SCRATCH_6)\206 )207 208#define clk_src_regs_init(index, pllid)\209 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)210 211static struct dce110_clk_src_regs clk_src_regs[5];212 213static const struct dce110_clk_src_shift cs_shift = {214 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)215};216 217static const struct dce110_clk_src_mask cs_mask = {218 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)219};220 221#define abm_regs_init(id)\222 ABM_DCN32_REG_LIST_RI(id)223 224static struct dce_abm_registers abm_regs[4];225 226static const struct dce_abm_shift abm_shift = {227 ABM_MASK_SH_LIST_DCN32(__SHIFT)228};229 230static const struct dce_abm_mask abm_mask = {231 ABM_MASK_SH_LIST_DCN32(_MASK)232};233 234#define audio_regs_init(id)\235 AUD_COMMON_REG_LIST_RI(id)236 237static struct dce_audio_registers audio_regs[5];238 239#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\242 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)243 244static const struct dce_audio_shift audio_shift = {245 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)246};247 248static const struct dce_audio_mask audio_mask = {249 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)250};251 252#define vpg_regs_init(id)\253 VPG_DCN3_REG_LIST_RI(id)254 255static struct dcn30_vpg_registers vpg_regs[10];256 257static const struct dcn30_vpg_shift vpg_shift = {258 DCN3_VPG_MASK_SH_LIST(__SHIFT)259};260 261static const struct dcn30_vpg_mask vpg_mask = {262 DCN3_VPG_MASK_SH_LIST(_MASK)263};264 265#define afmt_regs_init(id)\266 AFMT_DCN3_REG_LIST_RI(id)267 268static struct dcn30_afmt_registers afmt_regs[6];269 270static const struct dcn30_afmt_shift afmt_shift = {271 DCN3_AFMT_MASK_SH_LIST(__SHIFT)272};273 274static const struct dcn30_afmt_mask afmt_mask = {275 DCN3_AFMT_MASK_SH_LIST(_MASK)276};277 278#define apg_regs_init(id)\279 APG_DCN31_REG_LIST_RI(id)280 281static struct dcn31_apg_registers apg_regs[4];282 283static const struct dcn31_apg_shift apg_shift = {284 DCN31_APG_MASK_SH_LIST(__SHIFT)285};286 287static const struct dcn31_apg_mask apg_mask = {288 DCN31_APG_MASK_SH_LIST(_MASK)289};290 291#define stream_enc_regs_init(id)\292 SE_DCN32_REG_LIST_RI(id)293 294static struct dcn10_stream_enc_registers stream_enc_regs[5];295 296static const struct dcn10_stream_encoder_shift se_shift = {297 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)298};299 300static const struct dcn10_stream_encoder_mask se_mask = {301 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)302};303 304 305#define aux_regs_init(id)\306 DCN2_AUX_REG_LIST_RI(id)307 308static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];309 310#define hpd_regs_init(id)\311 HPD_REG_LIST_RI(id)312 313static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];314 315#define link_regs_init(id, phyid)\316 ( \317 LE_DCN31_REG_LIST_RI(id), \318 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\319 )320 /*DPCS_DCN31_REG_LIST(id),*/ \321 322static struct dcn10_link_enc_registers link_enc_regs[5];323 324static const struct dcn10_link_enc_shift le_shift = {325 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \326// DPCS_DCN31_MASK_SH_LIST(__SHIFT)327};328 329static const struct dcn10_link_enc_mask le_mask = {330 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \331// DPCS_DCN31_MASK_SH_LIST(_MASK)332};333 334#define hpo_dp_stream_encoder_reg_init(id)\335 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)336 337static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];338 339static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)341};342 343static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {344 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)345};346 347 348#define hpo_dp_link_encoder_reg_init(id)\349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/354 355static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];356 357static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)359};360 361static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {362 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)363};364 365#define dpp_regs_init(id)\366 DPP_REG_LIST_DCN30_COMMON_RI(id)367 368static struct dcn3_dpp_registers dpp_regs[4];369 370static const struct dcn3_dpp_shift tf_shift = {371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)372};373 374static const struct dcn3_dpp_mask tf_mask = {375 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)376};377 378 379#define opp_regs_init(id)\380 OPP_REG_LIST_DCN30_RI(id)381 382static struct dcn20_opp_registers opp_regs[4];383 384static const struct dcn20_opp_shift opp_shift = {385 OPP_MASK_SH_LIST_DCN20(__SHIFT)386};387 388static const struct dcn20_opp_mask opp_mask = {389 OPP_MASK_SH_LIST_DCN20(_MASK)390};391 392#define aux_engine_regs_init(id) \393 ( \394 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \395 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \396 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\398 )399 400static struct dce110_aux_registers aux_engine_regs[5];401 402static const struct dce110_aux_registers_shift aux_shift = {403 DCN_AUX_MASK_SH_LIST(__SHIFT)404};405 406static const struct dce110_aux_registers_mask aux_mask = {407 DCN_AUX_MASK_SH_LIST(_MASK)408};409 410#define dwbc_regs_dcn3_init(id)\411 DWBC_COMMON_REG_LIST_DCN30_RI(id)412 413static struct dcn30_dwbc_registers dwbc30_regs[1];414 415static const struct dcn30_dwbc_shift dwbc30_shift = {416 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)417};418 419static const struct dcn30_dwbc_mask dwbc30_mask = {420 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)421};422 423#define mcif_wb_regs_dcn3_init(id)\424 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)425 426static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];427 428static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {429 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)430};431 432static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {433 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)434};435 436#define dsc_regsDCN20_init(id)\437 DSC_REG_LIST_DCN20_RI(id)438 439static struct dcn20_dsc_registers dsc_regs[4];440 441static const struct dcn20_dsc_shift dsc_shift = {442 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)443};444 445static const struct dcn20_dsc_mask dsc_mask = {446 DSC_REG_LIST_SH_MASK_DCN20(_MASK)447};448 449static struct dcn30_mpc_registers mpc_regs;450#define dcn_mpc_regs_init()\451 MPC_REG_LIST_DCN3_2_RI(0),\452 MPC_REG_LIST_DCN3_2_RI(1),\453 MPC_REG_LIST_DCN3_2_RI(2),\454 MPC_REG_LIST_DCN3_2_RI(3),\455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\459 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)460 461static const struct dcn30_mpc_shift mpc_shift = {462 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)463};464 465static const struct dcn30_mpc_mask mpc_mask = {466 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)467};468 469#define optc_regs_init(id)\470 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)471 472static struct dcn_optc_registers optc_regs[4];473 474static const struct dcn_optc_shift optc_shift = {475 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)476};477 478static const struct dcn_optc_mask optc_mask = {479 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)480};481 482#define hubp_regs_init(id) \483 HUBP_REG_LIST_DCN32_RI(id)484 485static struct dcn_hubp2_registers hubp_regs[4];486 487static const struct dcn_hubp2_shift hubp_shift = {488 HUBP_MASK_SH_LIST_DCN32(__SHIFT)489};490 491static const struct dcn_hubp2_mask hubp_mask = {492 HUBP_MASK_SH_LIST_DCN32(_MASK)493};494 495static struct dcn_hubbub_registers hubbub_reg;496#define hubbub_reg_init()\497 HUBBUB_REG_LIST_DCN32_RI(0)498 499static const struct dcn_hubbub_shift hubbub_shift = {500 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)501};502 503static const struct dcn_hubbub_mask hubbub_mask = {504 HUBBUB_MASK_SH_LIST_DCN32(_MASK)505};506 507static struct dccg_registers dccg_regs;508 509#define dccg_regs_init()\510 DCCG_REG_LIST_DCN32_RI()511 512static const struct dccg_shift dccg_shift = {513 DCCG_MASK_SH_LIST_DCN32(__SHIFT)514};515 516static const struct dccg_mask dccg_mask = {517 DCCG_MASK_SH_LIST_DCN32(_MASK)518};519 520 521#define SRII2(reg_name_pre, reg_name_post, id)\522 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \523 ## id ## _ ## reg_name_post ## _BASE_IDX) + \524 reg ## reg_name_pre ## id ## _ ## reg_name_post525 526 527#define HWSEQ_DCN32_REG_LIST()\528 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \529 SR(DIO_MEM_PWR_CTRL), \530 SR(ODM_MEM_PWR_CTRL3), \531 SR(MMHUBBUB_MEM_PWR_CNTL), \532 SR(DCCG_GATE_DISABLE_CNTL), \533 SR(DCCG_GATE_DISABLE_CNTL2), \534 SR(DCFCLK_CNTL),\535 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \536 SRII(PIXEL_RATE_CNTL, OTG, 0), \537 SRII(PIXEL_RATE_CNTL, OTG, 1),\538 SRII(PIXEL_RATE_CNTL, OTG, 2),\539 SRII(PIXEL_RATE_CNTL, OTG, 3),\540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\544 SR(MICROSECOND_TIME_BASE_DIV), \545 SR(MILLISECOND_TIME_BASE_DIV), \546 SR(DISPCLK_FREQ_CHANGE_CNTL), \547 SR(RBBMIF_TIMEOUT_DIS), \548 SR(RBBMIF_TIMEOUT_DIS_2), \549 SR(DCHUBBUB_CRC_CTRL), \550 SR(DPP_TOP0_DPP_CRC_CTRL), \551 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \552 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \553 SR(MPC_CRC_CTRL), \554 SR(MPC_CRC_RESULT_GB), \555 SR(MPC_CRC_RESULT_C), \556 SR(MPC_CRC_RESULT_AR), \557 SR(DOMAIN0_PG_CONFIG), \558 SR(DOMAIN1_PG_CONFIG), \559 SR(DOMAIN2_PG_CONFIG), \560 SR(DOMAIN3_PG_CONFIG), \561 SR(DOMAIN16_PG_CONFIG), \562 SR(DOMAIN17_PG_CONFIG), \563 SR(DOMAIN18_PG_CONFIG), \564 SR(DOMAIN19_PG_CONFIG), \565 SR(DOMAIN0_PG_STATUS), \566 SR(DOMAIN1_PG_STATUS), \567 SR(DOMAIN2_PG_STATUS), \568 SR(DOMAIN3_PG_STATUS), \569 SR(DOMAIN16_PG_STATUS), \570 SR(DOMAIN17_PG_STATUS), \571 SR(DOMAIN18_PG_STATUS), \572 SR(DOMAIN19_PG_STATUS), \573 SR(D1VGA_CONTROL), \574 SR(D2VGA_CONTROL), \575 SR(D3VGA_CONTROL), \576 SR(D4VGA_CONTROL), \577 SR(D5VGA_CONTROL), \578 SR(D6VGA_CONTROL), \579 SR(DC_IP_REQUEST_CNTL), \580 SR(AZALIA_AUDIO_DTO), \581 SR(AZALIA_CONTROLLER_CLOCK_GATING)582 583static struct dce_hwseq_registers hwseq_reg;584 585#define hwseq_reg_init()\586 HWSEQ_DCN32_REG_LIST()587 588#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\589 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \590 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \591 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \595 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \597 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \599 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \601 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \603 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \605 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \607 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \608 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \609 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \611 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \612 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \613 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \614 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \616 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \617 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \620 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)621 622static const struct dce_hwseq_shift hwseq_shift = {623 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)624};625 626static const struct dce_hwseq_mask hwseq_mask = {627 HWSEQ_DCN32_MASK_SH_LIST(_MASK)628};629#define vmid_regs_init(id)\630 DCN20_VMID_REG_LIST_RI(id)631 632static struct dcn_vmid_registers vmid_regs[16];633 634static const struct dcn20_vmid_shift vmid_shifts = {635 DCN20_VMID_MASK_SH_LIST(__SHIFT)636};637 638static const struct dcn20_vmid_mask vmid_masks = {639 DCN20_VMID_MASK_SH_LIST(_MASK)640};641 642static const struct resource_caps res_cap_dcn321 = {643 .num_timing_generator = 4,644 .num_opp = 4,645 .num_video_plane = 4,646 .num_audio = 5,647 .num_stream_encoder = 5,648 .num_hpo_dp_stream_encoder = 4,649 .num_hpo_dp_link_encoder = 2,650 .num_pll = 5,651 .num_dwb = 1,652 .num_ddc = 5,653 .num_vmid = 16,654 .num_mpc_3dlut = 4,655 .num_dsc = 4,656};657 658static const struct dc_plane_cap plane_cap = {659 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,660 .per_pixel_alpha = true,661 662 .pixel_format_support = {663 .argb8888 = true,664 .nv12 = true,665 .fp16 = true,666 .p010 = true,667 .ayuv = false,668 },669 670 .max_upscale_factor = {671 .argb8888 = 16000,672 .nv12 = 16000,673 .fp16 = 16000674 },675 676 // 6:1 downscaling ratio: 1000/6 = 166.666677 .max_downscale_factor = {678 .argb8888 = 167,679 .nv12 = 167,680 .fp16 = 167681 },682 64,683 64684};685 686static const struct dc_debug_options debug_defaults_drv = {687 .disable_dmcu = true,688 .force_abm_enable = false,689 .timing_trace = false,690 .clock_trace = true,691 .disable_pplib_clock_request = false,692 .pipe_split_policy = MPC_SPLIT_AVOID,693 .force_single_disp_pipe_split = false,694 .disable_dcc = DCC_ENABLE,695 .vsr_support = true,696 .performance_trace = false,697 .max_downscale_src_width = 7680,/*upto 8K*/698 .disable_pplib_wm_range = false,699 .scl_reset_length10 = true,700 .sanity_checks = false,701 .underflow_assert_delay_us = 0xFFFFFFFF,702 .dwb_fi_phase = -1, // -1 = disable,703 .dmub_command_table = true,704 .enable_mem_low_power = {705 .bits = {706 .vga = false,707 .i2c = false,708 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled709 .dscl = false,710 .cm = false,711 .mpc = false,712 .optc = true,713 }714 },715 .use_max_lb = true,716 .force_disable_subvp = false,717 .exit_idle_opt_for_cursor_updates = true,718 .enable_single_display_2to1_odm_policy = true,719 720 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/721 .enable_double_buffered_dsc_pg_support = true,722 .enable_dp_dig_pixel_rate_div_policy = 1,723 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"724 .alloc_extra_way_for_cursor = true,725 .min_prefetch_in_strobe_ns = 60000, // 60us726 .disable_unbounded_requesting = false,727 .override_dispclk_programming = true,728 .disable_fpo_optimizations = false,729 .fpo_vactive_margin_us = 2000, // 2000us730 .disable_fpo_vactive = false,731 .disable_boot_optimizations = false,732 .disable_subvp_high_refresh = false,733 .fpo_vactive_min_active_margin_us = 200,734 .fpo_vactive_max_blank_us = 1000,735 .enable_legacy_fast_update = false,736 .disable_dc_mode_overwrite = true,737 .using_dml2 = false,738};739 740static struct dce_aux *dcn321_aux_engine_create(741 struct dc_context *ctx,742 uint32_t inst)743{744 struct aux_engine_dce110 *aux_engine =745 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);746 747 if (!aux_engine)748 return NULL;749 750#undef REG_STRUCT751#define REG_STRUCT aux_engine_regs752 aux_engine_regs_init(0),753 aux_engine_regs_init(1),754 aux_engine_regs_init(2),755 aux_engine_regs_init(3),756 aux_engine_regs_init(4);757 758 dce110_aux_engine_construct(aux_engine, ctx, inst,759 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,760 &aux_engine_regs[inst],761 &aux_mask,762 &aux_shift,763 ctx->dc->caps.extended_aux_timeout_support);764 765 return &aux_engine->base;766}767#define i2c_inst_regs_init(id)\768 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)769 770static struct dce_i2c_registers i2c_hw_regs[5];771 772static const struct dce_i2c_shift i2c_shifts = {773 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)774};775 776static const struct dce_i2c_mask i2c_masks = {777 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)778};779 780static struct dce_i2c_hw *dcn321_i2c_hw_create(781 struct dc_context *ctx,782 uint32_t inst)783{784 struct dce_i2c_hw *dce_i2c_hw =785 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);786 787 if (!dce_i2c_hw)788 return NULL;789 790#undef REG_STRUCT791#define REG_STRUCT i2c_hw_regs792 i2c_inst_regs_init(1),793 i2c_inst_regs_init(2),794 i2c_inst_regs_init(3),795 i2c_inst_regs_init(4),796 i2c_inst_regs_init(5);797 798 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,799 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);800 801 return dce_i2c_hw;802}803 804static struct clock_source *dcn321_clock_source_create(805 struct dc_context *ctx,806 struct dc_bios *bios,807 enum clock_source_id id,808 const struct dce110_clk_src_regs *regs,809 bool dp_clk_src)810{811 struct dce110_clk_src *clk_src =812 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);813 814 if (!clk_src)815 return NULL;816 817 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,818 regs, &cs_shift, &cs_mask)) {819 clk_src->base.dp_clk_src = dp_clk_src;820 return &clk_src->base;821 }822 823 kfree(clk_src);824 BREAK_TO_DEBUGGER();825 return NULL;826}827 828static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)829{830 int i;831 832 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),833 GFP_KERNEL);834 835 if (!hubbub2)836 return NULL;837 838#undef REG_STRUCT839#define REG_STRUCT hubbub_reg840 hubbub_reg_init();841 842#undef REG_STRUCT843#define REG_STRUCT vmid_regs844 vmid_regs_init(0),845 vmid_regs_init(1),846 vmid_regs_init(2),847 vmid_regs_init(3),848 vmid_regs_init(4),849 vmid_regs_init(5),850 vmid_regs_init(6),851 vmid_regs_init(7),852 vmid_regs_init(8),853 vmid_regs_init(9),854 vmid_regs_init(10),855 vmid_regs_init(11),856 vmid_regs_init(12),857 vmid_regs_init(13),858 vmid_regs_init(14),859 vmid_regs_init(15);860 861 hubbub32_construct(hubbub2, ctx,862 &hubbub_reg,863 &hubbub_shift,864 &hubbub_mask,865 ctx->dc->dml.ip.det_buffer_size_kbytes,866 ctx->dc->dml.ip.pixel_chunk_size_kbytes,867 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);868 869 870 for (i = 0; i < res_cap_dcn321.num_vmid; i++) {871 struct dcn20_vmid *vmid = &hubbub2->vmid[i];872 873 vmid->ctx = ctx;874 875 vmid->regs = &vmid_regs[i];876 vmid->shifts = &vmid_shifts;877 vmid->masks = &vmid_masks;878 }879 880 return &hubbub2->base;881}882 883static struct hubp *dcn321_hubp_create(884 struct dc_context *ctx,885 uint32_t inst)886{887 struct dcn20_hubp *hubp2 =888 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);889 890 if (!hubp2)891 return NULL;892 893#undef REG_STRUCT894#define REG_STRUCT hubp_regs895 hubp_regs_init(0),896 hubp_regs_init(1),897 hubp_regs_init(2),898 hubp_regs_init(3);899 900 if (hubp32_construct(hubp2, ctx, inst,901 &hubp_regs[inst], &hubp_shift, &hubp_mask))902 return &hubp2->base;903 904 BREAK_TO_DEBUGGER();905 kfree(hubp2);906 return NULL;907}908 909static void dcn321_dpp_destroy(struct dpp **dpp)910{911 kfree(TO_DCN30_DPP(*dpp));912 *dpp = NULL;913}914 915static struct dpp *dcn321_dpp_create(916 struct dc_context *ctx,917 uint32_t inst)918{919 struct dcn3_dpp *dpp3 =920 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);921 922 if (!dpp3)923 return NULL;924 925#undef REG_STRUCT926#define REG_STRUCT dpp_regs927 dpp_regs_init(0),928 dpp_regs_init(1),929 dpp_regs_init(2),930 dpp_regs_init(3);931 932 if (dpp32_construct(dpp3, ctx, inst,933 &dpp_regs[inst], &tf_shift, &tf_mask))934 return &dpp3->base;935 936 BREAK_TO_DEBUGGER();937 kfree(dpp3);938 return NULL;939}940 941static struct mpc *dcn321_mpc_create(942 struct dc_context *ctx,943 int num_mpcc,944 int num_rmu)945{946 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),947 GFP_KERNEL);948 949 if (!mpc30)950 return NULL;951 952#undef REG_STRUCT953#define REG_STRUCT mpc_regs954 dcn_mpc_regs_init();955 956 dcn32_mpc_construct(mpc30, ctx,957 &mpc_regs,958 &mpc_shift,959 &mpc_mask,960 num_mpcc,961 num_rmu);962 963 return &mpc30->base;964}965 966static struct output_pixel_processor *dcn321_opp_create(967 struct dc_context *ctx, uint32_t inst)968{969 struct dcn20_opp *opp2 =970 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);971 972 if (!opp2) {973 BREAK_TO_DEBUGGER();974 return NULL;975 }976 977#undef REG_STRUCT978#define REG_STRUCT opp_regs979 opp_regs_init(0),980 opp_regs_init(1),981 opp_regs_init(2),982 opp_regs_init(3);983 984 dcn20_opp_construct(opp2, ctx, inst,985 &opp_regs[inst], &opp_shift, &opp_mask);986 return &opp2->base;987}988 989 990static struct timing_generator *dcn321_timing_generator_create(991 struct dc_context *ctx,992 uint32_t instance)993{994 struct optc *tgn10 =995 kzalloc(sizeof(struct optc), GFP_KERNEL);996 997 if (!tgn10)998 return NULL;999 1000#undef REG_STRUCT1001#define REG_STRUCT optc_regs1002 optc_regs_init(0),1003 optc_regs_init(1),1004 optc_regs_init(2),1005 optc_regs_init(3);1006 1007 tgn10->base.inst = instance;1008 tgn10->base.ctx = ctx;1009 1010 tgn10->tg_regs = &optc_regs[instance];1011 tgn10->tg_shift = &optc_shift;1012 tgn10->tg_mask = &optc_mask;1013 1014 dcn32_timing_generator_init(tgn10);1015 1016 return &tgn10->base;1017}1018 1019static const struct encoder_feature_support link_enc_feature = {1020 .max_hdmi_deep_color = COLOR_DEPTH_121212,1021 .max_hdmi_pixel_clock = 600000,1022 .hdmi_ycbcr420_supported = true,1023 .dp_ycbcr420_supported = true,1024 .fec_supported = true,1025 .flags.bits.IS_HBR2_CAPABLE = true,1026 .flags.bits.IS_HBR3_CAPABLE = true,1027 .flags.bits.IS_TPS3_CAPABLE = true,1028 .flags.bits.IS_TPS4_CAPABLE = true1029};1030 1031static struct link_encoder *dcn321_link_encoder_create(1032 struct dc_context *ctx,1033 const struct encoder_init_data *enc_init_data)1034{1035 struct dcn20_link_encoder *enc20 =1036 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1037 1038 if (!enc20)1039 return NULL;1040 1041#undef REG_STRUCT1042#define REG_STRUCT link_enc_aux_regs1043 aux_regs_init(0),1044 aux_regs_init(1),1045 aux_regs_init(2),1046 aux_regs_init(3),1047 aux_regs_init(4);1048 1049#undef REG_STRUCT1050#define REG_STRUCT link_enc_hpd_regs1051 hpd_regs_init(0),1052 hpd_regs_init(1),1053 hpd_regs_init(2),1054 hpd_regs_init(3),1055 hpd_regs_init(4);1056 1057#undef REG_STRUCT1058#define REG_STRUCT link_enc_regs1059 link_regs_init(0, A),1060 link_regs_init(1, B),1061 link_regs_init(2, C),1062 link_regs_init(3, D),1063 link_regs_init(4, E);1064 1065 dcn321_link_encoder_construct(enc20,1066 enc_init_data,1067 &link_enc_feature,1068 &link_enc_regs[enc_init_data->transmitter],1069 &link_enc_aux_regs[enc_init_data->channel - 1],1070 &link_enc_hpd_regs[enc_init_data->hpd_source],1071 &le_shift,1072 &le_mask);1073 1074 return &enc20->enc10.base;1075}1076 1077static void read_dce_straps(1078 struct dc_context *ctx,1079 struct resource_straps *straps)1080{1081 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,1082 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);1083 1084}1085 1086static struct audio *dcn321_create_audio(1087 struct dc_context *ctx, unsigned int inst)1088{1089 1090#undef REG_STRUCT1091#define REG_STRUCT audio_regs1092 audio_regs_init(0),1093 audio_regs_init(1),1094 audio_regs_init(2),1095 audio_regs_init(3),1096 audio_regs_init(4);1097 1098 return dce_audio_create(ctx, inst,1099 &audio_regs[inst], &audio_shift, &audio_mask);1100}1101 1102static struct vpg *dcn321_vpg_create(1103 struct dc_context *ctx,1104 uint32_t inst)1105{1106 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);1107 1108 if (!vpg3)1109 return NULL;1110 1111#undef REG_STRUCT1112#define REG_STRUCT vpg_regs1113 vpg_regs_init(0),1114 vpg_regs_init(1),1115 vpg_regs_init(2),1116 vpg_regs_init(3),1117 vpg_regs_init(4),1118 vpg_regs_init(5),1119 vpg_regs_init(6),1120 vpg_regs_init(7),1121 vpg_regs_init(8),1122 vpg_regs_init(9);1123 1124 vpg3_construct(vpg3, ctx, inst,1125 &vpg_regs[inst],1126 &vpg_shift,1127 &vpg_mask);1128 1129 return &vpg3->base;1130}1131 1132static struct afmt *dcn321_afmt_create(1133 struct dc_context *ctx,1134 uint32_t inst)1135{1136 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);1137 1138 if (!afmt3)1139 return NULL;1140 1141#undef REG_STRUCT1142#define REG_STRUCT afmt_regs1143 afmt_regs_init(0),1144 afmt_regs_init(1),1145 afmt_regs_init(2),1146 afmt_regs_init(3),1147 afmt_regs_init(4),1148 afmt_regs_init(5);1149 1150 afmt3_construct(afmt3, ctx, inst,1151 &afmt_regs[inst],1152 &afmt_shift,1153 &afmt_mask);1154 1155 return &afmt3->base;1156}1157 1158static struct apg *dcn321_apg_create(1159 struct dc_context *ctx,1160 uint32_t inst)1161{1162 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);1163 1164 if (!apg31)1165 return NULL;1166 1167#undef REG_STRUCT1168#define REG_STRUCT apg_regs1169 apg_regs_init(0),1170 apg_regs_init(1),1171 apg_regs_init(2),1172 apg_regs_init(3);1173 1174 apg31_construct(apg31, ctx, inst,1175 &apg_regs[inst],1176 &apg_shift,1177 &apg_mask);1178 1179 return &apg31->base;1180}1181 1182static struct stream_encoder *dcn321_stream_encoder_create(1183 enum engine_id eng_id,1184 struct dc_context *ctx)1185{1186 struct dcn10_stream_encoder *enc1;1187 struct vpg *vpg;1188 struct afmt *afmt;1189 int vpg_inst;1190 int afmt_inst;1191 1192 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */1193 if (eng_id <= ENGINE_ID_DIGF) {1194 vpg_inst = eng_id;1195 afmt_inst = eng_id;1196 } else1197 return NULL;1198 1199 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1200 vpg = dcn321_vpg_create(ctx, vpg_inst);1201 afmt = dcn321_afmt_create(ctx, afmt_inst);1202 1203 if (!enc1 || !vpg || !afmt) {1204 kfree(enc1);1205 kfree(vpg);1206 kfree(afmt);1207 return NULL;1208 }1209 1210#undef REG_STRUCT1211#define REG_STRUCT stream_enc_regs1212 stream_enc_regs_init(0),1213 stream_enc_regs_init(1),1214 stream_enc_regs_init(2),1215 stream_enc_regs_init(3),1216 stream_enc_regs_init(4);1217 1218 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,1219 eng_id, vpg, afmt,1220 &stream_enc_regs[eng_id],1221 &se_shift, &se_mask);1222 1223 return &enc1->base;1224}1225 1226static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(1227 enum engine_id eng_id,1228 struct dc_context *ctx)1229{1230 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;1231 struct vpg *vpg;1232 struct apg *apg;1233 uint32_t hpo_dp_inst;1234 uint32_t vpg_inst;1235 uint32_t apg_inst;1236 1237 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));1238 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;1239 1240 /* Mapping of VPG register blocks to HPO DP block instance:1241 * VPG[6] -> HPO_DP[0]1242 * VPG[7] -> HPO_DP[1]1243 * VPG[8] -> HPO_DP[2]1244 * VPG[9] -> HPO_DP[3]1245 */1246 vpg_inst = hpo_dp_inst + 6;1247 1248 /* Mapping of APG register blocks to HPO DP block instance:1249 * APG[0] -> HPO_DP[0]1250 * APG[1] -> HPO_DP[1]1251 * APG[2] -> HPO_DP[2]1252 * APG[3] -> HPO_DP[3]1253 */1254 apg_inst = hpo_dp_inst;1255 1256 /* allocate HPO stream encoder and create VPG sub-block */1257 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);1258 vpg = dcn321_vpg_create(ctx, vpg_inst);1259 apg = dcn321_apg_create(ctx, apg_inst);1260 1261 if (!hpo_dp_enc31 || !vpg || !apg) {1262 kfree(hpo_dp_enc31);1263 kfree(vpg);1264 kfree(apg);1265 return NULL;1266 }1267 1268#undef REG_STRUCT1269#define REG_STRUCT hpo_dp_stream_enc_regs1270 hpo_dp_stream_encoder_reg_init(0),1271 hpo_dp_stream_encoder_reg_init(1),1272 hpo_dp_stream_encoder_reg_init(2),1273 hpo_dp_stream_encoder_reg_init(3);1274 1275 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,1276 hpo_dp_inst, eng_id, vpg, apg,1277 &hpo_dp_stream_enc_regs[hpo_dp_inst],1278 &hpo_dp_se_shift, &hpo_dp_se_mask);1279 1280 return &hpo_dp_enc31->base;1281}1282 1283static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(1284 uint8_t inst,1285 struct dc_context *ctx)1286{1287 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;1288 1289 /* allocate HPO link encoder */1290 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);1291 if (!hpo_dp_enc31)1292 return NULL; /* out of memory */1293 1294#undef REG_STRUCT1295#define REG_STRUCT hpo_dp_link_enc_regs1296 hpo_dp_link_encoder_reg_init(0),1297 hpo_dp_link_encoder_reg_init(1);1298 1299 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,1300 &hpo_dp_link_enc_regs[inst],1301 &hpo_dp_le_shift, &hpo_dp_le_mask);1302 1303 return &hpo_dp_enc31->base;1304}1305 1306static struct dce_hwseq *dcn321_hwseq_create(1307 struct dc_context *ctx)1308{1309 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1310 1311#undef REG_STRUCT1312#define REG_STRUCT hwseq_reg1313 hwseq_reg_init();1314 1315 if (hws) {1316 hws->ctx = ctx;1317 hws->regs = &hwseq_reg;1318 hws->shifts = &hwseq_shift;1319 hws->masks = &hwseq_mask;1320 }1321 return hws;1322}1323static const struct resource_create_funcs res_create_funcs = {1324 .read_dce_straps = read_dce_straps,1325 .create_audio = dcn321_create_audio,1326 .create_stream_encoder = dcn321_stream_encoder_create,1327 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,1328 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,1329 .create_hwseq = dcn321_hwseq_create,1330};1331 1332static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)1333{1334 unsigned int i;1335 1336 for (i = 0; i < pool->base.stream_enc_count; i++) {1337 if (pool->base.stream_enc[i] != NULL) {1338 if (pool->base.stream_enc[i]->vpg != NULL) {1339 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));1340 pool->base.stream_enc[i]->vpg = NULL;1341 }1342 if (pool->base.stream_enc[i]->afmt != NULL) {1343 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));1344 pool->base.stream_enc[i]->afmt = NULL;1345 }1346 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));1347 pool->base.stream_enc[i] = NULL;1348 }1349 }1350 1351 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {1352 if (pool->base.hpo_dp_stream_enc[i] != NULL) {1353 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {1354 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));1355 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;1356 }1357 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {1358 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));1359 pool->base.hpo_dp_stream_enc[i]->apg = NULL;1360 }1361 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));1362 pool->base.hpo_dp_stream_enc[i] = NULL;1363 }1364 }1365 1366 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {1367 if (pool->base.hpo_dp_link_enc[i] != NULL) {1368 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));1369 pool->base.hpo_dp_link_enc[i] = NULL;1370 }1371 }1372 1373 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1374 if (pool->base.dscs[i] != NULL)1375 dcn20_dsc_destroy(&pool->base.dscs[i]);1376 }1377 1378 if (pool->base.mpc != NULL) {1379 kfree(TO_DCN20_MPC(pool->base.mpc));1380 pool->base.mpc = NULL;1381 }1382 if (pool->base.hubbub != NULL) {1383 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));1384 pool->base.hubbub = NULL;1385 }1386 for (i = 0; i < pool->base.pipe_count; i++) {1387 if (pool->base.dpps[i] != NULL)1388 dcn321_dpp_destroy(&pool->base.dpps[i]);1389 1390 if (pool->base.ipps[i] != NULL)1391 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);1392 1393 if (pool->base.hubps[i] != NULL) {1394 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));1395 pool->base.hubps[i] = NULL;1396 }1397 1398 if (pool->base.irqs != NULL)1399 dal_irq_service_destroy(&pool->base.irqs);1400 }1401 1402 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1403 if (pool->base.engines[i] != NULL)1404 dce110_engine_destroy(&pool->base.engines[i]);1405 if (pool->base.hw_i2cs[i] != NULL) {1406 kfree(pool->base.hw_i2cs[i]);1407 pool->base.hw_i2cs[i] = NULL;1408 }1409 if (pool->base.sw_i2cs[i] != NULL) {1410 kfree(pool->base.sw_i2cs[i]);1411 pool->base.sw_i2cs[i] = NULL;1412 }1413 }1414 1415 for (i = 0; i < pool->base.res_cap->num_opp; i++) {1416 if (pool->base.opps[i] != NULL)1417 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);1418 }1419 1420 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1421 if (pool->base.timing_generators[i] != NULL) {1422 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));1423 pool->base.timing_generators[i] = NULL;1424 }1425 }1426 1427 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {1428 if (pool->base.dwbc[i] != NULL) {1429 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));1430 pool->base.dwbc[i] = NULL;1431 }1432 if (pool->base.mcif_wb[i] != NULL) {1433 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));1434 pool->base.mcif_wb[i] = NULL;1435 }1436 }1437 1438 for (i = 0; i < pool->base.audio_count; i++) {1439 if (pool->base.audios[i])1440 dce_aud_destroy(&pool->base.audios[i]);1441 }1442 1443 for (i = 0; i < pool->base.clk_src_count; i++) {1444 if (pool->base.clock_sources[i] != NULL) {1445 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);1446 pool->base.clock_sources[i] = NULL;1447 }1448 }1449 1450 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {1451 if (pool->base.mpc_lut[i] != NULL) {1452 dc_3dlut_func_release(pool->base.mpc_lut[i]);1453 pool->base.mpc_lut[i] = NULL;1454 }1455 if (pool->base.mpc_shaper[i] != NULL) {1456 dc_transfer_func_release(pool->base.mpc_shaper[i]);1457 pool->base.mpc_shaper[i] = NULL;1458 }1459 }1460 1461 if (pool->base.dp_clock_source != NULL) {1462 dcn20_clock_source_destroy(&pool->base.dp_clock_source);1463 pool->base.dp_clock_source = NULL;1464 }1465 1466 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1467 if (pool->base.multiple_abms[i] != NULL)1468 dce_abm_destroy(&pool->base.multiple_abms[i]);1469 }1470 1471 if (pool->base.psr != NULL)1472 dmub_psr_destroy(&pool->base.psr);1473 1474 if (pool->base.dccg != NULL)1475 dcn_dccg_destroy(&pool->base.dccg);1476 1477 if (pool->base.oem_device != NULL) {1478 struct dc *dc = pool->base.oem_device->ctx->dc;1479 1480 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);1481 }1482}1483 1484 1485static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)1486{1487 int i;1488 uint32_t dwb_count = pool->res_cap->num_dwb;1489 1490 for (i = 0; i < dwb_count; i++) {1491 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),1492 GFP_KERNEL);1493 1494 if (!dwbc30) {1495 dm_error("DC: failed to create dwbc30!\n");1496 return false;1497 }1498 1499#undef REG_STRUCT1500#define REG_STRUCT dwbc30_regs1501 dwbc_regs_dcn3_init(0);1502 1503 dcn30_dwbc_construct(dwbc30, ctx,1504 &dwbc30_regs[i],1505 &dwbc30_shift,1506 &dwbc30_mask,1507 i);1508 1509 pool->dwbc[i] = &dwbc30->base;1510 }1511 return true;1512}1513 1514static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)1515{1516 int i;1517 uint32_t dwb_count = pool->res_cap->num_dwb;1518 1519 for (i = 0; i < dwb_count; i++) {1520 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),1521 GFP_KERNEL);1522 1523 if (!mcif_wb30) {1524 dm_error("DC: failed to create mcif_wb30!\n");1525 return false;1526 }1527 1528#undef REG_STRUCT1529#define REG_STRUCT mcif_wb30_regs1530 mcif_wb_regs_dcn3_init(0);1531 1532 dcn32_mmhubbub_construct(mcif_wb30, ctx,1533 &mcif_wb30_regs[i],1534 &mcif_wb30_shift,1535 &mcif_wb30_mask,1536 i);1537 1538 pool->mcif_wb[i] = &mcif_wb30->base;1539 }1540 return true;1541}1542 1543static struct display_stream_compressor *dcn321_dsc_create(1544 struct dc_context *ctx, uint32_t inst)1545{1546 struct dcn20_dsc *dsc =1547 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);1548 1549 if (!dsc) {1550 BREAK_TO_DEBUGGER();1551 return NULL;1552 }1553 1554#undef REG_STRUCT1555#define REG_STRUCT dsc_regs1556 dsc_regsDCN20_init(0),1557 dsc_regsDCN20_init(1),1558 dsc_regsDCN20_init(2),1559 dsc_regsDCN20_init(3);1560 1561 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1562 1563 dsc->max_image_width = 6016;1564 1565 return &dsc->base;1566}1567 1568static void dcn321_destroy_resource_pool(struct resource_pool **pool)1569{1570 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);1571 1572 dcn321_resource_destruct(dcn321_pool);1573 kfree(dcn321_pool);1574 *pool = NULL;1575}1576 1577static struct dc_cap_funcs cap_funcs = {1578 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,1579 .get_subvp_en = dcn32_subvp_in_use,1580};1581 1582static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)1583{1584 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;1585 1586 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));1587 1588 DC_FP_START();1589 1590 dcn321_update_bw_bounding_box_fpu(dc, bw_params);1591 1592 dml2_opt->use_clock_dc_limits = false;1593 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)1594 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);1595 1596 dml2_opt->use_clock_dc_limits = true;1597 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)1598 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);1599 1600 DC_FP_END();1601}1602 1603static struct resource_funcs dcn321_res_pool_funcs = {1604 .destroy = dcn321_destroy_resource_pool,1605 .link_enc_create = dcn321_link_encoder_create,1606 .link_enc_create_minimal = NULL,1607 .panel_cntl_create = dcn32_panel_cntl_create,1608 .validate_bandwidth = dcn32_validate_bandwidth,1609 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,1610 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,1611 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,1612 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,1613 .release_pipe = dcn20_release_pipe,1614 .add_stream_to_ctx = dcn30_add_stream_to_ctx,1615 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1616 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1617 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,1618 .set_mcif_arb_params = dcn30_set_mcif_arb_params,1619 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1620 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,1621 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,1622 .update_bw_bounding_box = dcn321_update_bw_bounding_box,1623 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,1624 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,1625 .add_phantom_pipes = dcn32_add_phantom_pipes,1626 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,1627 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,1628};1629 1630static uint32_t read_pipe_fuses(struct dc_context *ctx)1631{1632 uint32_t value = REG_READ(CC_DC_PIPE_DIS);1633 /* DCN321 support max 4 pipes */1634 value = value & 0xf;1635 return value;1636}1637 1638 1639static bool dcn321_resource_construct(1640 uint8_t num_virtual_links,1641 struct dc *dc,1642 struct dcn321_resource_pool *pool)1643{1644 int i, j;1645 struct dc_context *ctx = dc->ctx;1646 struct irq_service_init_data init_data;1647 struct ddc_service_init_data ddc_init_data = {0};1648 uint32_t pipe_fuses = 0;1649 uint32_t num_pipes = 4;1650 1651#undef REG_STRUCT1652#define REG_STRUCT bios_regs1653 bios_regs_init();1654 1655#undef REG_STRUCT1656#define REG_STRUCT clk_src_regs1657 clk_src_regs_init(0, A),1658 clk_src_regs_init(1, B),1659 clk_src_regs_init(2, C),1660 clk_src_regs_init(3, D),1661 clk_src_regs_init(4, E);1662 1663#undef REG_STRUCT1664#define REG_STRUCT abm_regs1665 abm_regs_init(0),1666 abm_regs_init(1),1667 abm_regs_init(2),1668 abm_regs_init(3);1669 1670#undef REG_STRUCT1671#define REG_STRUCT dccg_regs1672 dccg_regs_init();1673 1674 1675 ctx->dc_bios->regs = &bios_regs;1676 1677 pool->base.res_cap = &res_cap_dcn321;1678 /* max number of pipes for ASIC before checking for pipe fuses */1679 num_pipes = pool->base.res_cap->num_timing_generator;1680 pipe_fuses = read_pipe_fuses(ctx);1681 1682 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)1683 if (pipe_fuses & 1 << i)1684 num_pipes--;1685 1686 if (pipe_fuses & 1)1687 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!1688 1689 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)1690 ASSERT(0); //Entire DCN is harvested!1691 1692 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the1693 * value will be changed, update max_num_dpp and max_num_otg for dml.1694 */1695 dcn3_21_ip.max_num_dpp = num_pipes;1696 dcn3_21_ip.max_num_otg = num_pipes;1697 1698 pool->base.funcs = &dcn321_res_pool_funcs;1699 1700 /*************************************************1701 * Resource + asic cap harcoding *1702 *************************************************/1703 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;1704 pool->base.timing_generator_count = num_pipes;1705 pool->base.pipe_count = num_pipes;1706 pool->base.mpcc_count = num_pipes;1707 dc->caps.max_downscale_ratio = 600;1708 dc->caps.i2c_speed_in_khz = 100;1709 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/1710 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/1711 dc->caps.max_cursor_size = 64;1712 dc->caps.min_horizontal_blanking_period = 80;1713 dc->caps.dmdata_alloc_size = 2048;1714 dc->caps.mall_size_per_mem_channel = 4;1715 /* total size = mall per channel * num channels * 1024 * 1024 */1716 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;1717 1718 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;1719 dc->caps.cache_line_size = 64;1720 dc->caps.cache_num_ways = 16;1721 1722 /* Calculate the available MALL space */1723 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(1724 dc, dc->ctx->dc_bios->vram_info.num_chans) *1725 dc->caps.mall_size_per_mem_channel * 1024 * 1024;1726 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;1727 1728 dc->caps.subvp_fw_processing_delay_us = 15;1729 dc->caps.subvp_drr_max_vblank_margin_us = 40;1730 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;1731 dc->caps.subvp_swath_height_margin_lines = 16;1732 dc->caps.subvp_pstate_allow_width_us = 20;1733 dc->caps.subvp_vertical_int_margin_us = 30;1734 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin1735 dc->caps.max_slave_planes = 2;1736 dc->caps.max_slave_yuv_planes = 2;1737 dc->caps.max_slave_rgb_planes = 2;1738 dc->caps.post_blend_color_processing = true;1739 dc->caps.force_dp_tps4_for_cp2520 = true;1740 dc->caps.dp_hpo = true;1741 dc->caps.dp_hdmi21_pcon_support = true;1742 dc->caps.edp_dsc_support = true;1743 dc->caps.extended_aux_timeout_support = true;1744 dc->caps.dmcub_support = true;1745 dc->caps.max_v_total = (1 << 15) - 1;1746 1747 /* Color pipeline capabilities */1748 dc->caps.color.dpp.dcn_arch = 1;1749 dc->caps.color.dpp.input_lut_shared = 0;1750 dc->caps.color.dpp.icsc = 1;1751 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr1752 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1753 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1754 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;1755 dc->caps.color.dpp.dgam_rom_caps.pq = 1;1756 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;1757 dc->caps.color.dpp.post_csc = 1;1758 dc->caps.color.dpp.gamma_corr = 1;1759 dc->caps.color.dpp.dgam_rom_for_yuv = 0;1760 1761 dc->caps.color.dpp.hw_3d_lut = 1;1762 dc->caps.color.dpp.ogam_ram = 1;1763 // no OGAM ROM on DCN2 and later ASICs1764 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1765 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1766 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1767 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1768 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1769 dc->caps.color.dpp.ocsc = 0;1770 1771 dc->caps.color.mpc.gamut_remap = 1;1772 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC1773 dc->caps.color.mpc.ogam_ram = 1;1774 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1775 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1776 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1777 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1778 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1779 dc->caps.color.mpc.ocsc = 1;1780 1781 /* Use pipe context based otg sync logic */1782 dc->config.use_pipe_ctx_sync_logic = true;1783 1784 dc->config.dc_mode_clk_limit_support = true;1785 dc->config.enable_windowed_mpo_odm = true;1786 dc->config.disable_hbr_audio_dp2 = true;1787 /* read VBIOS LTTPR caps */1788 {1789 if (ctx->dc_bios->funcs->get_lttpr_caps) {1790 enum bp_result bp_query_result;1791 uint8_t is_vbios_lttpr_enable = 0;1792 1793 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);1794 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;1795 }1796 1797 /* interop bit is implicit */1798 {1799 dc->caps.vbios_lttpr_aware = true;1800 }1801 }1802 1803 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1804 dc->debug = debug_defaults_drv;1805 1806 // Init the vm_helper1807 if (dc->vm_helper)1808 vm_helper_init(dc->vm_helper, 16);1809 1810 /*************************************************1811 * Create resources *1812 *************************************************/1813 1814 /* Clock Sources for Pixel Clock*/1815 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =1816 dcn321_clock_source_create(ctx, ctx->dc_bios,1817 CLOCK_SOURCE_COMBO_PHY_PLL0,1818 &clk_src_regs[0], false);1819 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =1820 dcn321_clock_source_create(ctx, ctx->dc_bios,1821 CLOCK_SOURCE_COMBO_PHY_PLL1,1822 &clk_src_regs[1], false);1823 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =1824 dcn321_clock_source_create(ctx, ctx->dc_bios,1825 CLOCK_SOURCE_COMBO_PHY_PLL2,1826 &clk_src_regs[2], false);1827 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =1828 dcn321_clock_source_create(ctx, ctx->dc_bios,1829 CLOCK_SOURCE_COMBO_PHY_PLL3,1830 &clk_src_regs[3], false);1831 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =1832 dcn321_clock_source_create(ctx, ctx->dc_bios,1833 CLOCK_SOURCE_COMBO_PHY_PLL4,1834 &clk_src_regs[4], false);1835 1836 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;1837 1838 /* todo: not reuse phy_pll registers */1839 pool->base.dp_clock_source =1840 dcn321_clock_source_create(ctx, ctx->dc_bios,1841 CLOCK_SOURCE_ID_DP_DTO,1842 &clk_src_regs[0], true);1843 1844 for (i = 0; i < pool->base.clk_src_count; i++) {1845 if (pool->base.clock_sources[i] == NULL) {1846 dm_error("DC: failed to create clock sources!\n");1847 BREAK_TO_DEBUGGER();1848 goto create_fail;1849 }1850 }1851 1852 /* DCCG */1853 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1854 if (pool->base.dccg == NULL) {1855 dm_error("DC: failed to create dccg!\n");1856 BREAK_TO_DEBUGGER();1857 goto create_fail;1858 }1859 1860 /* DML */1861 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);1862 1863 /* IRQ Service */1864 init_data.ctx = dc->ctx;1865 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);1866 if (!pool->base.irqs)1867 goto create_fail;1868 1869 /* HUBBUB */1870 pool->base.hubbub = dcn321_hubbub_create(ctx);1871 if (pool->base.hubbub == NULL) {1872 BREAK_TO_DEBUGGER();1873 dm_error("DC: failed to create hubbub!\n");1874 goto create_fail;1875 }1876 1877 /* HUBPs, DPPs, OPPs, TGs, ABMs */1878 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {1879 1880 /* if pipe is disabled, skip instance of HW pipe,1881 * i.e, skip ASIC register instance1882 */1883 if (pipe_fuses & 1 << i)1884 continue;1885 1886 pool->base.hubps[j] = dcn321_hubp_create(ctx, i);1887 if (pool->base.hubps[j] == NULL) {1888 BREAK_TO_DEBUGGER();1889 dm_error(1890 "DC: failed to create hubps!\n");1891 goto create_fail;1892 }1893 1894 pool->base.dpps[j] = dcn321_dpp_create(ctx, i);1895 if (pool->base.dpps[j] == NULL) {1896 BREAK_TO_DEBUGGER();1897 dm_error(1898 "DC: failed to create dpps!\n");1899 goto create_fail;1900 }1901 1902 pool->base.opps[j] = dcn321_opp_create(ctx, i);1903 if (pool->base.opps[j] == NULL) {1904 BREAK_TO_DEBUGGER();1905 dm_error(1906 "DC: failed to create output pixel processor!\n");1907 goto create_fail;1908 }1909 1910 pool->base.timing_generators[j] = dcn321_timing_generator_create(1911 ctx, i);1912 if (pool->base.timing_generators[j] == NULL) {1913 BREAK_TO_DEBUGGER();1914 dm_error("DC: failed to create tg!\n");1915 goto create_fail;1916 }1917 1918 pool->base.multiple_abms[j] = dmub_abm_create(ctx,1919 &abm_regs[i],1920 &abm_shift,1921 &abm_mask);1922 if (pool->base.multiple_abms[j] == NULL) {1923 dm_error("DC: failed to create abm for pipe %d!\n", i);1924 BREAK_TO_DEBUGGER();1925 goto create_fail;1926 }1927 1928 /* index for resource pool arrays for next valid pipe */1929 j++;1930 }1931 1932 /* PSR */1933 pool->base.psr = dmub_psr_create(ctx);1934 if (pool->base.psr == NULL) {1935 dm_error("DC: failed to create psr obj!\n");1936 BREAK_TO_DEBUGGER();1937 goto create_fail;1938 }1939 1940 /* MPCCs */1941 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);1942 if (pool->base.mpc == NULL) {1943 BREAK_TO_DEBUGGER();1944 dm_error("DC: failed to create mpc!\n");1945 goto create_fail;1946 }1947 1948 /* DSCs */1949 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1950 pool->base.dscs[i] = dcn321_dsc_create(ctx, i);1951 if (pool->base.dscs[i] == NULL) {1952 BREAK_TO_DEBUGGER();1953 dm_error("DC: failed to create display stream compressor %d!\n", i);1954 goto create_fail;1955 }1956 }1957 1958 /* DWB */1959 if (!dcn321_dwbc_create(ctx, &pool->base)) {1960 BREAK_TO_DEBUGGER();1961 dm_error("DC: failed to create dwbc!\n");1962 goto create_fail;1963 }1964 1965 /* MMHUBBUB */1966 if (!dcn321_mmhubbub_create(ctx, &pool->base)) {1967 BREAK_TO_DEBUGGER();1968 dm_error("DC: failed to create mcif_wb!\n");1969 goto create_fail;1970 }1971 1972 /* AUX and I2C */1973 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1974 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);1975 if (pool->base.engines[i] == NULL) {1976 BREAK_TO_DEBUGGER();1977 dm_error(1978 "DC:failed to create aux engine!!\n");1979 goto create_fail;1980 }1981 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);1982 if (pool->base.hw_i2cs[i] == NULL) {1983 BREAK_TO_DEBUGGER();1984 dm_error(1985 "DC:failed to create hw i2c!!\n");1986 goto create_fail;1987 }1988 pool->base.sw_i2cs[i] = NULL;1989 }1990 1991 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */1992 if (!resource_construct(num_virtual_links, dc, &pool->base,1993 &res_create_funcs))1994 goto create_fail;1995 1996 /* HW Sequencer init functions and Plane caps */1997 dcn32_hw_sequencer_init_functions(dc);1998 1999 dc->caps.max_planes = pool->base.pipe_count;2000 2001 for (i = 0; i < dc->caps.max_planes; ++i)2002 dc->caps.planes[i] = plane_cap;2003 2004 dc->cap_funcs = cap_funcs;2005 2006 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {2007 ddc_init_data.ctx = dc->ctx;2008 ddc_init_data.link = NULL;2009 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;2010 ddc_init_data.id.enum_id = 0;2011 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;2012 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);2013 } else {2014 pool->base.oem_device = NULL;2015 }2016 2017 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;2018 dc->dml2_options.use_native_pstate_optimization = false;2019 dc->dml2_options.use_native_soc_bb_construction = true;2020 dc->dml2_options.minimize_dispclk_using_odm = true;2021 2022 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);2023 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;2024 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;2025 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;2026 2027 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;2028 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;2029 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;2030 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;2031 2032 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;2033 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;2034 2035 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;2036 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;2037 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;2038 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;2039 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;2040 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;2041 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;2042 2043 dc->dml2_options.max_segments_per_hubp = 18;2044 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;2045 2046 return true;2047 2048create_fail:2049 2050 dcn321_resource_destruct(pool);2051 2052 return false;2053}2054 2055struct resource_pool *dcn321_create_resource_pool(2056 const struct dc_init_data *init_data,2057 struct dc *dc)2058{2059 struct dcn321_resource_pool *pool =2060 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);2061 2062 if (!pool)2063 return NULL;2064 2065 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))2066 return &pool->base;2067 2068 BREAK_TO_DEBUGGER();2069 kfree(pool);2070 return NULL;2071}2072