2189 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#include "dm_services.h"28#include "dc.h"29 30#include "dcn31/dcn31_init.h"31#include "dcn35/dcn35_init.h"32 33#include "resource.h"34#include "include/irq_service_interface.h"35#include "dcn35_resource.h"36#include "dml2/dml2_wrapper.h"37 38#include "dcn20/dcn20_resource.h"39#include "dcn30/dcn30_resource.h"40#include "dcn31/dcn31_resource.h"41#include "dcn32/dcn32_resource.h"42 43#include "dcn10/dcn10_ipp.h"44#include "dcn30/dcn30_hubbub.h"45#include "dcn31/dcn31_hubbub.h"46#include "dcn35/dcn35_hubbub.h"47#include "dcn32/dcn32_mpc.h"48#include "dcn35/dcn35_hubp.h"49#include "irq/dcn35/irq_service_dcn35.h"50#include "dcn35/dcn35_dpp.h"51#include "dcn35/dcn35_optc.h"52#include "dcn20/dcn20_hwseq.h"53#include "dcn30/dcn30_hwseq.h"54#include "dce110/dce110_hwseq.h"55#include "dcn35/dcn35_opp.h"56#include "dcn35/dcn35_dsc.h"57#include "dcn30/dcn30_vpg.h"58#include "dcn30/dcn30_afmt.h"59#include "dcn31/dcn31_dio_link_encoder.h"60#include "dcn35/dcn35_dio_stream_encoder.h"61#include "dcn31/dcn31_hpo_dp_stream_encoder.h"62#include "dcn31/dcn31_hpo_dp_link_encoder.h"63#include "dcn32/dcn32_hpo_dp_link_encoder.h"64#include "link.h"65#include "dcn31/dcn31_apg.h"66#include "dcn32/dcn32_dio_link_encoder.h"67#include "dcn31/dcn31_vpg.h"68#include "dcn31/dcn31_afmt.h"69#include "dce/dce_clock_source.h"70#include "dce/dce_audio.h"71#include "dce/dce_hwseq.h"72#include "clk_mgr.h"73#include "virtual/virtual_stream_encoder.h"74#include "dce110/dce110_resource.h"75#include "dml/display_mode_vba.h"76#include "dcn35/dcn35_dccg.h"77#include "dcn35/dcn35_pg_cntl.h"78#include "dcn10/dcn10_resource.h"79#include "dcn31/dcn31_panel_cntl.h"80#include "dcn35/dcn35_hwseq.h"81#include "dcn35/dcn35_dio_link_encoder.h"82#include "dml/dcn31/dcn31_fpu.h" /*todo*/83#include "dml/dcn35/dcn35_fpu.h"84#include "dcn35/dcn35_dwb.h"85#include "dcn35/dcn35_mmhubbub.h"86 87#include "dcn/dcn_3_5_0_offset.h"88#include "dcn/dcn_3_5_0_sh_mask.h"89#include "nbio/nbio_7_11_0_offset.h"90#include "mmhub/mmhub_3_3_0_offset.h"91#include "mmhub/mmhub_3_3_0_sh_mask.h"92 93#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x094#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL95 96#include "reg_helper.h"97#include "dce/dmub_abm.h"98#include "dce/dmub_psr.h"99#include "dce/dmub_replay.h"100#include "dce/dce_aux.h"101#include "dce/dce_i2c.h"102#include "dml/dcn31/display_mode_vba_31.h" /*temp*/103#include "vm_helper.h"104#include "dcn20/dcn20_vmid.h"105 106#include "dc_state_priv.h"107 108#include "link_enc_cfg.h"109#define DC_LOGGER_INIT(logger)110 111enum dcn35_clk_src_array_id {112 DCN35_CLK_SRC_PLL0,113 DCN35_CLK_SRC_PLL1,114 DCN35_CLK_SRC_PLL2,115 DCN35_CLK_SRC_PLL3,116 DCN35_CLK_SRC_PLL4,117 DCN35_CLK_SRC_TOTAL118};119 120/* begin *********************121 * macros to expend register list macro defined in HW object header file122 */123 124/* DCN */125/* TODO awful hack. fixup dcn20_dwb.h */126#undef BASE_INNER127#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]128 129#define BASE(seg) BASE_INNER(seg)130 131#define SR(reg_name)\132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \133 reg ## reg_name134 135#define SR_ARR(reg_name, id) \136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name137 138#define SR_ARR_INIT(reg_name, id, value) \139 REG_STRUCT[id].reg_name = value140 141#define SRI(reg_name, block, id)\142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \143 reg ## block ## id ## _ ## reg_name144 145#define SRI_ARR(reg_name, block, id)\146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \147 reg ## block ## id ## _ ## reg_name148 149#define SR_ARR_I2C(reg_name, id) \150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name151 152#define SRI_ARR_I2C(reg_name, block, id)\153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \154 reg ## block ## id ## _ ## reg_name155 156#define SRI_ARR_ALPHABET(reg_name, block, index, id)\157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \158 reg ## block ## id ## _ ## reg_name159 160#define SRI2(reg_name, block, id)\161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \162 reg ## reg_name163 164#define SRI2_ARR(reg_name, block, id)\165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \166 reg ## reg_name167 168#define SRIR(var_name, reg_name, block, id)\169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \170 reg ## block ## id ## _ ## reg_name171 172#define SRII(reg_name, block, id)\173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \174 reg ## block ## id ## _ ## reg_name175 176#define SRII_ARR_2(reg_name, block, id, inst)\177 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \178 reg ## block ## id ## _ ## reg_name179 180#define SRII_MPC_RMU(reg_name, block, id)\181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \182 reg ## block ## id ## _ ## reg_name183 184#define SRII_DWB(reg_name, temp_name, block, id)\185 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \186 reg ## block ## id ## _ ## temp_name187 188#define SF_DWB2(reg_name, block, id, field_name, post_fix) \189 .field_name = reg_name ## __ ## field_name ## post_fix190 191#define DCCG_SRII(reg_name, block, id)\192 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \193 reg ## block ## id ## _ ## reg_name194 195#define VUPDATE_SRII(reg_name, block, id)\196 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \197 reg ## reg_name ## _ ## block ## id198 199/* NBIO */200#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]201 202#define NBIO_BASE(seg) \203 NBIO_BASE_INNER(seg)204 205#define NBIO_SR(reg_name)\206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \207 regBIF_BX2_ ## reg_name208 209#define NBIO_SR_ARR(reg_name, id)\210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \211 regBIF_BX2_ ## reg_name212 213#define bios_regs_init() \214 ( \215 NBIO_SR(BIOS_SCRATCH_3),\216 NBIO_SR(BIOS_SCRATCH_6)\217 )218 219static struct bios_registers bios_regs;220 221#define clk_src_regs_init(index, pllid)\222 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)223 224static struct dce110_clk_src_regs clk_src_regs[5];225 226static const struct dce110_clk_src_shift cs_shift = {227 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)228};229 230static const struct dce110_clk_src_mask cs_mask = {231 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)232};233 234#define abm_regs_init(id)\235 ABM_DCN32_REG_LIST_RI(id)236 237static struct dce_abm_registers abm_regs[4];238 239static const struct dce_abm_shift abm_shift = {240 ABM_MASK_SH_LIST_DCN35(__SHIFT)241};242 243static const struct dce_abm_mask abm_mask = {244 ABM_MASK_SH_LIST_DCN35(_MASK)245};246 247#define audio_regs_init(id)\248 AUD_COMMON_REG_LIST_RI(id)249 250static struct dce_audio_registers audio_regs[7];251 252 253#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)257 258static const struct dce_audio_shift audio_shift = {259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)260};261 262static const struct dce_audio_mask audio_mask = {263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)264};265 266#define vpg_regs_init(id)\267 VPG_DCN31_REG_LIST_RI(id)268 269static struct dcn31_vpg_registers vpg_regs[10];270 271static const struct dcn31_vpg_shift vpg_shift = {272 DCN31_VPG_MASK_SH_LIST(__SHIFT)273};274 275static const struct dcn31_vpg_mask vpg_mask = {276 DCN31_VPG_MASK_SH_LIST(_MASK)277};278 279#define afmt_regs_init(id)\280 AFMT_DCN31_REG_LIST_RI(id)281 282static struct dcn31_afmt_registers afmt_regs[6];283 284static const struct dcn31_afmt_shift afmt_shift = {285 DCN31_AFMT_MASK_SH_LIST(__SHIFT)286};287 288static const struct dcn31_afmt_mask afmt_mask = {289 DCN31_AFMT_MASK_SH_LIST(_MASK)290};291 292#define apg_regs_init(id)\293 APG_DCN31_REG_LIST_RI(id)294 295static struct dcn31_apg_registers apg_regs[4];296 297static const struct dcn31_apg_shift apg_shift = {298 DCN31_APG_MASK_SH_LIST(__SHIFT)299};300 301static const struct dcn31_apg_mask apg_mask = {302 DCN31_APG_MASK_SH_LIST(_MASK)303};304 305#define stream_enc_regs_init(id)\306 SE_DCN35_REG_LIST_RI(id)307 308static struct dcn10_stream_enc_registers stream_enc_regs[5];309 310static const struct dcn10_stream_encoder_shift se_shift = {311 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)312};313 314static const struct dcn10_stream_encoder_mask se_mask = {315 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)316};317 318#define aux_regs_init(id)\319 DCN2_AUX_REG_LIST_RI(id)320 321static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];322 323#define hpd_regs_init(id)\324 HPD_REG_LIST_RI(id)325 326static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];327 328 329static const struct dce110_aux_registers_shift aux_shift = {330 DCN_AUX_MASK_SH_LIST(__SHIFT)331};332 333static const struct dce110_aux_registers_mask aux_mask = {334 DCN_AUX_MASK_SH_LIST(_MASK)335};336 337#define link_regs_init(id, phyid)\338 ( \339 LE_DCN35_REG_LIST_RI(id), \340 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\341 )342 343static struct dcn10_link_enc_registers link_enc_regs[5];344 345static const struct dcn10_link_enc_shift le_shift = {346 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \347 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)348};349 350static const struct dcn10_link_enc_mask le_mask = {351 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \352 //DPCS_DCN31_MASK_SH_LIST(_MASK)353};354 355#define hpo_dp_stream_encoder_reg_init(id)\356 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)357 358static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];359 360static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {361 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)362};363 364static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {365 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)366};367 368#define hpo_dp_link_encoder_reg_init(id)\369 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)370 /*DCN3_1_RDPCSTX_REG_LIST(0),*/371 /*DCN3_1_RDPCSTX_REG_LIST(1),*/372 /*DCN3_1_RDPCSTX_REG_LIST(2),*/373 /*DCN3_1_RDPCSTX_REG_LIST(3),*/374 375static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];376 377static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {378 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)379};380 381static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {382 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)383};384 385#define dpp_regs_init(id)\386 DPP_REG_LIST_DCN35_RI(id)387 388static struct dcn3_dpp_registers dpp_regs[4];389 390static const struct dcn35_dpp_shift tf_shift = {391 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)392};393 394static const struct dcn35_dpp_mask tf_mask = {395 DPP_REG_LIST_SH_MASK_DCN35(_MASK)396};397 398#define opp_regs_init(id)\399 OPP_REG_LIST_DCN35_RI(id)400 401static struct dcn35_opp_registers opp_regs[4];402 403static const struct dcn35_opp_shift opp_shift = {404 OPP_MASK_SH_LIST_DCN35(__SHIFT)405};406 407static const struct dcn35_opp_mask opp_mask = {408 OPP_MASK_SH_LIST_DCN35(_MASK)409};410 411#define aux_engine_regs_init(id)\412 ( \413 AUX_COMMON_REG_LIST0_RI(id), \414 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \415 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \416 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \417 )418 419static struct dce110_aux_registers aux_engine_regs[5];420 421#define dwbc_regs_dcn3_init(id)\422 DWBC_COMMON_REG_LIST_DCN30_RI(id)423 424static struct dcn30_dwbc_registers dwbc35_regs[1];425 426static const struct dcn35_dwbc_shift dwbc35_shift = {427 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)428};429 430static const struct dcn35_dwbc_mask dwbc35_mask = {431 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)432};433 434#define mcif_wb_regs_dcn3_init(id)\435 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)436 437static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];438 439static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {440 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)441};442 443static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {444 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)445};446 447#define dsc_regsDCN35_init(id)\448 DSC_REG_LIST_DCN20_RI(id)449 450static struct dcn20_dsc_registers dsc_regs[4];451 452static const struct dcn35_dsc_shift dsc_shift = {453 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)454};455 456static const struct dcn35_dsc_mask dsc_mask = {457 DSC_REG_LIST_SH_MASK_DCN35(_MASK)458};459 460static struct dcn30_mpc_registers mpc_regs;461 462#define dcn_mpc_regs_init() \463 MPC_REG_LIST_DCN3_2_RI(0),\464 MPC_REG_LIST_DCN3_2_RI(1),\465 MPC_REG_LIST_DCN3_2_RI(2),\466 MPC_REG_LIST_DCN3_2_RI(3),\467 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\468 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\469 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\470 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\471 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)472 473static const struct dcn30_mpc_shift mpc_shift = {474 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)475};476 477static const struct dcn30_mpc_mask mpc_mask = {478 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)479};480 481#define optc_regs_init(id)\482 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)483 484static struct dcn_optc_registers optc_regs[4];485 486static const struct dcn_optc_shift optc_shift = {487 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)488};489 490static const struct dcn_optc_mask optc_mask = {491 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)492};493 494#define hubp_regs_init(id)\495 HUBP_REG_LIST_DCN30_RI(id)496 497static struct dcn_hubp2_registers hubp_regs[4];498 499 500static const struct dcn35_hubp2_shift hubp_shift = {501 HUBP_MASK_SH_LIST_DCN35(__SHIFT)502};503 504static const struct dcn35_hubp2_mask hubp_mask = {505 HUBP_MASK_SH_LIST_DCN35(_MASK)506};507 508static struct dcn_hubbub_registers hubbub_reg;509 510#define hubbub_reg_init()\511 HUBBUB_REG_LIST_DCN35(0)512 513static const struct dcn_hubbub_shift hubbub_shift = {514 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)515};516 517static const struct dcn_hubbub_mask hubbub_mask = {518 HUBBUB_MASK_SH_LIST_DCN35(_MASK)519};520 521static struct dccg_registers dccg_regs;522 523#define dccg_regs_init()\524 DCCG_REG_LIST_DCN35()525 526static const struct dccg_shift dccg_shift = {527 DCCG_MASK_SH_LIST_DCN35(__SHIFT)528};529 530static const struct dccg_mask dccg_mask = {531 DCCG_MASK_SH_LIST_DCN35(_MASK)532};533 534static struct pg_cntl_registers pg_cntl_regs;535 536#define pg_cntl_dcn35_regs_init() \537 PG_CNTL_REG_LIST_DCN35()538 539static const struct pg_cntl_shift pg_cntl_shift = {540 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)541};542 543static const struct pg_cntl_mask pg_cntl_mask = {544 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)545};546 547#define SRII2(reg_name_pre, reg_name_post, id)\548 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \549 ## id ## _ ## reg_name_post ## _BASE_IDX) + \550 reg ## reg_name_pre ## id ## _ ## reg_name_post551 552static struct dce_hwseq_registers hwseq_reg;553 554#define hwseq_reg_init()\555 HWSEQ_DCN35_REG_LIST()556 557#define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\558 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \559 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \560 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \561 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \562 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \563 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \564 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \565 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \566 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \567 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \568 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \569 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \570 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \571 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \572 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \573 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \574 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \575 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \576 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \577 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \578 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \579 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \580 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \581 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \582 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \583 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \584 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \585 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \586 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \587 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \588 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \589 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \590 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \591 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \592 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \593 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \594 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \595 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \596 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \597 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \598 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \599 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \600 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \601 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \602 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \603 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\604 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\605 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\606 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\607 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\608 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\609 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\610 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\611 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\612 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\613 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\614 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\615 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\616 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \627 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \628 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \629 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \630 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \631 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \632 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\633 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\634 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\635 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\636 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\637 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\638 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\639 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\640 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\641 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\642 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\643 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\644 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)645 646static const struct dce_hwseq_shift hwseq_shift = {647 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)648};649 650static const struct dce_hwseq_mask hwseq_mask = {651 HWSEQ_DCN35_MASK_SH_LIST(_MASK)652};653 654#define vmid_regs_init(id)\655 DCN20_VMID_REG_LIST_RI(id)656 657static struct dcn_vmid_registers vmid_regs[16];658 659static const struct dcn20_vmid_shift vmid_shifts = {660 DCN20_VMID_MASK_SH_LIST(__SHIFT)661};662 663static const struct dcn20_vmid_mask vmid_masks = {664 DCN20_VMID_MASK_SH_LIST(_MASK)665};666 667static const struct resource_caps res_cap_dcn35 = {668 .num_timing_generator = 4,669 .num_opp = 4,670 .num_video_plane = 4,671 .num_audio = 5,672 .num_stream_encoder = 5,673 .num_dig_link_enc = 5,674 .num_hpo_dp_stream_encoder = 4,675 .num_hpo_dp_link_encoder = 2,676 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/677 .num_dwb = 1,678 .num_ddc = 5,679 .num_vmid = 16,680 .num_mpc_3dlut = 2,681 .num_dsc = 4,682};683 684static const struct dc_plane_cap plane_cap = {685 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,686 .per_pixel_alpha = true,687 688 .pixel_format_support = {689 .argb8888 = true,690 .nv12 = true,691 .fp16 = true,692 .p010 = true,693 .ayuv = false,694 },695 696 .max_upscale_factor = {697 .argb8888 = 16000,698 .nv12 = 16000,699 .fp16 = 16000700 },701 702 // 6:1 downscaling ratio: 1000/6 = 166.666703 .max_downscale_factor = {704 .argb8888 = 250,705 .nv12 = 167,706 .fp16 = 167707 },708 64,709 64710};711 712static const struct dc_debug_options debug_defaults_drv = {713 .disable_dmcu = true,714 .force_abm_enable = false,715 .timing_trace = false,716 .clock_trace = true,717 .disable_pplib_clock_request = false,718 .pipe_split_policy = MPC_SPLIT_AVOID,719 .force_single_disp_pipe_split = false,720 .disable_dcc = DCC_ENABLE,721 .disable_dpp_power_gate = true,722 .disable_hubp_power_gate = true,723 .disable_optc_power_gate = true, /*should the same as above two*/724 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/725 .disable_clock_gate = false,726 .disable_dsc_power_gate = true,727 .vsr_support = true,728 .performance_trace = false,729 .max_downscale_src_width = 4096,/*upto true 4k*/730 .disable_pplib_wm_range = false,731 .scl_reset_length10 = true,732 .sanity_checks = false,733 .underflow_assert_delay_us = 0xFFFFFFFF,734 .dwb_fi_phase = -1, // -1 = disable,735 .dmub_command_table = true,736 .pstate_enabled = true,737 .use_max_lb = true,738 .enable_mem_low_power = {739 .bits = {740 .vga = false,741 .i2c = true,742 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled743 .dscl = true,744 .cm = true,745 .mpc = true,746 .optc = true,747 .vpg = true,748 .afmt = true,749 }750 },751 .root_clock_optimization = {752 .bits = {753 .dpp = true,754 .dsc = true,/*dscclk and dsc pg*/755 .hdmistream = true,756 .hdmichar = true,757 .dpstream = true,758 .symclk32_se = true,759 .symclk32_le = true,760 .symclk_fe = true,761 .physymclk = false,762 .dpiasymclk = true,763 }764 },765 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,766 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/767 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */768 .using_dml2 = true,769 .support_eDP1_5 = true,770 .enable_hpo_pg_support = false,771 .enable_legacy_fast_update = true,772 .enable_single_display_2to1_odm_policy = true,773 .disable_idle_power_optimizations = false,774 .dmcub_emulation = false,775 .disable_boot_optimizations = false,776 .disable_unbounded_requesting = false,777 .disable_mem_low_power = false,778 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions779 .enable_double_buffered_dsc_pg_support = true,780 .enable_dp_dig_pixel_rate_div_policy = 1,781 .disable_z10 = false,782 .ignore_pg = true,783 .psp_disabled_wa = true,784 .ips2_eval_delay_us = 2000,785 .ips2_entry_delay_us = 800,786 .disable_dmub_reallow_idle = false,787 .static_screen_wait_frames = 2,788 .disable_timeout = true,789 .min_disp_clk_khz = 50000,790};791 792static const struct dc_panel_config panel_config_defaults = {793 .psr = {794 .disable_psr = false,795 .disallow_psrsu = false,796 .disallow_replay = false,797 },798 .ilr = {799 .optimize_edp_link_rate = true,800 },801};802 803static void dcn35_dpp_destroy(struct dpp **dpp)804{805 kfree(TO_DCN20_DPP(*dpp));806 *dpp = NULL;807}808 809static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)810{811 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);812 bool success = (dpp != NULL);813 814 if (!success)815 return NULL;816 817#undef REG_STRUCT818#define REG_STRUCT dpp_regs819 dpp_regs_init(0),820 dpp_regs_init(1),821 dpp_regs_init(2),822 dpp_regs_init(3);823 824 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,825 &tf_mask);826 if (success) {827 dpp35_set_fgcg(828 dpp,829 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);830 return &dpp->base;831 }832 833 BREAK_TO_DEBUGGER();834 kfree(dpp);835 return NULL;836}837 838static struct output_pixel_processor *dcn35_opp_create(839 struct dc_context *ctx, uint32_t inst)840{841 struct dcn20_opp *opp =842 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);843 844 if (!opp) {845 BREAK_TO_DEBUGGER();846 return NULL;847 }848 849#undef REG_STRUCT850#define REG_STRUCT opp_regs851 opp_regs_init(0),852 opp_regs_init(1),853 opp_regs_init(2),854 opp_regs_init(3);855 856 dcn35_opp_construct(opp, ctx, inst,857 &opp_regs[inst], &opp_shift, &opp_mask);858 859 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);860 861 return &opp->base;862}863 864static struct dce_aux *dcn31_aux_engine_create(865 struct dc_context *ctx,866 uint32_t inst)867{868 struct aux_engine_dce110 *aux_engine =869 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);870 871 if (!aux_engine)872 return NULL;873 874#undef REG_STRUCT875#define REG_STRUCT aux_engine_regs876 aux_engine_regs_init(0),877 aux_engine_regs_init(1),878 aux_engine_regs_init(2),879 aux_engine_regs_init(3),880 aux_engine_regs_init(4);881 882 dce110_aux_engine_construct(aux_engine, ctx, inst,883 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,884 &aux_engine_regs[inst],885 &aux_mask,886 &aux_shift,887 ctx->dc->caps.extended_aux_timeout_support);888 889 return &aux_engine->base;890}891 892#define i2c_inst_regs_init(id)\893 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)894 895static struct dce_i2c_registers i2c_hw_regs[5];896 897static const struct dce_i2c_shift i2c_shifts = {898 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)899};900 901static const struct dce_i2c_mask i2c_masks = {902 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)903};904 905/* ========================================================== */906 907/*908 * DPIA index | Preferred Encoder | Host Router909 * 0 | C | 0910 * 1 | First Available | 0911 * 2 | D | 1912 * 3 | First Available | 1913 */914/* ========================================================== */915static const enum engine_id dpia_to_preferred_enc_id_table[] = {916 ENGINE_ID_DIGC,917 ENGINE_ID_DIGC,918 ENGINE_ID_DIGD,919 ENGINE_ID_DIGD920};921 922static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)923{924 return dpia_to_preferred_enc_id_table[dpia_index];925}926 927static struct dce_i2c_hw *dcn31_i2c_hw_create(928 struct dc_context *ctx,929 uint32_t inst)930{931 struct dce_i2c_hw *dce_i2c_hw =932 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);933 934 if (!dce_i2c_hw)935 return NULL;936 937#undef REG_STRUCT938#define REG_STRUCT i2c_hw_regs939 i2c_inst_regs_init(1),940 i2c_inst_regs_init(2),941 i2c_inst_regs_init(3),942 i2c_inst_regs_init(4),943 i2c_inst_regs_init(5);944 945 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,946 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);947 948 return dce_i2c_hw;949}950static struct mpc *dcn35_mpc_create(951 struct dc_context *ctx,952 int num_mpcc,953 int num_rmu)954{955 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);956 957 if (!mpc30)958 return NULL;959 960#undef REG_STRUCT961#define REG_STRUCT mpc_regs962 dcn_mpc_regs_init();963 964 dcn32_mpc_construct(mpc30, ctx,965 &mpc_regs,966 &mpc_shift,967 &mpc_mask,968 num_mpcc,969 num_rmu);970 971 return &mpc30->base;972}973 974static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)975{976 int i;977 978 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),979 GFP_KERNEL);980 981 if (!hubbub3)982 return NULL;983 984#undef REG_STRUCT985#define REG_STRUCT hubbub_reg986 hubbub_reg_init();987 988#undef REG_STRUCT989#define REG_STRUCT vmid_regs990 vmid_regs_init(0),991 vmid_regs_init(1),992 vmid_regs_init(2),993 vmid_regs_init(3),994 vmid_regs_init(4),995 vmid_regs_init(5),996 vmid_regs_init(6),997 vmid_regs_init(7),998 vmid_regs_init(8),999 vmid_regs_init(9),1000 vmid_regs_init(10),1001 vmid_regs_init(11),1002 vmid_regs_init(12),1003 vmid_regs_init(13),1004 vmid_regs_init(14),1005 vmid_regs_init(15);1006 1007 hubbub35_construct(hubbub3, ctx,1008 &hubbub_reg,1009 &hubbub_shift,1010 &hubbub_mask,1011 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/1012 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/1013 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);1014 1015 1016 for (i = 0; i < res_cap_dcn35.num_vmid; i++) {1017 struct dcn20_vmid *vmid = &hubbub3->vmid[i];1018 1019 vmid->ctx = ctx;1020 1021 vmid->regs = &vmid_regs[i];1022 vmid->shifts = &vmid_shifts;1023 vmid->masks = &vmid_masks;1024 }1025 1026 return &hubbub3->base;1027}1028 1029static struct timing_generator *dcn35_timing_generator_create(1030 struct dc_context *ctx,1031 uint32_t instance)1032{1033 struct optc *tgn10 =1034 kzalloc(sizeof(struct optc), GFP_KERNEL);1035 1036 if (!tgn10)1037 return NULL;1038 1039#undef REG_STRUCT1040#define REG_STRUCT optc_regs1041 optc_regs_init(0),1042 optc_regs_init(1),1043 optc_regs_init(2),1044 optc_regs_init(3);1045 1046 tgn10->base.inst = instance;1047 tgn10->base.ctx = ctx;1048 1049 tgn10->tg_regs = &optc_regs[instance];1050 tgn10->tg_shift = &optc_shift;1051 tgn10->tg_mask = &optc_mask;1052 1053 dcn35_timing_generator_init(tgn10);1054 1055 return &tgn10->base;1056}1057 1058static const struct encoder_feature_support link_enc_feature = {1059 .max_hdmi_deep_color = COLOR_DEPTH_121212,1060 .max_hdmi_pixel_clock = 600000,1061 .hdmi_ycbcr420_supported = true,1062 .dp_ycbcr420_supported = true,1063 .fec_supported = true,1064 .flags.bits.IS_HBR2_CAPABLE = true,1065 .flags.bits.IS_HBR3_CAPABLE = true,1066 .flags.bits.IS_TPS3_CAPABLE = true,1067 .flags.bits.IS_TPS4_CAPABLE = true1068};1069 1070static struct link_encoder *dcn35_link_encoder_create(1071 struct dc_context *ctx,1072 const struct encoder_init_data *enc_init_data)1073{1074 struct dcn20_link_encoder *enc20 =1075 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1076 1077 if (!enc20)1078 return NULL;1079 1080#undef REG_STRUCT1081#define REG_STRUCT link_enc_aux_regs1082 aux_regs_init(0),1083 aux_regs_init(1),1084 aux_regs_init(2),1085 aux_regs_init(3),1086 aux_regs_init(4);1087 1088#undef REG_STRUCT1089#define REG_STRUCT link_enc_hpd_regs1090 hpd_regs_init(0),1091 hpd_regs_init(1),1092 hpd_regs_init(2),1093 hpd_regs_init(3),1094 hpd_regs_init(4);1095 1096#undef REG_STRUCT1097#define REG_STRUCT link_enc_regs1098 link_regs_init(0, A),1099 link_regs_init(1, B),1100 link_regs_init(2, C),1101 link_regs_init(3, D),1102 link_regs_init(4, E);1103 1104 dcn35_link_encoder_construct(enc20,1105 enc_init_data,1106 &link_enc_feature,1107 &link_enc_regs[enc_init_data->transmitter],1108 &link_enc_aux_regs[enc_init_data->channel - 1],1109 &link_enc_hpd_regs[enc_init_data->hpd_source],1110 &le_shift,1111 &le_mask);1112 1113 return &enc20->enc10.base;1114}1115 1116/* Create a minimal link encoder object not associated with a particular1117 * physical connector.1118 * resource_funcs.link_enc_create_minimal1119 */1120static struct link_encoder *dcn31_link_enc_create_minimal(1121 struct dc_context *ctx, enum engine_id eng_id)1122{1123 struct dcn20_link_encoder *enc20;1124 1125 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)1126 return NULL;1127 1128 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);1129 if (!enc20)1130 return NULL;1131 1132 dcn31_link_encoder_construct_minimal(1133 enc20,1134 ctx,1135 &link_enc_feature,1136 &link_enc_regs[eng_id - ENGINE_ID_DIGA],1137 eng_id);1138 1139 return &enc20->enc10.base;1140}1141 1142static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)1143{1144 struct dcn31_panel_cntl *panel_cntl =1145 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);1146 1147 if (!panel_cntl)1148 return NULL;1149 1150 dcn31_panel_cntl_construct(panel_cntl, init_data);1151 1152 return &panel_cntl->base;1153}1154 1155static void read_dce_straps(1156 struct dc_context *ctx,1157 struct resource_straps *straps)1158{1159 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),1160 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);1161 1162}1163 1164static struct audio *dcn31_create_audio(1165 struct dc_context *ctx, unsigned int inst)1166{1167 1168#undef REG_STRUCT1169#define REG_STRUCT audio_regs1170 audio_regs_init(0),1171 audio_regs_init(1),1172 audio_regs_init(2),1173 audio_regs_init(3),1174 audio_regs_init(4);1175 audio_regs_init(5);1176 audio_regs_init(6);1177 1178 return dce_audio_create(ctx, inst,1179 &audio_regs[inst], &audio_shift, &audio_mask);1180}1181 1182static struct vpg *dcn31_vpg_create(1183 struct dc_context *ctx,1184 uint32_t inst)1185{1186 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);1187 1188 if (!vpg31)1189 return NULL;1190 1191#undef REG_STRUCT1192#define REG_STRUCT vpg_regs1193 vpg_regs_init(0),1194 vpg_regs_init(1),1195 vpg_regs_init(2),1196 vpg_regs_init(3),1197 vpg_regs_init(4),1198 vpg_regs_init(5),1199 vpg_regs_init(6),1200 vpg_regs_init(7),1201 vpg_regs_init(8),1202 vpg_regs_init(9);1203 1204 vpg31_construct(vpg31, ctx, inst,1205 &vpg_regs[inst],1206 &vpg_shift,1207 &vpg_mask);1208 1209 return &vpg31->base;1210}1211 1212static struct afmt *dcn31_afmt_create(1213 struct dc_context *ctx,1214 uint32_t inst)1215{1216 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);1217 1218 if (!afmt31)1219 return NULL;1220 1221#undef REG_STRUCT1222#define REG_STRUCT afmt_regs1223 afmt_regs_init(0),1224 afmt_regs_init(1),1225 afmt_regs_init(2),1226 afmt_regs_init(3),1227 afmt_regs_init(4),1228 afmt_regs_init(5);1229 1230 afmt31_construct(afmt31, ctx, inst,1231 &afmt_regs[inst],1232 &afmt_shift,1233 &afmt_mask);1234 1235 // Light sleep by default, no need to power down here1236 1237 return &afmt31->base;1238}1239 1240static struct apg *dcn31_apg_create(1241 struct dc_context *ctx,1242 uint32_t inst)1243{1244 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);1245 1246 if (!apg31)1247 return NULL;1248 1249#undef REG_STRUCT1250#define REG_STRUCT apg_regs1251 apg_regs_init(0),1252 apg_regs_init(1),1253 apg_regs_init(2),1254 apg_regs_init(3);1255 1256 apg31_construct(apg31, ctx, inst,1257 &apg_regs[inst],1258 &apg_shift,1259 &apg_mask);1260 1261 return &apg31->base;1262}1263 1264static struct stream_encoder *dcn35_stream_encoder_create(1265 enum engine_id eng_id,1266 struct dc_context *ctx)1267{1268 struct dcn10_stream_encoder *enc1;1269 struct vpg *vpg;1270 struct afmt *afmt;1271 int vpg_inst;1272 int afmt_inst;1273 1274 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */1275 if (eng_id <= ENGINE_ID_DIGF) {1276 vpg_inst = eng_id;1277 afmt_inst = eng_id;1278 } else1279 return NULL;1280 1281 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);1282 vpg = dcn31_vpg_create(ctx, vpg_inst);1283 afmt = dcn31_afmt_create(ctx, afmt_inst);1284 1285 if (!enc1 || !vpg || !afmt) {1286 kfree(enc1);1287 kfree(vpg);1288 kfree(afmt);1289 return NULL;1290 }1291 1292#undef REG_STRUCT1293#define REG_STRUCT stream_enc_regs1294 stream_enc_regs_init(0),1295 stream_enc_regs_init(1),1296 stream_enc_regs_init(2),1297 stream_enc_regs_init(3),1298 stream_enc_regs_init(4);1299 1300 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,1301 eng_id, vpg, afmt,1302 &stream_enc_regs[eng_id],1303 &se_shift, &se_mask);1304 1305 return &enc1->base;1306}1307 1308static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(1309 enum engine_id eng_id,1310 struct dc_context *ctx)1311{1312 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;1313 struct vpg *vpg;1314 struct apg *apg;1315 uint32_t hpo_dp_inst;1316 uint32_t vpg_inst;1317 uint32_t apg_inst;1318 1319 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));1320 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;1321 1322 /* Mapping of VPG register blocks to HPO DP block instance:1323 * VPG[6] -> HPO_DP[0]1324 * VPG[7] -> HPO_DP[1]1325 * VPG[8] -> HPO_DP[2]1326 * VPG[9] -> HPO_DP[3]1327 */1328 vpg_inst = hpo_dp_inst + 6;1329 1330 /* Mapping of APG register blocks to HPO DP block instance:1331 * APG[0] -> HPO_DP[0]1332 * APG[1] -> HPO_DP[1]1333 * APG[2] -> HPO_DP[2]1334 * APG[3] -> HPO_DP[3]1335 */1336 apg_inst = hpo_dp_inst;1337 1338 /* allocate HPO stream encoder and create VPG sub-block */1339 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);1340 vpg = dcn31_vpg_create(ctx, vpg_inst);1341 apg = dcn31_apg_create(ctx, apg_inst);1342 1343 if (!hpo_dp_enc31 || !vpg || !apg) {1344 kfree(hpo_dp_enc31);1345 kfree(vpg);1346 kfree(apg);1347 return NULL;1348 }1349 1350#undef REG_STRUCT1351#define REG_STRUCT hpo_dp_stream_enc_regs1352 hpo_dp_stream_encoder_reg_init(0),1353 hpo_dp_stream_encoder_reg_init(1),1354 hpo_dp_stream_encoder_reg_init(2),1355 hpo_dp_stream_encoder_reg_init(3);1356 1357 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,1358 hpo_dp_inst, eng_id, vpg, apg,1359 &hpo_dp_stream_enc_regs[hpo_dp_inst],1360 &hpo_dp_se_shift, &hpo_dp_se_mask);1361 1362 return &hpo_dp_enc31->base;1363}1364 1365static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(1366 uint8_t inst,1367 struct dc_context *ctx)1368{1369 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;1370 1371 /* allocate HPO link encoder */1372 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);1373 if (!hpo_dp_enc31)1374 return NULL; /* out of memory */1375 1376#undef REG_STRUCT1377#define REG_STRUCT hpo_dp_link_enc_regs1378 hpo_dp_link_encoder_reg_init(0),1379 hpo_dp_link_encoder_reg_init(1);1380 1381 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,1382 &hpo_dp_link_enc_regs[inst],1383 &hpo_dp_le_shift, &hpo_dp_le_mask);1384 1385 return &hpo_dp_enc31->base;1386}1387 1388static struct dce_hwseq *dcn35_hwseq_create(1389 struct dc_context *ctx)1390{1391 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);1392 1393#undef REG_STRUCT1394#define REG_STRUCT hwseq_reg1395 hwseq_reg_init();1396 1397 if (hws) {1398 hws->ctx = ctx;1399 hws->regs = &hwseq_reg;1400 hws->shifts = &hwseq_shift;1401 hws->masks = &hwseq_mask;1402 }1403 return hws;1404}1405static const struct resource_create_funcs res_create_funcs = {1406 .read_dce_straps = read_dce_straps,1407 .create_audio = dcn31_create_audio,1408 .create_stream_encoder = dcn35_stream_encoder_create,1409 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,1410 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,1411 .create_hwseq = dcn35_hwseq_create,1412};1413 1414static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)1415{1416 unsigned int i;1417 1418 for (i = 0; i < pool->base.stream_enc_count; i++) {1419 if (pool->base.stream_enc[i] != NULL) {1420 if (pool->base.stream_enc[i]->vpg != NULL) {1421 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));1422 pool->base.stream_enc[i]->vpg = NULL;1423 }1424 if (pool->base.stream_enc[i]->afmt != NULL) {1425 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));1426 pool->base.stream_enc[i]->afmt = NULL;1427 }1428 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));1429 pool->base.stream_enc[i] = NULL;1430 }1431 }1432 1433 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {1434 if (pool->base.hpo_dp_stream_enc[i] != NULL) {1435 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {1436 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));1437 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;1438 }1439 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {1440 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));1441 pool->base.hpo_dp_stream_enc[i]->apg = NULL;1442 }1443 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));1444 pool->base.hpo_dp_stream_enc[i] = NULL;1445 }1446 }1447 1448 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {1449 if (pool->base.hpo_dp_link_enc[i] != NULL) {1450 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));1451 pool->base.hpo_dp_link_enc[i] = NULL;1452 }1453 }1454 1455 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {1456 if (pool->base.dscs[i] != NULL)1457 dcn20_dsc_destroy(&pool->base.dscs[i]);1458 }1459 1460 if (pool->base.mpc != NULL) {1461 kfree(TO_DCN20_MPC(pool->base.mpc));1462 pool->base.mpc = NULL;1463 }1464 if (pool->base.hubbub != NULL) {1465 kfree(pool->base.hubbub);1466 pool->base.hubbub = NULL;1467 }1468 for (i = 0; i < pool->base.pipe_count; i++) {1469 if (pool->base.dpps[i] != NULL)1470 dcn35_dpp_destroy(&pool->base.dpps[i]);1471 1472 if (pool->base.ipps[i] != NULL)1473 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);1474 1475 if (pool->base.hubps[i] != NULL) {1476 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));1477 pool->base.hubps[i] = NULL;1478 }1479 1480 if (pool->base.irqs != NULL) {1481 dal_irq_service_destroy(&pool->base.irqs);1482 }1483 }1484 1485 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {1486 if (pool->base.engines[i] != NULL)1487 dce110_engine_destroy(&pool->base.engines[i]);1488 if (pool->base.hw_i2cs[i] != NULL) {1489 kfree(pool->base.hw_i2cs[i]);1490 pool->base.hw_i2cs[i] = NULL;1491 }1492 if (pool->base.sw_i2cs[i] != NULL) {1493 kfree(pool->base.sw_i2cs[i]);1494 pool->base.sw_i2cs[i] = NULL;1495 }1496 }1497 1498 for (i = 0; i < pool->base.res_cap->num_opp; i++) {1499 if (pool->base.opps[i] != NULL)1500 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);1501 }1502 1503 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1504 if (pool->base.timing_generators[i] != NULL) {1505 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));1506 pool->base.timing_generators[i] = NULL;1507 }1508 }1509 1510 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {1511 if (pool->base.dwbc[i] != NULL) {1512 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));1513 pool->base.dwbc[i] = NULL;1514 }1515 if (pool->base.mcif_wb[i] != NULL) {1516 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));1517 pool->base.mcif_wb[i] = NULL;1518 }1519 }1520 1521 for (i = 0; i < pool->base.audio_count; i++) {1522 if (pool->base.audios[i])1523 dce_aud_destroy(&pool->base.audios[i]);1524 }1525 1526 for (i = 0; i < pool->base.clk_src_count; i++) {1527 if (pool->base.clock_sources[i] != NULL) {1528 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);1529 pool->base.clock_sources[i] = NULL;1530 }1531 }1532 1533 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {1534 if (pool->base.mpc_lut[i] != NULL) {1535 dc_3dlut_func_release(pool->base.mpc_lut[i]);1536 pool->base.mpc_lut[i] = NULL;1537 }1538 if (pool->base.mpc_shaper[i] != NULL) {1539 dc_transfer_func_release(pool->base.mpc_shaper[i]);1540 pool->base.mpc_shaper[i] = NULL;1541 }1542 }1543 1544 if (pool->base.dp_clock_source != NULL) {1545 dcn20_clock_source_destroy(&pool->base.dp_clock_source);1546 pool->base.dp_clock_source = NULL;1547 }1548 1549 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {1550 if (pool->base.multiple_abms[i] != NULL)1551 dce_abm_destroy(&pool->base.multiple_abms[i]);1552 }1553 1554 if (pool->base.psr != NULL)1555 dmub_psr_destroy(&pool->base.psr);1556 1557 if (pool->base.replay != NULL)1558 dmub_replay_destroy(&pool->base.replay);1559 1560 if (pool->base.pg_cntl != NULL)1561 dcn_pg_cntl_destroy(&pool->base.pg_cntl);1562 1563 if (pool->base.dccg != NULL)1564 dcn_dccg_destroy(&pool->base.dccg);1565}1566 1567static struct hubp *dcn35_hubp_create(1568 struct dc_context *ctx,1569 uint32_t inst)1570{1571 struct dcn20_hubp *hubp2 =1572 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);1573 1574 if (!hubp2)1575 return NULL;1576 1577#undef REG_STRUCT1578#define REG_STRUCT hubp_regs1579 hubp_regs_init(0),1580 hubp_regs_init(1),1581 hubp_regs_init(2),1582 hubp_regs_init(3);1583 1584 if (hubp35_construct(hubp2, ctx, inst,1585 &hubp_regs[inst], &hubp_shift, &hubp_mask))1586 return &hubp2->base;1587 1588 BREAK_TO_DEBUGGER();1589 kfree(hubp2);1590 return NULL;1591}1592 1593static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)1594{1595 dcn35_dwbc_set_fgcg(1596 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);1597}1598 1599static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)1600{1601 int i;1602 uint32_t pipe_count = pool->res_cap->num_dwb;1603 1604 for (i = 0; i < pipe_count; i++) {1605 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),1606 GFP_KERNEL);1607 1608 if (!dwbc30) {1609 dm_error("DC: failed to create dwbc30!\n");1610 return false;1611 }1612 1613#undef REG_STRUCT1614#define REG_STRUCT dwbc35_regs1615 dwbc_regs_dcn3_init(0);1616 1617 dcn35_dwbc_construct(dwbc30, ctx,1618 &dwbc35_regs[i],1619 &dwbc35_shift,1620 &dwbc35_mask,1621 i);1622 1623 pool->dwbc[i] = &dwbc30->base;1624 1625 dcn35_dwbc_init(dwbc30, ctx);1626 }1627 return true;1628}1629 1630static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,1631 struct dc_context *ctx)1632{1633 dcn35_mmhubbub_set_fgcg(1634 mcif_wb30,1635 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);1636}1637 1638static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)1639{1640 int i;1641 uint32_t pipe_count = pool->res_cap->num_dwb;1642 1643 for (i = 0; i < pipe_count; i++) {1644 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),1645 GFP_KERNEL);1646 1647 if (!mcif_wb30) {1648 dm_error("DC: failed to create mcif_wb30!\n");1649 return false;1650 }1651 1652#undef REG_STRUCT1653#define REG_STRUCT mcif_wb35_regs1654 mcif_wb_regs_dcn3_init(0);1655 1656 dcn35_mmhubbub_construct(mcif_wb30, ctx,1657 &mcif_wb35_regs[i],1658 &mcif_wb35_shift,1659 &mcif_wb35_mask,1660 i);1661 1662 dcn35_mmhubbub_init(mcif_wb30, ctx);1663 1664 pool->mcif_wb[i] = &mcif_wb30->base;1665 }1666 return true;1667}1668 1669static struct display_stream_compressor *dcn35_dsc_create(1670 struct dc_context *ctx, uint32_t inst)1671{1672 struct dcn20_dsc *dsc =1673 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);1674 1675 if (!dsc) {1676 BREAK_TO_DEBUGGER();1677 return NULL;1678 }1679 1680#undef REG_STRUCT1681#define REG_STRUCT dsc_regs1682 dsc_regsDCN35_init(0),1683 dsc_regsDCN35_init(1),1684 dsc_regsDCN35_init(2),1685 dsc_regsDCN35_init(3);1686 1687 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);1688 dsc35_set_fgcg(dsc,1689 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);1690 return &dsc->base;1691}1692 1693static void dcn35_destroy_resource_pool(struct resource_pool **pool)1694{1695 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);1696 1697 dcn35_resource_destruct(dcn35_pool);1698 kfree(dcn35_pool);1699 *pool = NULL;1700}1701 1702static struct clock_source *dcn35_clock_source_create(1703 struct dc_context *ctx,1704 struct dc_bios *bios,1705 enum clock_source_id id,1706 const struct dce110_clk_src_regs *regs,1707 bool dp_clk_src)1708{1709 struct dce110_clk_src *clk_src =1710 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);1711 1712 if (!clk_src)1713 return NULL;1714 1715 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,1716 regs, &cs_shift, &cs_mask)) {1717 clk_src->base.dp_clk_src = dp_clk_src;1718 return &clk_src->base;1719 }1720 1721 kfree(clk_src);1722 BREAK_TO_DEBUGGER();1723 return NULL;1724}1725 1726static struct dc_cap_funcs cap_funcs = {1727 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap1728};1729 1730static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)1731{1732 *panel_config = panel_config_defaults;1733}1734 1735 1736static bool dcn35_validate_bandwidth(struct dc *dc,1737 struct dc_state *context,1738 bool fast_validate)1739{1740 bool out = false;1741 1742 out = dml2_validate(dc, context,1743 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,1744 fast_validate);1745 1746 if (fast_validate)1747 return out;1748 1749 DC_FP_START();1750 dcn35_decide_zstate_support(dc, context);1751 DC_FP_END();1752 1753 return out;1754}1755 1756 1757static struct resource_funcs dcn35_res_pool_funcs = {1758 .destroy = dcn35_destroy_resource_pool,1759 .link_enc_create = dcn35_link_encoder_create,1760 .link_enc_create_minimal = dcn31_link_enc_create_minimal,1761 .link_encs_assign = link_enc_cfg_link_encs_assign,1762 .link_enc_unassign = link_enc_cfg_link_enc_unassign,1763 .panel_cntl_create = dcn31_panel_cntl_create,1764 .validate_bandwidth = dcn35_validate_bandwidth,1765 .calculate_wm_and_dlg = NULL,1766 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,1767 .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,1768 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,1769 .release_pipe = dcn20_release_pipe,1770 .add_stream_to_ctx = dcn30_add_stream_to_ctx,1771 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,1772 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,1773 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,1774 .set_mcif_arb_params = dcn30_set_mcif_arb_params,1775 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,1776 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,1777 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,1778 .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,1779 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,1780 .get_panel_config_defaults = dcn35_get_panel_config_defaults,1781 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,1782};1783 1784static bool dcn35_resource_construct(1785 uint8_t num_virtual_links,1786 struct dc *dc,1787 struct dcn35_resource_pool *pool)1788{1789 int i;1790 struct dc_context *ctx = dc->ctx;1791 struct irq_service_init_data init_data;1792 1793#undef REG_STRUCT1794#define REG_STRUCT bios_regs1795 bios_regs_init();1796 1797#undef REG_STRUCT1798#define REG_STRUCT clk_src_regs1799 clk_src_regs_init(0, A),1800 clk_src_regs_init(1, B),1801 clk_src_regs_init(2, C),1802 clk_src_regs_init(3, D),1803 clk_src_regs_init(4, E);1804 1805#undef REG_STRUCT1806#define REG_STRUCT abm_regs1807 abm_regs_init(0),1808 abm_regs_init(1),1809 abm_regs_init(2),1810 abm_regs_init(3);1811 1812#undef REG_STRUCT1813#define REG_STRUCT dccg_regs1814 dccg_regs_init();1815 1816 ctx->dc_bios->regs = &bios_regs;1817 1818 pool->base.res_cap = &res_cap_dcn35;1819 1820 pool->base.funcs = &dcn35_res_pool_funcs;1821 1822 /*************************************************1823 * Resource + asic cap harcoding *1824 *************************************************/1825 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;1826 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;1827 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;1828 dc->caps.max_downscale_ratio = 600;1829 dc->caps.i2c_speed_in_khz = 100;1830 dc->caps.i2c_speed_in_khz_hdcp = 100;1831 dc->caps.max_cursor_size = 256;1832 dc->caps.min_horizontal_blanking_period = 80;1833 dc->caps.dmdata_alloc_size = 2048;1834 dc->caps.max_slave_planes = 2;1835 dc->caps.max_slave_yuv_planes = 2;1836 dc->caps.max_slave_rgb_planes = 2;1837 dc->caps.post_blend_color_processing = true;1838 dc->caps.force_dp_tps4_for_cp2520 = true;1839 if (dc->config.forceHBR2CP2520)1840 dc->caps.force_dp_tps4_for_cp2520 = false;1841 dc->caps.dp_hpo = true;1842 dc->caps.dp_hdmi21_pcon_support = true;1843 1844 dc->caps.edp_dsc_support = true;1845 dc->caps.extended_aux_timeout_support = true;1846 dc->caps.dmcub_support = true;1847 dc->caps.is_apu = true;1848 dc->caps.seamless_odm = true;1849 1850 dc->caps.zstate_support = true;1851 dc->caps.ips_support = true;1852 dc->caps.max_v_total = (1 << 15) - 1;1853 1854 /* Color pipeline capabilities */1855 dc->caps.color.dpp.dcn_arch = 1;1856 dc->caps.color.dpp.input_lut_shared = 0;1857 dc->caps.color.dpp.icsc = 1;1858 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr1859 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;1860 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;1861 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;1862 dc->caps.color.dpp.dgam_rom_caps.pq = 1;1863 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;1864 dc->caps.color.dpp.post_csc = 1;1865 dc->caps.color.dpp.gamma_corr = 1;1866 dc->caps.color.dpp.dgam_rom_for_yuv = 0;1867 1868 dc->caps.color.dpp.hw_3d_lut = 1;1869 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN11870 // no OGAM ROM on DCN3011871 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;1872 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;1873 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;1874 dc->caps.color.dpp.ogam_rom_caps.pq = 0;1875 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;1876 dc->caps.color.dpp.ocsc = 0;1877 1878 dc->caps.color.mpc.gamut_remap = 1;1879 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //21880 dc->caps.color.mpc.ogam_ram = 1;1881 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;1882 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;1883 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;1884 dc->caps.color.mpc.ogam_rom_caps.pq = 0;1885 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;1886 dc->caps.color.mpc.ocsc = 1;1887 1888 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order1889 * to provide some margin.1890 * It's expected for furture ASIC to have equal or higher value, in order to1891 * have determinstic power improvement from generate to genration.1892 * (i.e., we should not expect new ASIC generation with lower vmin rate)1893 */1894 dc->caps.max_disp_clock_khz_at_vmin = 650000;1895 1896 /* Sequential ONO is based on ASIC. */1897 if (dc->ctx->asic_id.hw_internal_rev > 0x10)1898 dc->caps.sequential_ono = true;1899 1900 /* Use pipe context based otg sync logic */1901 dc->config.use_pipe_ctx_sync_logic = true;1902 1903 dc->config.disable_hbr_audio_dp2 = true;1904 /* read VBIOS LTTPR caps */1905 {1906 if (ctx->dc_bios->funcs->get_lttpr_caps) {1907 enum bp_result bp_query_result;1908 uint8_t is_vbios_lttpr_enable = 0;1909 1910 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);1911 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;1912 }1913 1914 /* interop bit is implicit */1915 {1916 dc->caps.vbios_lttpr_aware = true;1917 }1918 }1919 1920 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)1921 dc->debug = debug_defaults_drv;1922 /*HW default is to have all the FGCG enabled, SW no need to program them*/1923 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;1924 // Init the vm_helper1925 if (dc->vm_helper)1926 vm_helper_init(dc->vm_helper, 16);1927 1928 /*************************************************1929 * Create resources *1930 *************************************************/1931 1932 /* Clock Sources for Pixel Clock*/1933 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =1934 dcn35_clock_source_create(ctx, ctx->dc_bios,1935 CLOCK_SOURCE_COMBO_PHY_PLL0,1936 &clk_src_regs[0], false);1937 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =1938 dcn35_clock_source_create(ctx, ctx->dc_bios,1939 CLOCK_SOURCE_COMBO_PHY_PLL1,1940 &clk_src_regs[1], false);1941 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =1942 dcn35_clock_source_create(ctx, ctx->dc_bios,1943 CLOCK_SOURCE_COMBO_PHY_PLL2,1944 &clk_src_regs[2], false);1945 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =1946 dcn35_clock_source_create(ctx, ctx->dc_bios,1947 CLOCK_SOURCE_COMBO_PHY_PLL3,1948 &clk_src_regs[3], false);1949 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =1950 dcn35_clock_source_create(ctx, ctx->dc_bios,1951 CLOCK_SOURCE_COMBO_PHY_PLL4,1952 &clk_src_regs[4], false);1953 1954 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;1955 1956 /* todo: not reuse phy_pll registers */1957 pool->base.dp_clock_source =1958 dcn35_clock_source_create(ctx, ctx->dc_bios,1959 CLOCK_SOURCE_ID_DP_DTO,1960 &clk_src_regs[0], true);1961 1962 for (i = 0; i < pool->base.clk_src_count; i++) {1963 if (pool->base.clock_sources[i] == NULL) {1964 dm_error("DC: failed to create clock sources!\n");1965 BREAK_TO_DEBUGGER();1966 goto create_fail;1967 }1968 }1969 /*temp till dml2 fully work without dml1*/1970 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);1971 1972 /* TODO: DCCG */1973 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);1974 if (pool->base.dccg == NULL) {1975 dm_error("DC: failed to create dccg!\n");1976 BREAK_TO_DEBUGGER();1977 goto create_fail;1978 }1979 1980#undef REG_STRUCT1981#define REG_STRUCT pg_cntl_regs1982 pg_cntl_dcn35_regs_init();1983 1984 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);1985 if (pool->base.pg_cntl == NULL) {1986 dm_error("DC: failed to create power gate control!\n");1987 BREAK_TO_DEBUGGER();1988 goto create_fail;1989 }1990 1991 /* TODO: IRQ */1992 init_data.ctx = dc->ctx;1993 pool->base.irqs = dal_irq_service_dcn35_create(&init_data);1994 if (!pool->base.irqs)1995 goto create_fail;1996 1997 /* HUBBUB */1998 pool->base.hubbub = dcn35_hubbub_create(ctx);1999 if (pool->base.hubbub == NULL) {2000 BREAK_TO_DEBUGGER();2001 dm_error("DC: failed to create hubbub!\n");2002 goto create_fail;2003 }2004 2005 /* HUBPs, DPPs, OPPs and TGs */2006 for (i = 0; i < pool->base.pipe_count; i++) {2007 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);2008 if (pool->base.hubps[i] == NULL) {2009 BREAK_TO_DEBUGGER();2010 dm_error(2011 "DC: failed to create hubps!\n");2012 goto create_fail;2013 }2014 2015 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);2016 if (pool->base.dpps[i] == NULL) {2017 BREAK_TO_DEBUGGER();2018 dm_error(2019 "DC: failed to create dpps!\n");2020 goto create_fail;2021 }2022 }2023 2024 for (i = 0; i < pool->base.res_cap->num_opp; i++) {2025 pool->base.opps[i] = dcn35_opp_create(ctx, i);2026 if (pool->base.opps[i] == NULL) {2027 BREAK_TO_DEBUGGER();2028 dm_error(2029 "DC: failed to create output pixel processor!\n");2030 goto create_fail;2031 }2032 }2033 2034 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2035 pool->base.timing_generators[i] = dcn35_timing_generator_create(2036 ctx, i);2037 if (pool->base.timing_generators[i] == NULL) {2038 BREAK_TO_DEBUGGER();2039 dm_error("DC: failed to create tg!\n");2040 goto create_fail;2041 }2042 }2043 pool->base.timing_generator_count = i;2044 2045 /* PSR */2046 pool->base.psr = dmub_psr_create(ctx);2047 if (pool->base.psr == NULL) {2048 dm_error("DC: failed to create psr obj!\n");2049 BREAK_TO_DEBUGGER();2050 goto create_fail;2051 }2052 2053 /* Replay */2054 pool->base.replay = dmub_replay_create(ctx);2055 if (pool->base.replay == NULL) {2056 dm_error("DC: failed to create replay obj!\n");2057 BREAK_TO_DEBUGGER();2058 goto create_fail;2059 }2060 2061 /* ABM */2062 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {2063 pool->base.multiple_abms[i] = dmub_abm_create(ctx,2064 &abm_regs[i],2065 &abm_shift,2066 &abm_mask);2067 if (pool->base.multiple_abms[i] == NULL) {2068 dm_error("DC: failed to create abm for pipe %d!\n", i);2069 BREAK_TO_DEBUGGER();2070 goto create_fail;2071 }2072 }2073 2074 /* MPC and DSC */2075 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);2076 if (pool->base.mpc == NULL) {2077 BREAK_TO_DEBUGGER();2078 dm_error("DC: failed to create mpc!\n");2079 goto create_fail;2080 }2081 2082 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {2083 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);2084 if (pool->base.dscs[i] == NULL) {2085 BREAK_TO_DEBUGGER();2086 dm_error("DC: failed to create display stream compressor %d!\n", i);2087 goto create_fail;2088 }2089 }2090 2091 /* DWB and MMHUBBUB */2092 if (!dcn35_dwbc_create(ctx, &pool->base)) {2093 BREAK_TO_DEBUGGER();2094 dm_error("DC: failed to create dwbc!\n");2095 goto create_fail;2096 }2097 2098 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {2099 BREAK_TO_DEBUGGER();2100 dm_error("DC: failed to create mcif_wb!\n");2101 goto create_fail;2102 }2103 2104 /* AUX and I2C */2105 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {2106 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);2107 if (pool->base.engines[i] == NULL) {2108 BREAK_TO_DEBUGGER();2109 dm_error(2110 "DC:failed to create aux engine!!\n");2111 goto create_fail;2112 }2113 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);2114 if (pool->base.hw_i2cs[i] == NULL) {2115 BREAK_TO_DEBUGGER();2116 dm_error(2117 "DC:failed to create hw i2c!!\n");2118 goto create_fail;2119 }2120 pool->base.sw_i2cs[i] = NULL;2121 }2122 2123 /* DCN3.5 has 6 DPIA */2124 pool->base.usb4_dpia_count = 4;2125 if (dc->debug.dpia_debug.bits.disable_dpia)2126 pool->base.usb4_dpia_count = 0;2127 2128 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */2129 if (!resource_construct(num_virtual_links, dc, &pool->base,2130 &res_create_funcs))2131 goto create_fail;2132 2133 /* HW Sequencer and Plane caps */2134 dcn35_hw_sequencer_construct(dc);2135 2136 dc->caps.max_planes = pool->base.pipe_count;2137 2138 for (i = 0; i < dc->caps.max_planes; ++i)2139 dc->caps.planes[i] = plane_cap;2140 2141 dc->cap_funcs = cap_funcs;2142 2143 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;2144 2145 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;2146 dc->dml2_options.use_native_pstate_optimization = true;2147 dc->dml2_options.use_native_soc_bb_construction = true;2148 dc->dml2_options.minimize_dispclk_using_odm = false;2149 if (dc->config.EnableMinDispClkODM)2150 dc->dml2_options.minimize_dispclk_using_odm = true;2151 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;2152 2153 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);2154 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;2155 2156 dc->dml2_options.max_segments_per_hubp = 24;2157 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/2158 dc->dml2_options.override_det_buffer_size_kbytes = true;2159 2160 if (dc->config.sdpif_request_limit_words_per_umc == 0)2161 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/2162 2163 return true;2164 2165create_fail:2166 2167 dcn35_resource_destruct(pool);2168 2169 return false;2170}2171 2172struct resource_pool *dcn35_create_resource_pool(2173 const struct dc_init_data *init_data,2174 struct dc *dc)2175{2176 struct dcn35_resource_pool *pool =2177 kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL);2178 2179 if (!pool)2180 return NULL;2181 2182 if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))2183 return &pool->base;2184 2185 BREAK_TO_DEBUGGER();2186 kfree(pool);2187 return NULL;2188}2189