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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2023 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#ifndef _DCN35_RESOURCE_H_28#define _DCN35_RESOURCE_H_29 30#include "core_types.h"31 32#define DCN3_5_VMIN_DISPCLK_HZ 71700000033#define TO_DCN35_RES_POOL(pool)\34 container_of(pool, struct dcn35_resource_pool, base)35 36extern struct _vcs_dpi_ip_params_st dcn3_5_ip;37extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc;38 39struct dcn35_resource_pool {40 struct resource_pool base;41};42 43struct resource_pool *dcn35_create_resource_pool(44 const struct dc_init_data *init_data,45 struct dc *dc);46 47/* Defs for runtime init of registers */48 49#define OPP_REG_LIST_DCN20_RI(id) \50 OPP_REG_LIST_DCN10_RI(id), \51 OPP_DPG_REG_LIST_RI(id), \52 SRI_ARR(FMT_422_CONTROL, FMT, id), \53 SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)54 55#define OPP_REG_LIST_DCN35_RI(id) \56 OPP_REG_LIST_DCN20_RI(id), \57 SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)58 59#define VPG_DCN31_REG_LIST_RI(id) \60 SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \61 SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \62 SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \63 SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \64 SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \65 SRI_ARR(VPG_MEM_PWR, VPG, id)66 67#define AFMT_DCN31_REG_LIST_RI(id) \68 SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \69 SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \70 SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \71 SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \72 SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \73 SRI_ARR(AFMT_60958_0, AFMT, id), \74 SRI_ARR(AFMT_60958_1, AFMT, id), \75 SRI_ARR(AFMT_60958_2, AFMT, id), \76 SRI_ARR(AFMT_MEM_PWR, AFMT, id)77 78/* Stream encoder */79#define SE_DCN35_REG_LIST_RI(id) \80 SRI_ARR(AFMT_CNTL, DIG, id), \81 SRI_ARR(DIG_FE_CNTL, DIG, id), \82 SRI_ARR(HDMI_CONTROL, DIG, id), \83 SRI_ARR(HDMI_DB_CONTROL, DIG, id), \84 SRI_ARR(HDMI_GC, DIG, id), \85 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \86 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \87 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \88 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \89 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \90 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \91 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \92 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \93 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \94 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \95 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \96 SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \97 SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \98 SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \99 SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\100 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),\101 SRI_ARR(HDMI_ACR_32_0, DIG, id),\102 SRI_ARR(HDMI_ACR_32_1, DIG, id),\103 SRI_ARR(HDMI_ACR_44_0, DIG, id),\104 SRI_ARR(HDMI_ACR_44_1, DIG, id),\105 SRI_ARR(HDMI_ACR_48_0, DIG, id),\106 SRI_ARR(HDMI_ACR_48_1, DIG, id),\107 SRI_ARR(DP_DB_CNTL, DP, id), \108 SRI_ARR(DP_MSA_MISC, DP, id), \109 SRI_ARR(DP_MSA_VBID_MISC, DP, id), \110 SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \111 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \112 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \113 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \114 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \115 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), \116 SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \117 SRI_ARR(DP_PIXEL_FORMAT, DP, id), \118 SRI_ARR(DP_SEC_CNTL, DP, id), \119 SRI_ARR(DP_SEC_CNTL1, DP, id), \120 SRI_ARR(DP_SEC_CNTL2, DP, id), \121 SRI_ARR(DP_SEC_CNTL5, DP, id), \122 SRI_ARR(DP_SEC_CNTL6, DP, id), \123 SRI_ARR(DP_STEER_FIFO, DP, id), \124 SRI_ARR(DP_VID_M, DP, id), \125 SRI_ARR(DP_VID_N, DP, id), \126 SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \127 SRI_ARR(DP_VID_TIMING, DP, id), \128 SRI_ARR(DP_SEC_AUD_N, DP, id), \129 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \130 SRI_ARR(DP_DSC_CNTL, DP, id), \131 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \132 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \133 SRI_ARR(DP_SEC_FRAMING4, DP, id), \134 SRI_ARR(DP_GSP11_CNTL, DP, id), \135 SRI_ARR(DME_CONTROL, DME, id),\136 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \137 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \138 SRI_ARR(DIG_FE_CNTL, DIG, id), \139 SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \140 SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \141 SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \142 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \143 SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)144 145#define LE_DCN35_REG_LIST_RI(id)\146 LE_DCN3_REG_LIST_RI(id),\147 SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \148 SR_ARR(DIO_LINKA_CNTL, id), \149 SR_ARR(DIO_LINKB_CNTL, id), \150 SR_ARR(DIO_LINKC_CNTL, id), \151 SR_ARR(DIO_LINKD_CNTL, id), \152 SR_ARR(DIO_LINKE_CNTL, id), \153 SR_ARR(DIO_LINKF_CNTL, id),\154 SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\155 SR_ARR(DIO_CLK_CNTL, id)156 157#define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst) \158 MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst), \159 SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)160 161#define HWSEQ_DCN35_REG_LIST()\162 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \163 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \164 SR(DIO_MEM_PWR_CTRL), \165 SR(ODM_MEM_PWR_CTRL3), \166 SR(MMHUBBUB_MEM_PWR_CNTL), \167 SR(DCCG_GATE_DISABLE_CNTL), \168 SR(DCCG_GATE_DISABLE_CNTL2), \169 SR(DCCG_GATE_DISABLE_CNTL4), \170 SR(DCCG_GATE_DISABLE_CNTL5), \171 SR(DCFCLK_CNTL),\172 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \173 SRII(PIXEL_RATE_CNTL, OTG, 0), \174 SRII(PIXEL_RATE_CNTL, OTG, 1),\175 SRII(PIXEL_RATE_CNTL, OTG, 2),\176 SRII(PIXEL_RATE_CNTL, OTG, 3),\177 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\178 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\179 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\180 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\181 SR(MICROSECOND_TIME_BASE_DIV), \182 SR(MILLISECOND_TIME_BASE_DIV), \183 SR(DISPCLK_FREQ_CHANGE_CNTL), \184 SR(RBBMIF_TIMEOUT_DIS), \185 SR(RBBMIF_TIMEOUT_DIS_2), \186 SR(DCHUBBUB_CRC_CTRL), \187 SR(DPP_TOP0_DPP_CRC_CTRL), \188 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \189 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \190 SR(MPC_CRC_CTRL), \191 SR(MPC_CRC_RESULT_GB), \192 SR(MPC_CRC_RESULT_C), \193 SR(MPC_CRC_RESULT_AR), \194 SR(DOMAIN0_PG_CONFIG), \195 SR(DOMAIN1_PG_CONFIG), \196 SR(DOMAIN2_PG_CONFIG), \197 SR(DOMAIN3_PG_CONFIG), \198 SR(DOMAIN16_PG_CONFIG), \199 SR(DOMAIN17_PG_CONFIG), \200 SR(DOMAIN18_PG_CONFIG), \201 SR(DOMAIN19_PG_CONFIG), \202 SR(DOMAIN0_PG_STATUS), \203 SR(DOMAIN1_PG_STATUS), \204 SR(DOMAIN2_PG_STATUS), \205 SR(DOMAIN3_PG_STATUS), \206 SR(DOMAIN16_PG_STATUS), \207 SR(DOMAIN17_PG_STATUS), \208 SR(DOMAIN18_PG_STATUS), \209 SR(DOMAIN19_PG_STATUS), \210 SR(DC_IP_REQUEST_CNTL), \211 SR(AZALIA_AUDIO_DTO), \212 SR(AZALIA_CONTROLLER_CLOCK_GATING), \213 SR(HPO_TOP_HW_CONTROL),\214 SR(DMU_CLK_CNTL)215 216/* OPTC */217#define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst) \218 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\219 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\220 SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\221 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\222 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\223 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\224 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\225 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\226 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\227 SRI_ARR(OTG_H_TOTAL, OTG, inst),\228 SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\229 SRI_ARR(OTG_H_SYNC_A, OTG, inst),\230 SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\231 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\232 SRI_ARR(OTG_V_TOTAL, OTG, inst),\233 SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\234 SRI_ARR(OTG_V_SYNC_A, OTG, inst),\235 SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\236 SRI_ARR(OTG_CONTROL, OTG, inst),\237 SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\238 SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\239 SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\240 SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\241 SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\242 SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\243 SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\244 SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\245 SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\246 SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\247 SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\248 SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\249 SRI_ARR(OTG_STATUS, OTG, inst),\250 SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\251 SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\252 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\253 SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\254 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\255 SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\256 SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\257 SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\258 SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\259 SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\260 SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\261 SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\262 SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\263 SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\264 SRI_ARR(CONTROL, VTG, inst),\265 SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\266 SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\267 SRI_ARR(OTG_CRC_CNTL, OTG, inst),\268 SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\269 SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\270 SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\271 SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\272 SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\273 SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\274 SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\275 SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\276 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\277 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\278 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\279 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\280 SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\281 SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\282 SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\283 SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\284 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\285 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\286 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\287 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\288 SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\289 SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\290 SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\291 SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\292 SR_ARR(GSL_SOURCE_SELECT, inst),\293 SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\294 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\295 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\296 SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\297 SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\298 SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\299 SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\300 SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\301 SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\302 SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\303 SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\304 SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\305 SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\306 SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\307 SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst)308 309/* DPP */310#define DPP_REG_LIST_DCN35_RI(id)\311 DPP_REG_LIST_DCN30_COMMON_RI(id)312 313#endif /* _DCN35_RESOURCE_H_ */314