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1// SPDX-License-Identifier: MIT2//3// Copyright 2024 Advanced Micro Devices, Inc.4 5#ifndef _DCN401_RESOURCE_H_6#define _DCN401_RESOURCE_H_7 8#include "core_types.h"9#include "dcn32/dcn32_resource.h"10#include "dcn401/dcn401_hubp.h"11 12#define TO_DCN401_RES_POOL(pool)\13 container_of(pool, struct dcn401_resource_pool, base)14 15struct dcn401_resource_pool {16 struct resource_pool base;17};18 19struct resource_pool *dcn401_create_resource_pool(20 const struct dc_init_data *init_data,21 struct dc *dc);22 23enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);24 25bool dcn401_validate_bandwidth(struct dc *dc,26 struct dc_state *context,27 bool fast_validate);28 29void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);30 31/* Following are definitions for run time init of reg offsets */32 33/* HUBP */34#define HUBP_REG_LIST_DCN401_RI(id) \35 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \36 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \37 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \38 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \39 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \40 SRI_ARR(DCHUBP_CNTL, HUBP, id), \41 SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \42 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \43 SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \44 SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \45 SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \46 SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \47 SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \48 SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \49 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \50 SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \51 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \52 SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \53 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \54 SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \55 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \56 SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \57 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \58 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \59 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \60 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \61 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \62 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \63 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \64 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \65 SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \66 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \67 SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \68 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \69 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \70 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \71 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \72 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \73 SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \74 SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \75 SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \76 SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \77 SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \78 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \79 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \80 SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \81 SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \82 SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \83 SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \84 SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \85 SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \86 SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \87 SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \88 SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \89 SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \90 SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \91 SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \92 SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \93 SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \94 SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \95 SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \96 SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \97 SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \98 SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \99 SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \100 SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \101 SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \102 SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \103 SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \104 SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \105 SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \106 SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \107 SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \108 SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \109 SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \110 SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \111 SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \112 SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \113 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \114 SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \115 SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \116 SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \117 SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \118 SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \119 SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \120 SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \121 SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \122 SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \123 SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \124 SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \125 SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \126 SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \127 SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \128 SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \129 SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \130 SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id), \131 SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \132 SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \133 SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \134 SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \135 SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \136 SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id), \137 SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id), \138 SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \139 SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \140 SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \141 HUBP_3DLUT_FL_REG_LIST_DCN401(id), \142 SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \143 SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id)144 145/* ABM */146#define ABM_DCN401_REG_LIST_RI(id) \147 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \148 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \149 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \150 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \151 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \152 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \153 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \154 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \155 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \156 SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \157 SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \158 SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \159 SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \160 SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \161 SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \162 SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \163 SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \164 SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \165 SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id), \166 SRI_ARR(DC_ABM1_ACE_THRES_DATA, ABM, id), \167 NBIO_SR_ARR(BIOS_SCRATCH_2, id)168 169/* VPG */170#define VPG_DCN401_REG_LIST_RI(id) \171 VPG_DCN3_REG_LIST_RI(id), \172 SRI_ARR(VPG_MEM_PWR, VPG, id)173 174/* Stream encoder */175#define SE_DCN4_01_REG_LIST_RI(id) \176 SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id), \177 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \178 SRI_ARR(HDMI_GC, DIG, id), \179 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \180 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \181 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \182 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \183 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \184 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \185 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \186 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \187 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \188 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \189 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \190 SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \191 SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \192 SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \193 SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \194 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \195 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \196 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \197 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \198 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \199 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \200 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \201 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \202 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \203 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \204 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \205 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \206 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \207 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \208 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \209 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \210 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \211 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \212 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \213 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \214 SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \215 SRI_ARR(DME_CONTROL, DME, id), \216 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \217 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \218 SRI_ARR(DIG_FE_CNTL, DIG, id), \219 SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \220 SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \221 SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \222 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \223 SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)224 225/* Link encoder */226#define LE_DCN401_REG_LIST_RI(id) \227 LE_DCN3_REG_LIST_RI(id), \228 SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \229 SRI_ARR(DIG_BE_CLK_CNTL, DIG, id)230 231/* DPP */232#define DPP_REG_LIST_DCN401_COMMON_RI(id) \233 SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \234 SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \235 SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \236 SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \237 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \238 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \239 SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \240 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \241 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \242 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \243 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \244 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \245 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \246 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \247 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \248 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \249 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \250 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \251 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \252 SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \253 SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \254 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \255 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \256 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \257 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \258 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \259 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \260 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \261 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \262 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \263 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \264 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \265 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \266 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \267 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \268 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \269 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \270 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \271 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \272 SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \273 SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \274 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \275 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \276 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \277 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \278 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \279 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \280 SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \281 SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \282 SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \283 SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \284 SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \285 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \286 SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \287 SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \288 SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \289 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \290 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \291 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \292 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \293 SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \294 SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \295 SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \296 SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \297 SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \298 SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \299 SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \300 SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \301 SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \302 SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \303 SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \304 SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \305 SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \306 SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \307 SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \308 SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \309 SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \310 SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \311 SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \312 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \313 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \314 SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \315 SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \316 SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \317 SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \318 SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \319 SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \320 SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \321 SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \322 SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \323 SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \324 SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \325 SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \326 SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \327 SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \328 SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \329 SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \330 SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \331 SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \332 SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \333 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \334 SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id), \335 SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \336 SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \337 SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \338 SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \339 SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \340 SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \341 SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \342 SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \343 SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \344 SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \345 SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \346 SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \347 SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \348 SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \349 SRI_ARR(DSCL_CONTROL, DSCL, id), \350 SRI_ARR(DSCL_SC_MODE, DSCL, id), \351 SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \352 SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \353 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \354 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \355 SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \356 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \357 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \358 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \359 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \360 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \361 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \362 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \363 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \364 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \365 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \366 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \367 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \368 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \369 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \370 SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \371 SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \372 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \373 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \374 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \375 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \376 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \377 SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \378 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \379 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \380 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \381 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \382 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \383 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \384 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \385 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \386 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \387 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \388 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \389 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \390 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \391 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \392 SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \393 SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \394 SRI_ARR(ISHARP_MODE, DSCL, id), \395 SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \396 SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \397 SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \398 SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \399 SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \400 SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \401 SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \402 SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \403 SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \404 SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \405 SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \406 SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \407 SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \408 SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)409 410/* OPP */411#define OPP_REG_LIST_DCN401_RI(id) \412 OPP_REG_LIST_DCN10_RI(id), OPP_DPG_REG_LIST_RI(id), \413 SRI_ARR(FMT_422_CONTROL, FMT, id)414 415/* DSC */416#define DSC_REG_LIST_DCN401_RI(id) \417 SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \418 SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \419 SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \420 SRI_ARR(DSCC_STATUS, DSCC, id), \421 SRI_ARR(DSCC_INTERRUPT_CONTROL0, DSCC, id), \422 SRI_ARR(DSCC_INTERRUPT_CONTROL1, DSCC, id), \423 SRI_ARR(DSCC_INTERRUPT_STATUS0, DSCC, id), \424 SRI_ARR(DSCC_INTERRUPT_STATUS1, DSCC, id), \425 SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \426 SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \427 SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \428 SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \429 SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \430 SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \431 SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \432 SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \433 SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \434 SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \435 SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \436 SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \437 SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \438 SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \439 SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \440 SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \441 SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \442 SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \443 SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \444 SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \445 SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \446 SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \447 SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \448 SRI_ARR(DSCC_MEM_POWER_CONTROL0, DSCC, id), \449 SRI_ARR(DSCC_MEM_POWER_CONTROL1, DSCC, id), \450 SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id), \451 SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id), \452 SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id), \453 SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id), \454 SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id), \455 SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id), \456 SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id), \457 SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id), \458 SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC, id), \459 SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC, id), \460 SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC, id), \461 SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC, id), \462 SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id), \463 SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \464 SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)465 466/* MPC */467#define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst) \468 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)469 470#define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst) \471 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)472 473#define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst) \474 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)475 476/* OPTC */477#define OPTC_COMMON_REG_LIST_DCN401_RI(inst) \478 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \479 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \480 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \481 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \482 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \483 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \484 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \485 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \486 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \487 SRI_ARR(OTG_H_TOTAL, OTG, inst), \488 SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \489 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \490 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \491 SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \492 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \493 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \494 SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \495 SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \496 SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \497 SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \498 SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \499 SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \500 SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \501 SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \502 SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \503 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \504 SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \505 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \506 SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \507 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \508 SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \509 SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \510 SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \511 SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \512 SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \513 SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \514 SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \515 SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \516 SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \517 SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \518 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \519 SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \520 SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \521 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \522 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \523 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \524 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \525 SR_ARR(GSL_SOURCE_SELECT, inst), \526 SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \527 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \528 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \529 SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \530 SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \531 SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \532 SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \533 SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \534 SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \535 SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \536 SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \537 SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \538 SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \539 SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \540 SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst)541 542/* HUBBUB */543#define HUBBUB_REG_LIST_DCN4_01_RI(id) \544 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \545 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \546 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \547 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \548 SR(DCHUBBUB_ARB_SAT_LEVEL), \549 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), \550 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \551 SR(DCHUBBUB_TEST_DEBUG_INDEX), \552 SR(DCHUBBUB_TEST_DEBUG_DATA), \553 SR(DCHUBBUB_SOFT_RESET), \554 SR(DCHUBBUB_CRC_CTRL), \555 SR(DCN_VM_FB_LOCATION_BASE), \556 SR(DCN_VM_FB_LOCATION_TOP), \557 SR(DCN_VM_FB_OFFSET), \558 SR(DCN_VM_AGP_BOT), \559 SR(DCN_VM_AGP_TOP), \560 SR(DCN_VM_AGP_BASE), \561 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A), \562 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A), \563 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B), \564 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B), \565 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A), \566 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A), \567 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B), \568 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B), \569 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A), \570 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A), \571 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B), \572 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B), \573 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A), \574 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A), \575 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B), \576 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B), \577 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), \578 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \579 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A), \580 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B), \581 SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A), \582 SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B), \583 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A), \584 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B), \585 SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A), \586 SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B), \587 SR(DCHUBBUB_DET0_CTRL), \588 SR(DCHUBBUB_DET1_CTRL), \589 SR(DCHUBBUB_DET2_CTRL), \590 SR(DCHUBBUB_DET3_CTRL), \591 SR(DCHUBBUB_COMPBUF_CTRL), \592 SR(COMPBUF_RESERVED_SPACE), \593 SR(DCHUBBUB_DEBUG_CTRL_0), \594 SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL), \595 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A), \596 SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B), \597 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A), \598 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B), \599 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A), \600 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B), \601 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A), \602 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \603 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A), \604 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B), \605 SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \606 SR(DCN_VM_FAULT_CNTL), \607 SR(DCN_VM_FAULT_STATUS), \608 SR(SDPIF_REQUEST_RATE_LIMIT), \609 SR(DCHUBBUB_CLOCK_CNTL), \610 SR(DCHUBBUB_SDPIF_CFG0), \611 SR(DCHUBBUB_SDPIF_CFG1), \612 SR(DCHUBBUB_MEM_PWR_MODE_CTRL)613 614/* DCCG */615 616#define DCCG_REG_LIST_DCN401_RI() \617 SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \618 DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \619 DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \620 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \621 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \622 SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \623 SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL), \624 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \625 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \626 SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \627 SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL), \628 SR(DPPCLK_CTRL), \629 DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1), \630 DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3), \631 DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \632 DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \633 SR(DSCCLK0_DTO_PARAM),\634 SR(DSCCLK1_DTO_PARAM),\635 SR(DSCCLK2_DTO_PARAM),\636 SR(DSCCLK3_DTO_PARAM),\637 SR(DSCCLK_DTO_CTRL),\638 SR(DCCG_GATE_DISABLE_CNTL),\639 SR(DCCG_GATE_DISABLE_CNTL2),\640 SR(DCCG_GATE_DISABLE_CNTL3),\641 SR(DCCG_GATE_DISABLE_CNTL4),\642 SR(DCCG_GATE_DISABLE_CNTL5),\643 SR(DCCG_GATE_DISABLE_CNTL6),\644 SR(SYMCLKA_CLOCK_ENABLE),\645 SR(SYMCLKB_CLOCK_ENABLE),\646 SR(SYMCLKC_CLOCK_ENABLE),\647 SR(SYMCLKD_CLOCK_ENABLE)648 649#endif /* _DCN401_RESOURCE_H_ */650