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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef DMUB_CMD_H27#define DMUB_CMD_H28 29#include <asm/byteorder.h>30#include <linux/types.h>31#include <linux/string.h>32#include <linux/delay.h>33 34#include "atomfirmware.h"35 36//<DMUB_TYPES>==================================================================37/* Basic type definitions. */38 39#define __forceinline inline40 41/**42 * Flag from driver to indicate that ABM should be disabled gradually43 * by slowly reversing all backlight programming and pixel compensation.44 */45#define SET_ABM_PIPE_GRADUALLY_DISABLE 046 47/**48 * Flag from driver to indicate that ABM should be disabled immediately49 * and undo all backlight programming and pixel compensation.50 */51#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 25552 53/**54 * Flag from driver to indicate that ABM should be disabled immediately55 * and keep the current backlight programming and pixel compensation.56 */57#define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 25458 59/**60 * Flag from driver to set the current ABM pipe index or ABM operating level.61 */62#define SET_ABM_PIPE_NORMAL 163 64/**65 * Number of ambient light levels in ABM algorithm.66 */67#define NUM_AMBI_LEVEL 568 69/**70 * Number of operating/aggression levels in ABM algorithm.71 */72#define NUM_AGGR_LEVEL 473 74/**75 * Number of segments in the gamma curve.76 */77#define NUM_POWER_FN_SEGS 878 79/**80 * Number of segments in the backlight curve.81 */82#define NUM_BL_CURVE_SEGS 1683 84/**85 * Maximum number of segments in ABM ACE curve.86 */87#define ABM_MAX_NUM_OF_ACE_SEGMENTS 6488 89/**90 * Maximum number of bins in ABM histogram.91 */92#define ABM_MAX_NUM_OF_HG_BINS 6493 94/* Maximum number of SubVP streams */95#define DMUB_MAX_SUBVP_STREAMS 296 97/* Define max FPO streams as 4 for now. Current implementation today98 * only supports 1, but could be more in the future. Reduce array99 * size to ensure the command size remains less than 64 bytes if100 * adding new fields.101 */102#define DMUB_MAX_FPO_STREAMS 4103 104/* Maximum number of streams on any ASIC. */105#define DMUB_MAX_STREAMS 6106 107/* Maximum number of planes on any ASIC. */108#define DMUB_MAX_PLANES 6109 110/* Maximum number of phantom planes on any ASIC */111#define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)112 113/* Trace buffer offset for entry */114#define TRACE_BUFFER_ENTRY_OFFSET 16115 116/**117 * Maximum number of dirty rects supported by FW.118 */119#define DMUB_MAX_DIRTY_RECTS 3120 121/**122 *123 * PSR control version legacy124 */125#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0126/**127 * PSR control version with multi edp support128 */129#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1130 131 132/**133 * ABM control version legacy134 */135#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0136 137/**138 * ABM control version with multi edp support139 */140#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1141 142/**143 * Physical framebuffer address location, 64-bit.144 */145#ifndef PHYSICAL_ADDRESS_LOC146#define PHYSICAL_ADDRESS_LOC union large_integer147#endif148 149/**150 * OS/FW agnostic memcpy151 */152#ifndef dmub_memcpy153#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))154#endif155 156/**157 * OS/FW agnostic memset158 */159#ifndef dmub_memset160#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))161#endif162 163/**164 * OS/FW agnostic udelay165 */166#ifndef dmub_udelay167#define dmub_udelay(microseconds) udelay(microseconds)168#endif169 170#pragma pack(push, 1)171#define ABM_NUM_OF_ACE_SEGMENTS 5172 173union abm_flags {174 struct {175 /**176 * @abm_enabled: Indicates if ABM is enabled.177 */178 unsigned int abm_enabled : 1;179 180 /**181 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.182 */183 unsigned int disable_abm_requested : 1;184 185 /**186 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.187 */188 unsigned int disable_abm_immediately : 1;189 190 /**191 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM192 * to be disabled immediately and keep gain.193 */194 unsigned int disable_abm_immediate_keep_gain : 1;195 196 /**197 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.198 */199 unsigned int fractional_pwm : 1;200 201 /**202 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment203 * of user backlight level.204 */205 unsigned int abm_gradual_bl_change : 1;206 207 /**208 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady209 */210 unsigned int abm_new_frame : 1;211 212 /**213 * @vb_scaling_enabled: Indicates variBright Scaling Enable214 */215 unsigned int vb_scaling_enabled : 1;216 } bitfields;217 218 unsigned int u32All;219};220 221struct abm_save_restore {222 /**223 * @flags: Misc. ABM flags.224 */225 union abm_flags flags;226 227 /**228 * @pause: true: pause ABM and get state229 * false: unpause ABM after setting state230 */231 uint32_t pause;232 233 /**234 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)235 */236 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];237 238 /**239 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)240 */241 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];242 243 /**244 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)245 */246 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];247 248 249 /**250 * @knee_threshold: Current x-position of ACE knee (u0.16).251 */252 uint32_t knee_threshold;253 /**254 * @current_gain: Current backlight reduction (u16.16).255 */256 uint32_t current_gain;257 /**258 * @curr_bl_level: Current actual backlight level converging to target backlight level.259 */260 uint16_t curr_bl_level;261 262 /**263 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.264 */265 uint16_t curr_user_bl_level;266 267};268 269/**270 * union dmub_addr - DMUB physical/virtual 64-bit address.271 */272union dmub_addr {273 struct {274 uint32_t low_part; /**< Lower 32 bits */275 uint32_t high_part; /**< Upper 32 bits */276 } u; /*<< Low/high bit access */277 uint64_t quad_part; /*<< 64 bit address */278};279#pragma pack(pop)280 281/**282 * Dirty rect definition.283 */284struct dmub_rect {285 /**286 * Dirty rect x offset.287 */288 uint32_t x;289 290 /**291 * Dirty rect y offset.292 */293 uint32_t y;294 295 /**296 * Dirty rect width.297 */298 uint32_t width;299 300 /**301 * Dirty rect height.302 */303 uint32_t height;304};305 306/**307 * Flags that can be set by driver to change some PSR behaviour.308 */309union dmub_psr_debug_flags {310 /**311 * Debug flags.312 */313 struct {314 /**315 * Enable visual confirm in FW.316 */317 uint32_t visual_confirm : 1;318 319 /**320 * Force all selective updates to bw full frame updates.321 */322 uint32_t force_full_frame_update : 1;323 324 /**325 * Use HW Lock Mgr object to do HW locking in FW.326 */327 uint32_t use_hw_lock_mgr : 1;328 329 /**330 * Use TPS3 signal when restore main link.331 */332 uint32_t force_wakeup_by_tps3 : 1;333 334 /**335 * Back to back flip, therefore cannot power down PHY336 */337 uint32_t back_to_back_flip : 1;338 339 /**340 * Enable visual confirm for IPS341 */342 uint32_t enable_ips_visual_confirm : 1;343 } bitfields;344 345 /**346 * Union for debug flags.347 */348 uint32_t u32All;349};350 351/**352 * Flags that can be set by driver to change some Replay behaviour.353 */354union replay_debug_flags {355 struct {356 /**357 * 0x1 (bit 0)358 * Enable visual confirm in FW.359 */360 uint32_t visual_confirm : 1;361 362 /**363 * 0x2 (bit 1)364 * @skip_crc: Set if need to skip CRC.365 */366 uint32_t skip_crc : 1;367 368 /**369 * 0x4 (bit 2)370 * @force_link_power_on: Force disable ALPM control371 */372 uint32_t force_link_power_on : 1;373 374 /**375 * 0x8 (bit 3)376 * @force_phy_power_on: Force phy power on377 */378 uint32_t force_phy_power_on : 1;379 380 /**381 * 0x10 (bit 4)382 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync383 */384 uint32_t timing_resync_disabled : 1;385 386 /**387 * 0x20 (bit 5)388 * @skip_crtc_disabled: CRTC disable skipped389 */390 uint32_t skip_crtc_disabled : 1;391 392 /**393 * 0x40 (bit 6)394 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode395 */396 uint32_t force_defer_one_frame_update : 1;397 398 /**399 * 0x80 (bit 7)400 * @disable_delay_alpm_on: Force disable delay alpm on401 */402 uint32_t disable_delay_alpm_on : 1;403 404 /**405 * 0x100 (bit 8)406 * @disable_desync_error_check: Force disable desync error check407 */408 uint32_t disable_desync_error_check : 1;409 410 /**411 * 0x200 (bit 9)412 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady413 */414 uint32_t force_self_update_when_abm_non_steady : 1;415 416 /**417 * 0x400 (bit 10)418 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS419 * If we enter IPS2, the Visual confirm bar will change to yellow420 */421 uint32_t enable_ips_visual_confirm : 1;422 423 /**424 * 0x800 (bit 11)425 * @enable_ips_residency_profiling: Enable IPS residency profiling426 */427 uint32_t enable_ips_residency_profiling : 1;428 429 uint32_t reserved : 20;430 } bitfields;431 432 uint32_t u32All;433};434 435union replay_hw_flags {436 struct {437 /**438 * @allow_alpm_fw_standby_mode: To indicate whether the439 * ALPM FW standby mode is allowed440 */441 uint32_t allow_alpm_fw_standby_mode : 1;442 443 /*444 * @dsc_enable_status: DSC enable status in driver445 */446 uint32_t dsc_enable_status : 1;447 448 /**449 * @fec_enable_status: receive fec enable/disable status from driver450 */451 uint32_t fec_enable_status : 1;452 453 /*454 * @smu_optimizations_en: SMU power optimization.455 * Only when active display is Replay capable and display enters Replay.456 * Trigger interrupt to SMU to powerup/down.457 */458 uint32_t smu_optimizations_en : 1;459 460 /**461 * @phy_power_state: Indicates current phy power state462 */463 uint32_t phy_power_state : 1;464 465 /**466 * @link_power_state: Indicates current link power state467 */468 uint32_t link_power_state : 1;469 /**470 * Use TPS3 signal when restore main link.471 */472 uint32_t force_wakeup_by_tps3 : 1;473 } bitfields;474 475 uint32_t u32All;476};477 478/**479 * DMUB feature capabilities.480 * After DMUB init, driver will query FW capabilities prior to enabling certain features.481 */482struct dmub_feature_caps {483 /**484 * Max PSR version supported by FW.485 */486 uint8_t psr;487 uint8_t fw_assisted_mclk_switch_ver;488 uint8_t reserved[4];489 uint8_t subvp_psr_support;490 uint8_t gecc_enable;491 uint8_t replay_supported;492 uint8_t replay_reserved[3];493};494 495struct dmub_visual_confirm_color {496 /**497 * Maximum 10 bits color value498 */499 uint16_t color_r_cr;500 uint16_t color_g_y;501 uint16_t color_b_cb;502 uint16_t panel_inst;503};504 505//==============================================================================506//</DMUB_TYPES>=================================================================507//==============================================================================508//< DMUB_META>==================================================================509//==============================================================================510#pragma pack(push, 1)511 512/* Magic value for identifying dmub_fw_meta_info */513#define DMUB_FW_META_MAGIC 0x444D5542514 515/* Offset from the end of the file to the dmub_fw_meta_info */516#define DMUB_FW_META_OFFSET 0x24517 518/**519 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization520 */521union dmub_fw_meta_feature_bits {522 struct {523 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */524 uint32_t reserved : 31;525 } bits; /**< status bits */526 uint32_t all; /**< 32-bit access to status bits */527};528 529/**530 * struct dmub_fw_meta_info - metadata associated with fw binary531 *532 * NOTE: This should be considered a stable API. Fields should533 * not be repurposed or reordered. New fields should be534 * added instead to extend the structure.535 *536 * @magic_value: magic value identifying DMUB firmware meta info537 * @fw_region_size: size of the firmware state region538 * @trace_buffer_size: size of the tracebuffer region539 * @fw_version: the firmware version information540 * @dal_fw: 1 if the firmware is DAL541 * @shared_state_size: size of the shared state region in bytes542 * @shared_state_features: number of shared state features543 */544struct dmub_fw_meta_info {545 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */546 uint32_t fw_region_size; /**< size of the firmware state region */547 uint32_t trace_buffer_size; /**< size of the tracebuffer region */548 uint32_t fw_version; /**< the firmware version information */549 uint8_t dal_fw; /**< 1 if the firmware is DAL */550 uint8_t reserved[3]; /**< padding bits */551 uint32_t shared_state_size; /**< size of the shared state region in bytes */552 uint16_t shared_state_features; /**< number of shared state features */553 uint16_t reserved2; /**< padding bytes */554 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */555};556 557/**558 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes559 */560union dmub_fw_meta {561 struct dmub_fw_meta_info info; /**< metadata info */562 uint8_t reserved[64]; /**< padding bits */563};564 565#pragma pack(pop)566 567//==============================================================================568//< DMUB Trace Buffer>================================================================569//==============================================================================570#if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)571/**572 * dmub_trace_code_t - firmware trace code, 32-bits573 */574typedef uint32_t dmub_trace_code_t;575 576/**577 * struct dmcub_trace_buf_entry - Firmware trace entry578 */579struct dmcub_trace_buf_entry {580 dmub_trace_code_t trace_code; /**< trace code for the event */581 uint32_t tick_count; /**< the tick count at time of trace */582 uint32_t param0; /**< trace defined parameter 0 */583 uint32_t param1; /**< trace defined parameter 1 */584};585#endif586 587//==============================================================================588//< DMUB_STATUS>================================================================589//==============================================================================590 591/**592 * DMCUB scratch registers can be used to determine firmware status.593 * Current scratch register usage is as follows:594 *595 * SCRATCH0: FW Boot Status register596 * SCRATCH5: LVTMA Status Register597 * SCRATCH15: FW Boot Options register598 */599 600/**601 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.602 */603union dmub_fw_boot_status {604 struct {605 uint32_t dal_fw : 1; /**< 1 if DAL FW */606 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */607 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */608 uint32_t restore_required : 1; /**< 1 if driver should call restore */609 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */610 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */611 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */612 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */613 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */614 } bits; /**< status bits */615 uint32_t all; /**< 32-bit access to status bits */616};617 618/**619 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.620 */621enum dmub_fw_boot_status_bit {622 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */623 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */624 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */625 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */626 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */627 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/628 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/629 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */630 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */631};632 633/* Register bit definition for SCRATCH5 */634union dmub_lvtma_status {635 struct {636 uint32_t psp_ok : 1;637 uint32_t edp_on : 1;638 uint32_t reserved : 30;639 } bits;640 uint32_t all;641};642 643enum dmub_lvtma_status_bit {644 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),645 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),646};647 648enum dmub_ips_disable_type {649 DMUB_IPS_ENABLE = 0,650 DMUB_IPS_DISABLE_ALL = 1,651 DMUB_IPS_DISABLE_IPS1 = 2,652 DMUB_IPS_DISABLE_IPS2 = 3,653 DMUB_IPS_DISABLE_IPS2_Z10 = 4,654 DMUB_IPS_DISABLE_DYNAMIC = 5,655 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,656};657 658#define DMUB_IPS1_ALLOW_MASK 0x00000001659#define DMUB_IPS2_ALLOW_MASK 0x00000002660#define DMUB_IPS1_COMMIT_MASK 0x00000004661#define DMUB_IPS2_COMMIT_MASK 0x00000008662 663/**664 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14665 */666union dmub_fw_boot_options {667 struct {668 uint32_t pemu_env : 1; /**< 1 if PEMU */669 uint32_t fpga_env : 1; /**< 1 if FPGA */670 uint32_t optimized_init : 1; /**< 1 if optimized init */671 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */672 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */673 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */674 uint32_t z10_disable: 1; /**< 1 to disable z10 */675 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */676 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */677 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */678 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */679 /**< 1 if all root clock gating is enabled and low power memory is enabled*/680 uint32_t power_optimization: 1;681 uint32_t diag_env: 1; /* 1 if diagnostic environment */682 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/683 uint32_t usb4_cm_version: 1; /**< 1 CM support */684 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */685 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/686 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/687 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */688 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/689 uint32_t ips_disable: 3; /* options to disable ips support*/690 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */691 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */692 uint32_t reserved : 7; /**< reserved */693 } bits; /**< boot bits */694 uint32_t all; /**< 32-bit access to bits */695};696 697enum dmub_fw_boot_options_bit {698 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */699 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */700 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */701};702 703//==============================================================================704//< DMUB_SHARED_STATE>==========================================================705//==============================================================================706 707/**708 * Shared firmware state between driver and firmware for lockless communication709 * in situations where the inbox/outbox may be unavailable.710 *711 * Each structure *must* be at most 256-bytes in size. The layout allocation is712 * described below:713 *714 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...715 */716 717/**718 * enum dmub_shared_state_feature_id - List of shared state features.719 */720enum dmub_shared_state_feature_id {721 DMUB_SHARED_SHARE_FEATURE__INVALID = 0,722 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,723 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,724 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */725};726 727/**728 * struct dmub_shared_state_ips_fw - Firmware signals for IPS.729 */730union dmub_shared_state_ips_fw_signals {731 struct {732 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */733 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */734 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */735 uint32_t detection_required : 1; /**< 1 if detection is required */736 uint32_t reserved_bits : 28; /**< Reversed */737 } bits;738 uint32_t all;739};740 741/**742 * struct dmub_shared_state_ips_signals - Firmware signals for IPS.743 */744union dmub_shared_state_ips_driver_signals {745 struct {746 uint32_t allow_pg : 1; /**< 1 if PG is allowed */747 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */748 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */749 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */750 uint32_t reserved_bits : 28; /**< Reversed bits */751 } bits;752 uint32_t all;753};754 755/**756 * IPS FW Version757 */758#define DMUB_SHARED_STATE__IPS_FW_VERSION 1759 760/**761 * struct dmub_shared_state_ips_fw - Firmware state for IPS.762 */763struct dmub_shared_state_ips_fw {764 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */765 uint32_t rcg_entry_count; /**< Entry counter for RCG */766 uint32_t rcg_exit_count; /**< Exit counter for RCG */767 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */768 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */769 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */770 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */771 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */772}; /* 248-bytes, fixed */773 774/**775 * IPS Driver Version776 */777#define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1778 779/**780 * struct dmub_shared_state_ips_driver - Driver state for IPS.781 */782struct dmub_shared_state_ips_driver {783 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */784 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */785}; /* 248-bytes, fixed */786 787/**788 * enum dmub_shared_state_feature_common - Generic payload.789 */790struct dmub_shared_state_feature_common {791 uint32_t padding[62];792}; /* 248-bytes, fixed */793 794/**795 * enum dmub_shared_state_feature_header - Feature description.796 */797struct dmub_shared_state_feature_header {798 uint16_t id; /**< Feature ID */799 uint16_t version; /**< Feature version */800 uint32_t reserved; /**< Reserved bytes. */801}; /* 8 bytes, fixed */802 803/**804 * struct dmub_shared_state_feature_block - Feature block.805 */806struct dmub_shared_state_feature_block {807 struct dmub_shared_state_feature_header header; /**< Shared state header. */808 union dmub_shared_feature_state_union {809 struct dmub_shared_state_feature_common common; /**< Generic data */810 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */811 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */812 } data; /**< Shared state data. */813}; /* 256-bytes, fixed */814 815/**816 * Shared state size in bytes.817 */818#define DMUB_FW_HEADER_SHARED_STATE_SIZE \819 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))820 821//==============================================================================822//</DMUB_STATUS>================================================================823//==============================================================================824//< DMUB_VBIOS>=================================================================825//==============================================================================826 827/*828 * enum dmub_cmd_vbios_type - VBIOS commands.829 *830 * Command IDs should be treated as stable ABI.831 * Do not reuse or modify IDs.832 */833enum dmub_cmd_vbios_type {834 /**835 * Configures the DIG encoder.836 */837 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,838 /**839 * Controls the PHY.840 */841 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,842 /**843 * Sets the pixel clock/symbol clock.844 */845 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,846 /**847 * Enables or disables power gating.848 */849 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,850 /**851 * Controls embedded panels.852 */853 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,854 /**855 * Query DP alt status on a transmitter.856 */857 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,858 /**859 * Control PHY FSM860 */861 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29,862 /**863 * Controls domain power gating864 */865 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,866};867 868//==============================================================================869//</DMUB_VBIOS>=================================================================870//==============================================================================871//< DMUB_GPINT>=================================================================872//==============================================================================873 874/**875 * The shifts and masks below may alternatively be used to format and read876 * the command register bits.877 */878 879#define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF880#define DMUB_GPINT_DATA_PARAM_SHIFT 0881 882#define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF883#define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16884 885#define DMUB_GPINT_DATA_STATUS_MASK 0xF886#define DMUB_GPINT_DATA_STATUS_SHIFT 28887 888/**889 * Command responses.890 */891 892/**893 * Return response for DMUB_GPINT__STOP_FW command.894 */895#define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD896 897/**898 * union dmub_gpint_data_register - Format for sending a command via the GPINT.899 */900union dmub_gpint_data_register {901 struct {902 uint32_t param : 16; /**< 16-bit parameter */903 uint32_t command_code : 12; /**< GPINT command */904 uint32_t status : 4; /**< Command status bit */905 } bits; /**< GPINT bit access */906 uint32_t all; /**< GPINT 32-bit access */907};908 909/*910 * enum dmub_gpint_command - GPINT command to DMCUB FW911 *912 * Command IDs should be treated as stable ABI.913 * Do not reuse or modify IDs.914 */915enum dmub_gpint_command {916 /**917 * Invalid command, ignored.918 */919 DMUB_GPINT__INVALID_COMMAND = 0,920 /**921 * DESC: Queries the firmware version.922 * RETURN: Firmware version.923 */924 DMUB_GPINT__GET_FW_VERSION = 1,925 /**926 * DESC: Halts the firmware.927 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted928 */929 DMUB_GPINT__STOP_FW = 2,930 /**931 * DESC: Get PSR state from FW.932 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.933 */934 DMUB_GPINT__GET_PSR_STATE = 7,935 /**936 * DESC: Notifies DMCUB of the currently active streams.937 * ARGS: Stream mask, 1 bit per active stream index.938 */939 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,940 /**941 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.942 * ARGS: We can measure residency from various points. The argument will specify the residency mode.943 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.944 * RETURN: PSR residency in milli-percent.945 */946 DMUB_GPINT__PSR_RESIDENCY = 9,947 948 /**949 * DESC: Notifies DMCUB detection is done so detection required can be cleared.950 */951 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,952 953 /**954 * DESC: Get REPLAY state from FW.955 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.956 */957 DMUB_GPINT__GET_REPLAY_STATE = 13,958 959 /**960 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.961 * ARGS: We can measure residency from various points. The argument will specify the residency mode.962 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.963 * RETURN: REPLAY residency in milli-percent.964 */965 DMUB_GPINT__REPLAY_RESIDENCY = 14,966 967 /**968 * DESC: Copy bounding box to the host.969 * ARGS: Version of bounding box to copy970 * RETURN: Result of copying bounding box971 */972 DMUB_GPINT__BB_COPY = 96,973 974 /**975 * DESC: Updates the host addresses bit48~bit63 for bounding box.976 * ARGS: The word3 for the 64 bit address977 */978 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,979 980 /**981 * DESC: Updates the host addresses bit32~bit47 for bounding box.982 * ARGS: The word2 for the 64 bit address983 */984 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,985 986 /**987 * DESC: Updates the host addresses bit16~bit31 for bounding box.988 * ARGS: The word1 for the 64 bit address989 */990 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,991 992 /**993 * DESC: Updates the host addresses bit0~bit15 for bounding box.994 * ARGS: The word0 for the 64 bit address995 */996 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,997 998 /**999 * DESC: Updates the trace buffer lower 32-bit mask.1000 * ARGS: The new mask1001 * RETURN: Lower 32-bit mask.1002 */1003 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,1004 1005 /**1006 * DESC: Updates the trace buffer mask bit0~bit15.1007 * ARGS: The new mask1008 * RETURN: Lower 32-bit mask.1009 */1010 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,1011 1012 /**1013 * DESC: Updates the trace buffer mask bit16~bit31.1014 * ARGS: The new mask1015 * RETURN: Lower 32-bit mask.1016 */1017 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,1018 1019 /**1020 * DESC: Updates the trace buffer mask bit32~bit47.1021 * ARGS: The new mask1022 * RETURN: Lower 32-bit mask.1023 */1024 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,1025 1026 /**1027 * DESC: Updates the trace buffer mask bit48~bit63.1028 * ARGS: The new mask1029 * RETURN: Lower 32-bit mask.1030 */1031 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,1032 1033 /**1034 * DESC: Read the trace buffer mask bi0~bit15.1035 */1036 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,1037 1038 /**1039 * DESC: Read the trace buffer mask bit16~bit31.1040 */1041 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,1042 1043 /**1044 * DESC: Read the trace buffer mask bi32~bit47.1045 */1046 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,1047 1048 /**1049 * DESC: Updates the trace buffer mask bit32~bit63.1050 */1051 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,1052 1053 /**1054 * DESC: Enable measurements for various task duration1055 * ARGS: 0 - Disable measurement1056 * 1 - Enable measurement1057 */1058 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,1059};1060 1061/**1062 * INBOX0 generic command definition1063 */1064union dmub_inbox0_cmd_common {1065 struct {1066 uint32_t command_code: 8; /**< INBOX0 command code */1067 uint32_t param: 24; /**< 24-bit parameter */1068 } bits;1069 uint32_t all;1070};1071 1072/**1073 * INBOX0 hw_lock command definition1074 */1075union dmub_inbox0_cmd_lock_hw {1076 struct {1077 uint32_t command_code: 8;1078 1079 /* NOTE: Must be have enough bits to match: enum hw_lock_client */1080 uint32_t hw_lock_client: 2;1081 1082 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */1083 uint32_t otg_inst: 3;1084 uint32_t opp_inst: 3;1085 uint32_t dig_inst: 3;1086 1087 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */1088 uint32_t lock_pipe: 1;1089 uint32_t lock_cursor: 1;1090 uint32_t lock_dig: 1;1091 uint32_t triple_buffer_lock: 1;1092 1093 uint32_t lock: 1; /**< Lock */1094 uint32_t should_release: 1; /**< Release */1095 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */1096 } bits;1097 uint32_t all;1098};1099 1100union dmub_inbox0_data_register {1101 union dmub_inbox0_cmd_common inbox0_cmd_common;1102 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;1103};1104 1105enum dmub_inbox0_command {1106 /**1107 * DESC: Invalid command, ignored.1108 */1109 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,1110 /**1111 * DESC: Notification to acquire/release HW lock1112 * ARGS:1113 */1114 DMUB_INBOX0_CMD__HW_LOCK = 1,1115};1116//==============================================================================1117//</DMUB_GPINT>=================================================================1118//==============================================================================1119//< DMUB_CMD>===================================================================1120//==============================================================================1121 1122/**1123 * Size in bytes of each DMUB command.1124 */1125#define DMUB_RB_CMD_SIZE 641126 1127/**1128 * Maximum number of items in the DMUB ringbuffer.1129 */1130#define DMUB_RB_MAX_ENTRY 1281131 1132/**1133 * Ringbuffer size in bytes.1134 */1135#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)1136 1137/**1138 * REG_SET mask for reg offload.1139 */1140#define REG_SET_MASK 0xFFFF1141 1142/*1143 * enum dmub_cmd_type - DMUB inbox command.1144 *1145 * Command IDs should be treated as stable ABI.1146 * Do not reuse or modify IDs.1147 */1148enum dmub_cmd_type {1149 /**1150 * Invalid command.1151 */1152 DMUB_CMD__NULL = 0,1153 /**1154 * Read modify write register sequence offload.1155 */1156 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,1157 /**1158 * Field update register sequence offload.1159 */1160 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,1161 /**1162 * Burst write sequence offload.1163 */1164 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,1165 /**1166 * Reg wait sequence offload.1167 */1168 DMUB_CMD__REG_REG_WAIT = 4,1169 /**1170 * Workaround to avoid HUBP underflow during NV12 playback.1171 */1172 DMUB_CMD__PLAT_54186_WA = 5,1173 /**1174 * Command type used to query FW feature caps.1175 */1176 DMUB_CMD__QUERY_FEATURE_CAPS = 6,1177 /**1178 * Command type used to get visual confirm color.1179 */1180 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,1181 /**1182 * Command type used for all PSR commands.1183 */1184 DMUB_CMD__PSR = 64,1185 /**1186 * Command type used for all MALL commands.1187 */1188 DMUB_CMD__MALL = 65,1189 /**1190 * Command type used for all ABM commands.1191 */1192 DMUB_CMD__ABM = 66,1193 /**1194 * Command type used to update dirty rects in FW.1195 */1196 DMUB_CMD__UPDATE_DIRTY_RECT = 67,1197 /**1198 * Command type used to update cursor info in FW.1199 */1200 DMUB_CMD__UPDATE_CURSOR_INFO = 68,1201 /**1202 * Command type used for HW locking in FW.1203 */1204 DMUB_CMD__HW_LOCK = 69,1205 /**1206 * Command type used to access DP AUX.1207 */1208 DMUB_CMD__DP_AUX_ACCESS = 70,1209 /**1210 * Command type used for OUTBOX1 notification enable1211 */1212 DMUB_CMD__OUTBOX1_ENABLE = 71,1213 1214 /**1215 * Command type used for all idle optimization commands.1216 */1217 DMUB_CMD__IDLE_OPT = 72,1218 /**1219 * Command type used for all clock manager commands.1220 */1221 DMUB_CMD__CLK_MGR = 73,1222 /**1223 * Command type used for all panel control commands.1224 */1225 DMUB_CMD__PANEL_CNTL = 74,1226 1227 /**1228 * Command type used for all CAB commands.1229 */1230 DMUB_CMD__CAB_FOR_SS = 75,1231 1232 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,1233 1234 /**1235 * Command type used for interfacing with DPIA.1236 */1237 DMUB_CMD__DPIA = 77,1238 /**1239 * Command type used for EDID CEA parsing1240 */1241 DMUB_CMD__EDID_CEA = 79,1242 /**1243 * Command type used for getting usbc cable ID1244 */1245 DMUB_CMD_GET_USBC_CABLE_ID = 81,1246 /**1247 * Command type used to query HPD state.1248 */1249 DMUB_CMD__QUERY_HPD_STATE = 82,1250 /**1251 * Command type used for all VBIOS interface commands.1252 */1253 /**1254 * Command type used for all REPLAY commands.1255 */1256 DMUB_CMD__REPLAY = 83,1257 1258 /**1259 * Command type used for all SECURE_DISPLAY commands.1260 */1261 DMUB_CMD__SECURE_DISPLAY = 85,1262 1263 /**1264 * Command type used to set DPIA HPD interrupt state1265 */1266 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,1267 1268 /**1269 * Command type used for all PSP commands.1270 */1271 DMUB_CMD__PSP = 88,1272 1273 DMUB_CMD__VBIOS = 128,1274};1275 1276/**1277 * enum dmub_out_cmd_type - DMUB outbox commands.1278 */1279enum dmub_out_cmd_type {1280 /**1281 * Invalid outbox command, ignored.1282 */1283 DMUB_OUT_CMD__NULL = 0,1284 /**1285 * Command type used for DP AUX Reply data notification1286 */1287 DMUB_OUT_CMD__DP_AUX_REPLY = 1,1288 /**1289 * Command type used for DP HPD event notification1290 */1291 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,1292 /**1293 * Command type used for SET_CONFIG Reply notification1294 */1295 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,1296 /**1297 * Command type used for USB4 DPIA notification1298 */1299 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,1300 /**1301 * Command type used for HPD redetect notification1302 */1303 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,1304};1305 1306/* DMUB_CMD__DPIA command sub-types. */1307enum dmub_cmd_dpia_type {1308 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,1309 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,1310 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,1311 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,1312};1313 1314/* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */1315enum dmub_cmd_dpia_notification_type {1316 DPIA_NOTIFY__BW_ALLOCATION = 0,1317};1318 1319#pragma pack(push, 1)1320 1321/**1322 * struct dmub_cmd_header - Common command header fields.1323 */1324struct dmub_cmd_header {1325 unsigned int type : 8; /**< command type */1326 unsigned int sub_type : 8; /**< command sub type */1327 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */1328 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */1329 unsigned int reserved0 : 6; /**< reserved bits */1330 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */1331 unsigned int reserved1 : 2; /**< reserved bits */1332};1333 1334/*1335 * struct dmub_cmd_read_modify_write_sequence - Read modify write1336 *1337 * 60 payload bytes can hold up to 5 sets of read modify writes,1338 * each take 3 dwords.1339 *1340 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)1341 *1342 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case1343 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write1344 */1345struct dmub_cmd_read_modify_write_sequence {1346 uint32_t addr; /**< register address */1347 uint32_t modify_mask; /**< modify mask */1348 uint32_t modify_value; /**< modify value */1349};1350 1351/**1352 * Maximum number of ops in read modify write sequence.1353 */1354#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 51355 1356/**1357 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.1358 */1359struct dmub_rb_cmd_read_modify_write {1360 struct dmub_cmd_header header; /**< command header */1361 /**1362 * Read modify write sequence.1363 */1364 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];1365};1366 1367/*1368 * Update a register with specified masks and values sequeunce1369 *1370 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword1371 *1372 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)1373 *1374 *1375 * USE CASE:1376 * 1. auto-increment register where additional read would update pointer and produce wrong result1377 * 2. toggle a bit without read in the middle1378 */1379 1380struct dmub_cmd_reg_field_update_sequence {1381 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */1382 uint32_t modify_value; /**< value to update with */1383};1384 1385/**1386 * Maximum number of ops in field update sequence.1387 */1388#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 71389 1390/**1391 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.1392 */1393struct dmub_rb_cmd_reg_field_update_sequence {1394 struct dmub_cmd_header header; /**< command header */1395 uint32_t addr; /**< register address */1396 /**1397 * Field update sequence.1398 */1399 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];1400};1401 1402 1403/**1404 * Maximum number of burst write values.1405 */1406#define DMUB_BURST_WRITE_VALUES__MAX 141407 1408/*1409 * struct dmub_rb_cmd_burst_write - Burst write1410 *1411 * support use case such as writing out LUTs.1412 *1413 * 60 payload bytes can hold up to 14 values to write to given address1414 *1415 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)1416 */1417struct dmub_rb_cmd_burst_write {1418 struct dmub_cmd_header header; /**< command header */1419 uint32_t addr; /**< register start address */1420 /**1421 * Burst write register values.1422 */1423 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];1424};1425 1426/**1427 * struct dmub_rb_cmd_common - Common command header1428 */1429struct dmub_rb_cmd_common {1430 struct dmub_cmd_header header; /**< command header */1431 /**1432 * Padding to RB_CMD_SIZE1433 */1434 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];1435};1436 1437/**1438 * struct dmub_cmd_reg_wait_data - Register wait data1439 */1440struct dmub_cmd_reg_wait_data {1441 uint32_t addr; /**< Register address */1442 uint32_t mask; /**< Mask for register bits */1443 uint32_t condition_field_value; /**< Value to wait for */1444 uint32_t time_out_us; /**< Time out for reg wait in microseconds */1445};1446 1447/**1448 * struct dmub_rb_cmd_reg_wait - Register wait command1449 */1450struct dmub_rb_cmd_reg_wait {1451 struct dmub_cmd_header header; /**< Command header */1452 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */1453};1454 1455/**1456 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround1457 *1458 * Reprograms surface parameters to avoid underflow.1459 */1460struct dmub_cmd_PLAT_54186_wa {1461 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */1462 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */1463 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */1464 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */1465 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */1466 struct {1467 uint32_t hubp_inst : 4; /**< HUBP instance */1468 uint32_t tmz_surface : 1; /**< TMZ enable or disable */1469 uint32_t immediate :1; /**< Immediate flip */1470 uint32_t vmid : 4; /**< VMID */1471 uint32_t grph_stereo : 1; /**< 1 if stereo */1472 uint32_t reserved : 21; /**< Reserved */1473 } flip_params; /**< Pageflip parameters */1474 uint32_t reserved[9]; /**< Reserved bits */1475};1476 1477/**1478 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command1479 */1480struct dmub_rb_cmd_PLAT_54186_wa {1481 struct dmub_cmd_header header; /**< Command header */1482 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */1483};1484 1485/**1486 * enum dmub_cmd_mall_type - MALL commands1487 */1488enum dmub_cmd_mall_type {1489 /**1490 * Allows display refresh from MALL.1491 */1492 DMUB_CMD__MALL_ACTION_ALLOW = 0,1493 /**1494 * Disallows display refresh from MALL.1495 */1496 DMUB_CMD__MALL_ACTION_DISALLOW = 1,1497 /**1498 * Cursor copy for MALL.1499 */1500 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,1501 /**1502 * Controls DF requests.1503 */1504 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,1505};1506 1507/**1508 * struct dmub_rb_cmd_mall - MALL command data.1509 */1510struct dmub_rb_cmd_mall {1511 struct dmub_cmd_header header; /**< Common command header */1512 union dmub_addr cursor_copy_src; /**< Cursor copy address */1513 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */1514 uint32_t tmr_delay; /**< Timer delay */1515 uint32_t tmr_scale; /**< Timer scale */1516 uint16_t cursor_width; /**< Cursor width in pixels */1517 uint16_t cursor_pitch; /**< Cursor pitch in pixels */1518 uint16_t cursor_height; /**< Cursor height in pixels */1519 uint8_t cursor_bpp; /**< Cursor bits per pixel */1520 uint8_t debug_bits; /**< Debug bits */1521 1522 uint8_t reserved1; /**< Reserved bits */1523 uint8_t reserved2; /**< Reserved bits */1524};1525 1526/**1527 * enum dmub_cmd_cab_type - CAB command data.1528 */1529enum dmub_cmd_cab_type {1530 /**1531 * No idle optimizations (i.e. no CAB)1532 */1533 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,1534 /**1535 * No DCN requests for memory1536 */1537 DMUB_CMD__CAB_NO_DCN_REQ = 1,1538 /**1539 * Fit surfaces in CAB (i.e. CAB enable)1540 */1541 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,1542 /**1543 * Do not fit surfaces in CAB (i.e. no CAB)1544 */1545 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,1546};1547 1548/**1549 * struct dmub_rb_cmd_cab - CAB command data.1550 */1551struct dmub_rb_cmd_cab_for_ss {1552 struct dmub_cmd_header header;1553 uint8_t cab_alloc_ways; /* total number of ways */1554 uint8_t debug_bits; /* debug bits */1555};1556 1557/**1558 * Enum for indicating which MCLK switch mode per pipe1559 */1560enum mclk_switch_mode {1561 NONE = 0,1562 FPO = 1,1563 SUBVP = 2,1564 VBLANK = 3,1565};1566 1567/* Per pipe struct which stores the MCLK switch mode1568 * data to be sent to DMUB.1569 * Named "v2" for now -- once FPO and SUBVP are fully merged1570 * the type name can be updated1571 */1572struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {1573 union {1574 struct {1575 uint32_t pix_clk_100hz;1576 uint16_t main_vblank_start;1577 uint16_t main_vblank_end;1578 uint16_t mall_region_lines;1579 uint16_t prefetch_lines;1580 uint16_t prefetch_to_mall_start_lines;1581 uint16_t processing_delay_lines;1582 uint16_t htotal; // required to calculate line time for multi-display cases1583 uint16_t vtotal;1584 uint8_t main_pipe_index;1585 uint8_t phantom_pipe_index;1586 /* Since the microschedule is calculated in terms of OTG lines,1587 * include any scaling factors to make sure when we get accurate1588 * conversion when programming MALL_START_LINE (which is in terms1589 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor1590 * is 1/2 (numerator = 1, denominator = 2).1591 */1592 uint8_t scale_factor_numerator;1593 uint8_t scale_factor_denominator;1594 uint8_t is_drr;1595 uint8_t main_split_pipe_index;1596 uint8_t phantom_split_pipe_index;1597 } subvp_data;1598 1599 struct {1600 uint32_t pix_clk_100hz;1601 uint16_t vblank_start;1602 uint16_t vblank_end;1603 uint16_t vstartup_start;1604 uint16_t vtotal;1605 uint16_t htotal;1606 uint8_t vblank_pipe_index;1607 uint8_t padding[1];1608 struct {1609 uint8_t drr_in_use;1610 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame1611 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK1612 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling1613 uint8_t use_ramping; // Use ramping or not1614 uint8_t drr_vblank_start_margin;1615 } drr_info; // DRR considered as part of SubVP + VBLANK case1616 } vblank_data;1617 } pipe_config;1618 1619 /* - subvp_data in the union (pipe_config) takes up 27 bytes.1620 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only1621 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).1622 */1623 uint8_t mode; // enum mclk_switch_mode1624};1625 1626/**1627 * Config data for Sub-VP and FPO1628 * Named "v2" for now -- once FPO and SUBVP are fully merged1629 * the type name can be updated1630 */1631struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {1632 uint16_t watermark_a_cache;1633 uint8_t vertical_int_margin_us;1634 uint8_t pstate_allow_width_us;1635 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];1636};1637 1638/**1639 * DMUB rb command definition for Sub-VP and FPO1640 * Named "v2" for now -- once FPO and SUBVP are fully merged1641 * the type name can be updated1642 */1643struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {1644 struct dmub_cmd_header header;1645 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;1646};1647 1648struct dmub_flip_addr_info {1649 uint32_t surf_addr_lo;1650 uint32_t surf_addr_c_lo;1651 uint32_t meta_addr_lo;1652 uint32_t meta_addr_c_lo;1653 uint16_t surf_addr_hi;1654 uint16_t surf_addr_c_hi;1655 uint16_t meta_addr_hi;1656 uint16_t meta_addr_c_hi;1657};1658 1659struct dmub_fams2_flip_info {1660 union {1661 struct {1662 uint8_t is_immediate: 1;1663 } bits;1664 uint8_t all;1665 } config;1666 uint8_t otg_inst;1667 uint8_t pipe_mask;1668 uint8_t pad;1669 struct dmub_flip_addr_info addr_info;1670};1671 1672struct dmub_rb_cmd_fams2_flip {1673 struct dmub_cmd_header header;1674 struct dmub_fams2_flip_info flip_info;1675};1676 1677struct dmub_optc_state_v2 {1678 uint32_t v_total_min;1679 uint32_t v_total_max;1680 uint32_t v_total_mid;1681 uint32_t v_total_mid_frame_num;1682 uint8_t program_manual_trigger;1683 uint8_t tg_inst;1684 uint8_t pad[2];1685};1686 1687struct dmub_optc_position {1688 uint32_t vpos;1689 uint32_t hpos;1690 uint32_t frame;1691};1692 1693struct dmub_rb_cmd_fams2_drr_update {1694 struct dmub_cmd_header header;1695 struct dmub_optc_state_v2 dmub_optc_state_req;1696};1697 1698/* HW and FW global configuration data for FAMS2 */1699/* FAMS2 types and structs */1700enum fams2_stream_type {1701 FAMS2_STREAM_TYPE_NONE = 0,1702 FAMS2_STREAM_TYPE_VBLANK = 1,1703 FAMS2_STREAM_TYPE_VACTIVE = 2,1704 FAMS2_STREAM_TYPE_DRR = 3,1705 FAMS2_STREAM_TYPE_SUBVP = 4,1706};1707 1708/* dynamic stream state */1709struct dmub_fams2_legacy_stream_dynamic_state {1710 uint8_t force_allow_at_vblank;1711 uint8_t pad[3];1712};1713 1714struct dmub_fams2_subvp_stream_dynamic_state {1715 uint16_t viewport_start_hubp_vline;1716 uint16_t viewport_height_hubp_vlines;1717 uint16_t viewport_start_c_hubp_vline;1718 uint16_t viewport_height_c_hubp_vlines;1719 uint16_t phantom_viewport_height_hubp_vlines;1720 uint16_t phantom_viewport_height_c_hubp_vlines;1721 uint16_t microschedule_start_otg_vline;1722 uint16_t mall_start_otg_vline;1723 uint16_t mall_start_hubp_vline;1724 uint16_t mall_start_c_hubp_vline;1725 uint8_t force_allow_at_vblank_only;1726 uint8_t pad[3];1727};1728 1729struct dmub_fams2_drr_stream_dynamic_state {1730 uint16_t stretched_vtotal;1731 uint8_t use_cur_vtotal;1732 uint8_t pad;1733};1734 1735struct dmub_fams2_stream_dynamic_state {1736 uint64_t ref_tick;1737 uint32_t cur_vtotal;1738 uint16_t adjusted_allow_end_otg_vline;1739 uint8_t pad[2];1740 struct dmub_optc_position ref_otg_pos;1741 struct dmub_optc_position target_otg_pos;1742 union {1743 struct dmub_fams2_legacy_stream_dynamic_state legacy;1744 struct dmub_fams2_subvp_stream_dynamic_state subvp;1745 struct dmub_fams2_drr_stream_dynamic_state drr;1746 } sub_state;1747};1748 1749/* static stream state */1750struct dmub_fams2_legacy_stream_static_state {1751 uint8_t vactive_det_fill_delay_otg_vlines;1752 uint8_t programming_delay_otg_vlines;1753};1754 1755struct dmub_fams2_subvp_stream_static_state {1756 uint16_t vratio_numerator;1757 uint16_t vratio_denominator;1758 uint16_t phantom_vtotal;1759 uint16_t phantom_vactive;1760 union {1761 struct {1762 uint8_t is_multi_planar : 1;1763 uint8_t is_yuv420 : 1;1764 } bits;1765 uint8_t all;1766 } config;1767 uint8_t programming_delay_otg_vlines;1768 uint8_t prefetch_to_mall_otg_vlines;1769 uint8_t phantom_otg_inst;1770 uint8_t phantom_pipe_mask;1771 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)1772};1773 1774struct dmub_fams2_drr_stream_static_state {1775 uint16_t nom_stretched_vtotal;1776 uint8_t programming_delay_otg_vlines;1777 uint8_t only_stretch_if_required;1778 uint8_t pad[2];1779};1780 1781struct dmub_fams2_stream_static_state {1782 enum fams2_stream_type type;1783 uint32_t otg_vline_time_ns;1784 uint32_t otg_vline_time_ticks;1785 uint16_t htotal;1786 uint16_t vtotal; // nominal vtotal1787 uint16_t vblank_start;1788 uint16_t vblank_end;1789 uint16_t max_vtotal;1790 uint16_t allow_start_otg_vline;1791 uint16_t allow_end_otg_vline;1792 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed1793 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start1794 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution1795 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing1796 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline1797 union {1798 struct {1799 uint8_t is_drr: 1; // stream is DRR enabled1800 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal1801 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank1802 } bits;1803 uint8_t all;1804 } config;1805 uint8_t otg_inst;1806 uint8_t pipe_mask; // pipe mask for the whole config1807 uint8_t num_planes;1808 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)1809 uint8_t pad[DMUB_MAX_PLANES % 4];1810 union {1811 struct dmub_fams2_legacy_stream_static_state legacy;1812 struct dmub_fams2_subvp_stream_static_state subvp;1813 struct dmub_fams2_drr_stream_static_state drr;1814 } sub_state;1815};1816 1817/**1818 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive1819 * p-state request to allow latency1820 */1821enum dmub_fams2_allow_delay_check_mode {1822 /* No check for request to allow delay */1823 FAMS2_ALLOW_DELAY_CHECK_NONE = 0,1824 /* Check for request to allow delay */1825 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,1826 /* Check for prepare to allow delay */1827 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,1828};1829 1830union dmub_fams2_global_feature_config {1831 struct {1832 uint32_t enable: 1;1833 uint32_t enable_ppt_check: 1;1834 uint32_t enable_stall_recovery: 1;1835 uint32_t enable_debug: 1;1836 uint32_t enable_offload_flip: 1;1837 uint32_t enable_visual_confirm: 1;1838 uint32_t allow_delay_check_mode: 2;1839 uint32_t reserved: 24;1840 } bits;1841 uint32_t all;1842};1843 1844struct dmub_cmd_fams2_global_config {1845 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin1846 uint32_t lock_wait_time_us; // time to forecast acquisition of lock1847 uint32_t num_streams;1848 union dmub_fams2_global_feature_config features;1849 uint32_t recovery_timeout_us;1850 uint32_t hwfq_flip_programming_delay_us;1851};1852 1853union dmub_cmd_fams2_config {1854 struct dmub_cmd_fams2_global_config global;1855 struct dmub_fams2_stream_static_state stream;1856};1857 1858/**1859 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)1860 */1861struct dmub_rb_cmd_fams2 {1862 struct dmub_cmd_header header;1863 union dmub_cmd_fams2_config config;1864};1865 1866/**1867 * enum dmub_cmd_idle_opt_type - Idle optimization command type.1868 */1869enum dmub_cmd_idle_opt_type {1870 /**1871 * DCN hardware restore.1872 */1873 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,1874 1875 /**1876 * DCN hardware save.1877 */1878 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,1879 1880 /**1881 * DCN hardware notify idle.1882 */1883 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,1884 1885 /**1886 * DCN hardware notify power state.1887 */1888 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,1889};1890 1891/**1892 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.1893 */1894struct dmub_rb_cmd_idle_opt_dcn_restore {1895 struct dmub_cmd_header header; /**< header */1896};1897 1898/**1899 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.1900 */1901struct dmub_dcn_notify_idle_cntl_data {1902 uint8_t driver_idle;1903 uint8_t skip_otg_disable;1904 uint8_t reserved[58];1905};1906 1907/**1908 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.1909 */1910struct dmub_rb_cmd_idle_opt_dcn_notify_idle {1911 struct dmub_cmd_header header; /**< header */1912 struct dmub_dcn_notify_idle_cntl_data cntl_data;1913};1914 1915/**1916 * enum dmub_idle_opt_dc_power_state - DC power states.1917 */1918enum dmub_idle_opt_dc_power_state {1919 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,1920 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,1921 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,1922 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,1923 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,1924};1925 1926/**1927 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.1928 */1929struct dmub_idle_opt_set_dc_power_state_data {1930 uint8_t power_state; /**< power state */1931 uint8_t pad[3]; /**< padding */1932};1933 1934/**1935 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.1936 */1937struct dmub_rb_cmd_idle_opt_set_dc_power_state {1938 struct dmub_cmd_header header; /**< header */1939 struct dmub_idle_opt_set_dc_power_state_data data;1940};1941 1942/**1943 * struct dmub_clocks - Clock update notification.1944 */1945struct dmub_clocks {1946 uint32_t dispclk_khz; /**< dispclk kHz */1947 uint32_t dppclk_khz; /**< dppclk kHz */1948 uint32_t dcfclk_khz; /**< dcfclk kHz */1949 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */1950};1951 1952/**1953 * enum dmub_cmd_clk_mgr_type - Clock manager commands.1954 */1955enum dmub_cmd_clk_mgr_type {1956 /**1957 * Notify DMCUB of clock update.1958 */1959 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,1960};1961 1962/**1963 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.1964 */1965struct dmub_rb_cmd_clk_mgr_notify_clocks {1966 struct dmub_cmd_header header; /**< header */1967 struct dmub_clocks clocks; /**< clock data */1968};1969 1970/**1971 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.1972 */1973struct dmub_cmd_digx_encoder_control_data {1974 union dig_encoder_control_parameters_v1_5 dig; /**< payload */1975};1976 1977/**1978 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.1979 */1980struct dmub_rb_cmd_digx_encoder_control {1981 struct dmub_cmd_header header; /**< header */1982 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */1983};1984 1985/**1986 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.1987 */1988struct dmub_cmd_set_pixel_clock_data {1989 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */1990};1991 1992/**1993 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.1994 */1995struct dmub_rb_cmd_set_pixel_clock {1996 struct dmub_cmd_header header; /**< header */1997 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */1998};1999 2000/**2001 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.2002 */2003struct dmub_cmd_enable_disp_power_gating_data {2004 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */2005};2006 2007/**2008 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.2009 */2010struct dmub_rb_cmd_enable_disp_power_gating {2011 struct dmub_cmd_header header; /**< header */2012 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */2013};2014 2015/**2016 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.2017 */2018struct dmub_dig_transmitter_control_data_v1_7 {2019 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */2020 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */2021 union {2022 uint8_t digmode; /**< enum atom_encode_mode_def */2023 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */2024 } mode_laneset;2025 uint8_t lanenum; /**< Number of lanes */2026 union {2027 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */2028 } symclk_units;2029 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */2030 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */2031 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */2032 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */2033 uint8_t reserved1; /**< For future use */2034 uint8_t reserved2[3]; /**< For future use */2035 uint32_t reserved3[11]; /**< For future use */2036};2037 2038/**2039 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.2040 */2041union dmub_cmd_dig1_transmitter_control_data {2042 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */2043 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */2044};2045 2046/**2047 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.2048 */2049struct dmub_rb_cmd_dig1_transmitter_control {2050 struct dmub_cmd_header header; /**< header */2051 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */2052};2053 2054/**2055 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control2056 */2057struct dmub_rb_cmd_domain_control_data {2058 uint8_t inst : 6; /**< DOMAIN instance to control */2059 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */2060 uint8_t reserved[3]; /**< Reserved for future use */2061};2062 2063/**2064 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating2065 */2066struct dmub_rb_cmd_domain_control {2067 struct dmub_cmd_header header; /**< header */2068 struct dmub_rb_cmd_domain_control_data data; /**< payload */2069};2070 2071/**2072 * DPIA tunnel command parameters.2073 */2074struct dmub_cmd_dig_dpia_control_data {2075 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */2076 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */2077 union {2078 uint8_t digmode; /** enum atom_encode_mode_def */2079 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */2080 } mode_laneset;2081 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */2082 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */2083 uint8_t hpdsel; /** =0: HPD is not assigned */2084 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */2085 uint8_t dpia_id; /** Index of DPIA */2086 uint8_t fec_rdy : 1;2087 uint8_t reserved : 7;2088 uint32_t reserved1;2089};2090 2091/**2092 * DMUB command for DPIA tunnel control.2093 */2094struct dmub_rb_cmd_dig1_dpia_control {2095 struct dmub_cmd_header header;2096 struct dmub_cmd_dig_dpia_control_data dpia_control;2097};2098 2099/**2100 * SET_CONFIG Command Payload2101 */2102struct set_config_cmd_payload {2103 uint8_t msg_type; /* set config message type */2104 uint8_t msg_data; /* set config message data */2105};2106 2107/**2108 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.2109 */2110struct dmub_cmd_set_config_control_data {2111 struct set_config_cmd_payload cmd_pkt;2112 uint8_t instance; /* DPIA instance */2113 uint8_t immed_status; /* Immediate status returned in case of error */2114};2115 2116/**2117 * DMUB command structure for SET_CONFIG command.2118 */2119struct dmub_rb_cmd_set_config_access {2120 struct dmub_cmd_header header; /* header */2121 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */2122};2123 2124/**2125 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.2126 */2127struct dmub_cmd_mst_alloc_slots_control_data {2128 uint8_t mst_alloc_slots; /* mst slots to be allotted */2129 uint8_t instance; /* DPIA instance */2130 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */2131 uint8_t mst_slots_in_use; /* returns slots in use for error cases */2132};2133 2134/**2135 * DMUB command structure for SET_ command.2136 */2137struct dmub_rb_cmd_set_mst_alloc_slots {2138 struct dmub_cmd_header header; /* header */2139 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */2140};2141 2142/**2143 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.2144 */2145struct dmub_cmd_tps_notification_data {2146 uint8_t instance; /* DPIA instance */2147 uint8_t tps; /* requested training pattern */2148 uint8_t reserved1;2149 uint8_t reserved2;2150};2151 2152/**2153 * DMUB command structure for SET_TPS_NOTIFICATION command.2154 */2155struct dmub_rb_cmd_set_tps_notification {2156 struct dmub_cmd_header header; /* header */2157 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */2158};2159 2160/**2161 * DMUB command structure for DPIA HPD int enable control.2162 */2163struct dmub_rb_cmd_dpia_hpd_int_enable {2164 struct dmub_cmd_header header; /* header */2165 uint32_t enable; /* dpia hpd interrupt enable */2166};2167 2168/**2169 * struct dmub_rb_cmd_dpphy_init - DPPHY init.2170 */2171struct dmub_rb_cmd_dpphy_init {2172 struct dmub_cmd_header header; /**< header */2173 uint8_t reserved[60]; /**< reserved bits */2174};2175 2176/**2177 * enum dp_aux_request_action - DP AUX request command listing.2178 *2179 * 4 AUX request command bits are shifted to high nibble.2180 */2181enum dp_aux_request_action {2182 /** I2C-over-AUX write request */2183 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,2184 /** I2C-over-AUX read request */2185 DP_AUX_REQ_ACTION_I2C_READ = 0x10,2186 /** I2C-over-AUX write status request */2187 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,2188 /** I2C-over-AUX write request with MOT=1 */2189 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,2190 /** I2C-over-AUX read request with MOT=1 */2191 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,2192 /** I2C-over-AUX write status request with MOT=1 */2193 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,2194 /** Native AUX write request */2195 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,2196 /** Native AUX read request */2197 DP_AUX_REQ_ACTION_DPCD_READ = 0x902198};2199 2200/**2201 * enum aux_return_code_type - DP AUX process return code listing.2202 */2203enum aux_return_code_type {2204 /** AUX process succeeded */2205 AUX_RET_SUCCESS = 0,2206 /** AUX process failed with unknown reason */2207 AUX_RET_ERROR_UNKNOWN,2208 /** AUX process completed with invalid reply */2209 AUX_RET_ERROR_INVALID_REPLY,2210 /** AUX process timed out */2211 AUX_RET_ERROR_TIMEOUT,2212 /** HPD was low during AUX process */2213 AUX_RET_ERROR_HPD_DISCON,2214 /** Failed to acquire AUX engine */2215 AUX_RET_ERROR_ENGINE_ACQUIRE,2216 /** AUX request not supported */2217 AUX_RET_ERROR_INVALID_OPERATION,2218 /** AUX process not available */2219 AUX_RET_ERROR_PROTOCOL_ERROR,2220};2221 2222/**2223 * enum aux_channel_type - DP AUX channel type listing.2224 */2225enum aux_channel_type {2226 /** AUX thru Legacy DP AUX */2227 AUX_CHANNEL_LEGACY_DDC,2228 /** AUX thru DPIA DP tunneling */2229 AUX_CHANNEL_DPIA2230};2231 2232/**2233 * struct aux_transaction_parameters - DP AUX request transaction data2234 */2235struct aux_transaction_parameters {2236 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */2237 uint8_t action; /**< enum dp_aux_request_action */2238 uint8_t length; /**< DP AUX request data length */2239 uint8_t reserved; /**< For future use */2240 uint32_t address; /**< DP AUX address */2241 uint8_t data[16]; /**< DP AUX write data */2242};2243 2244/**2245 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.2246 */2247struct dmub_cmd_dp_aux_control_data {2248 uint8_t instance; /**< AUX instance or DPIA instance */2249 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */2250 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */2251 uint8_t reserved0; /**< For future use */2252 uint16_t timeout; /**< timeout time in us */2253 uint16_t reserved1; /**< For future use */2254 enum aux_channel_type type; /**< enum aux_channel_type */2255 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */2256};2257 2258/**2259 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.2260 */2261struct dmub_rb_cmd_dp_aux_access {2262 /**2263 * Command header.2264 */2265 struct dmub_cmd_header header;2266 /**2267 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.2268 */2269 struct dmub_cmd_dp_aux_control_data aux_control;2270};2271 2272/**2273 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.2274 */2275struct dmub_rb_cmd_outbox1_enable {2276 /**2277 * Command header.2278 */2279 struct dmub_cmd_header header;2280 /**2281 * enable: 0x0 -> disable outbox1 notification (default value)2282 * 0x1 -> enable outbox1 notification2283 */2284 uint32_t enable;2285};2286 2287/* DP AUX Reply command - OutBox Cmd */2288/**2289 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.2290 */2291struct aux_reply_data {2292 /**2293 * Aux cmd2294 */2295 uint8_t command;2296 /**2297 * Aux reply data length (max: 16 bytes)2298 */2299 uint8_t length;2300 /**2301 * Alignment only2302 */2303 uint8_t pad[2];2304 /**2305 * Aux reply data2306 */2307 uint8_t data[16];2308};2309 2310/**2311 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.2312 */2313struct aux_reply_control_data {2314 /**2315 * Reserved for future use2316 */2317 uint32_t handle;2318 /**2319 * Aux Instance2320 */2321 uint8_t instance;2322 /**2323 * Aux transaction result: definition in enum aux_return_code_type2324 */2325 uint8_t result;2326 /**2327 * Alignment only2328 */2329 uint16_t pad;2330};2331 2332/**2333 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.2334 */2335struct dmub_rb_cmd_dp_aux_reply {2336 /**2337 * Command header.2338 */2339 struct dmub_cmd_header header;2340 /**2341 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.2342 */2343 struct aux_reply_control_data control;2344 /**2345 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.2346 */2347 struct aux_reply_data reply_data;2348};2349 2350/* DP HPD Notify command - OutBox Cmd */2351/**2352 * DP HPD Type2353 */2354enum dp_hpd_type {2355 /**2356 * Normal DP HPD2357 */2358 DP_HPD = 0,2359 /**2360 * DP HPD short pulse2361 */2362 DP_IRQ2363};2364 2365/**2366 * DP HPD Status2367 */2368enum dp_hpd_status {2369 /**2370 * DP_HPD status low2371 */2372 DP_HPD_UNPLUG = 0,2373 /**2374 * DP_HPD status high2375 */2376 DP_HPD_PLUG2377};2378 2379/**2380 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.2381 */2382struct dp_hpd_data {2383 /**2384 * DP HPD instance2385 */2386 uint8_t instance;2387 /**2388 * HPD type2389 */2390 uint8_t hpd_type;2391 /**2392 * HPD status: only for type: DP_HPD to indicate status2393 */2394 uint8_t hpd_status;2395 /**2396 * Alignment only2397 */2398 uint8_t pad;2399};2400 2401/**2402 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.2403 */2404struct dmub_rb_cmd_dp_hpd_notify {2405 /**2406 * Command header.2407 */2408 struct dmub_cmd_header header;2409 /**2410 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.2411 */2412 struct dp_hpd_data hpd_data;2413};2414 2415/**2416 * Definition of a SET_CONFIG reply from DPOA.2417 */2418enum set_config_status {2419 SET_CONFIG_PENDING = 0,2420 SET_CONFIG_ACK_RECEIVED,2421 SET_CONFIG_RX_TIMEOUT,2422 SET_CONFIG_UNKNOWN_ERROR,2423};2424 2425/**2426 * Definition of a set_config reply2427 */2428struct set_config_reply_control_data {2429 uint8_t instance; /* DPIA Instance */2430 uint8_t status; /* Set Config reply */2431 uint16_t pad; /* Alignment */2432};2433 2434/**2435 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.2436 */2437struct dmub_rb_cmd_dp_set_config_reply {2438 struct dmub_cmd_header header;2439 struct set_config_reply_control_data set_config_reply_control;2440};2441 2442/**2443 * Definition of a DPIA notification header2444 */2445struct dpia_notification_header {2446 uint8_t instance; /**< DPIA Instance */2447 uint8_t reserved[3];2448 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */2449};2450 2451/**2452 * Definition of the common data struct of DPIA notification2453 */2454struct dpia_notification_common {2455 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)2456 - sizeof(struct dpia_notification_header)];2457};2458 2459/**2460 * Definition of a DPIA notification data2461 */2462struct dpia_bw_allocation_notify_data {2463 union {2464 struct {2465 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */2466 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */2467 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */2468 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */2469 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */2470 uint16_t reserved: 11; /**< Reserved */2471 } bits;2472 2473 uint16_t flags;2474 };2475 2476 uint8_t cm_id; /**< CM ID */2477 uint8_t group_id; /**< Group ID */2478 uint8_t granularity; /**< BW Allocation Granularity */2479 uint8_t estimated_bw; /**< Estimated_BW */2480 uint8_t allocated_bw; /**< Allocated_BW */2481 uint8_t reserved;2482};2483 2484/**2485 * union dpia_notify_data_type - DPIA Notification in Outbox command2486 */2487union dpia_notification_data {2488 /**2489 * DPIA Notification for common data struct2490 */2491 struct dpia_notification_common common_data;2492 2493 /**2494 * DPIA Notification for DP BW Allocation support2495 */2496 struct dpia_bw_allocation_notify_data dpia_bw_alloc;2497};2498 2499/**2500 * Definition of a DPIA notification payload2501 */2502struct dpia_notification_payload {2503 struct dpia_notification_header header;2504 union dpia_notification_data data; /**< DPIA notification payload data */2505};2506 2507/**2508 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.2509 */2510struct dmub_rb_cmd_dpia_notification {2511 struct dmub_cmd_header header; /**< DPIA notification header */2512 struct dpia_notification_payload payload; /**< DPIA notification payload */2513};2514 2515/**2516 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.2517 */2518struct dmub_cmd_hpd_state_query_data {2519 uint8_t instance; /**< HPD instance or DPIA instance */2520 uint8_t result; /**< For returning HPD state */2521 uint16_t pad; /** < Alignment */2522 enum aux_channel_type ch_type; /**< enum aux_channel_type */2523 enum aux_return_code_type status; /**< for returning the status of command */2524};2525 2526/**2527 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.2528 */2529struct dmub_rb_cmd_query_hpd_state {2530 /**2531 * Command header.2532 */2533 struct dmub_cmd_header header;2534 /**2535 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.2536 */2537 struct dmub_cmd_hpd_state_query_data data;2538};2539 2540/**2541 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.2542 */2543struct dmub_rb_cmd_hpd_sense_notify_data {2544 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */2545 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */2546};2547 2548/**2549 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.2550 */2551struct dmub_rb_cmd_hpd_sense_notify {2552 struct dmub_cmd_header header; /**< header */2553 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */2554};2555 2556/*2557 * Command IDs should be treated as stable ABI.2558 * Do not reuse or modify IDs.2559 */2560 2561/**2562 * PSR command sub-types.2563 */2564enum dmub_cmd_psr_type {2565 /**2566 * Set PSR version support.2567 */2568 DMUB_CMD__PSR_SET_VERSION = 0,2569 /**2570 * Copy driver-calculated parameters to PSR state.2571 */2572 DMUB_CMD__PSR_COPY_SETTINGS = 1,2573 /**2574 * Enable PSR.2575 */2576 DMUB_CMD__PSR_ENABLE = 2,2577 2578 /**2579 * Disable PSR.2580 */2581 DMUB_CMD__PSR_DISABLE = 3,2582 2583 /**2584 * Set PSR level.2585 * PSR level is a 16-bit value dicated by driver that2586 * will enable/disable different functionality.2587 */2588 DMUB_CMD__PSR_SET_LEVEL = 4,2589 2590 /**2591 * Forces PSR enabled until an explicit PSR disable call.2592 */2593 DMUB_CMD__PSR_FORCE_STATIC = 5,2594 /**2595 * Set vtotal in psr active for FreeSync PSR.2596 */2597 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,2598 /**2599 * Set PSR power option2600 */2601 DMUB_CMD__SET_PSR_POWER_OPT = 7,2602};2603 2604/**2605 * Different PSR residency modes.2606 * Different modes change the definition of PSR residency.2607 */2608enum psr_residency_mode {2609 PSR_RESIDENCY_MODE_PHY = 0,2610 PSR_RESIDENCY_MODE_ALPM,2611 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,2612 /* Do not add below. */2613 PSR_RESIDENCY_MODE_LAST_ELEMENT,2614};2615 2616enum dmub_cmd_fams_type {2617 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,2618 DMUB_CMD__FAMS_DRR_UPDATE = 1,2619 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd2620 /**2621 * For SubVP set manual trigger in FW because it2622 * triggers DRR_UPDATE_PENDING which SubVP relies2623 * on (for any SubVP cases that use a DRR display)2624 */2625 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,2626 DMUB_CMD__FAMS2_CONFIG = 4,2627 DMUB_CMD__FAMS2_DRR_UPDATE = 5,2628 DMUB_CMD__FAMS2_FLIP = 6,2629};2630 2631/**2632 * PSR versions.2633 */2634enum psr_version {2635 /**2636 * PSR version 1.2637 */2638 PSR_VERSION_1 = 0,2639 /**2640 * Freesync PSR SU.2641 */2642 PSR_VERSION_SU_1 = 1,2643 /**2644 * PSR not supported.2645 */2646 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide2647};2648 2649/**2650 * PHY Link rate for DP.2651 */2652enum phy_link_rate {2653 /**2654 * not supported.2655 */2656 PHY_RATE_UNKNOWN = 0,2657 /**2658 * Rate_1 (RBR) - 1.62 Gbps/Lane2659 */2660 PHY_RATE_162 = 1,2661 /**2662 * Rate_2 - 2.16 Gbps/Lane2663 */2664 PHY_RATE_216 = 2,2665 /**2666 * Rate_3 - 2.43 Gbps/Lane2667 */2668 PHY_RATE_243 = 3,2669 /**2670 * Rate_4 (HBR) - 2.70 Gbps/Lane2671 */2672 PHY_RATE_270 = 4,2673 /**2674 * Rate_5 (RBR2)- 3.24 Gbps/Lane2675 */2676 PHY_RATE_324 = 5,2677 /**2678 * Rate_6 - 4.32 Gbps/Lane2679 */2680 PHY_RATE_432 = 6,2681 /**2682 * Rate_7 (HBR2)- 5.40 Gbps/Lane2683 */2684 PHY_RATE_540 = 7,2685 /**2686 * Rate_8 (HBR3)- 8.10 Gbps/Lane2687 */2688 PHY_RATE_810 = 8,2689 /**2690 * UHBR10 - 10.0 Gbps/Lane2691 */2692 PHY_RATE_1000 = 9,2693 /**2694 * UHBR13.5 - 13.5 Gbps/Lane2695 */2696 PHY_RATE_1350 = 10,2697 /**2698 * UHBR10 - 20.0 Gbps/Lane2699 */2700 PHY_RATE_2000 = 11,2701 2702 PHY_RATE_675 = 12,2703 /**2704 * Rate 12 - 6.75 Gbps/Lane2705 */2706};2707 2708/**2709 * enum dmub_phy_fsm_state - PHY FSM states.2710 * PHY FSM state to transit to during PSR enable/disable.2711 */2712enum dmub_phy_fsm_state {2713 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,2714 DMUB_PHY_FSM_RESET,2715 DMUB_PHY_FSM_RESET_RELEASED,2716 DMUB_PHY_FSM_SRAM_LOAD_DONE,2717 DMUB_PHY_FSM_INITIALIZED,2718 DMUB_PHY_FSM_CALIBRATED,2719 DMUB_PHY_FSM_CALIBRATED_LP,2720 DMUB_PHY_FSM_CALIBRATED_PG,2721 DMUB_PHY_FSM_POWER_DOWN,2722 DMUB_PHY_FSM_PLL_EN,2723 DMUB_PHY_FSM_TX_EN,2724 DMUB_PHY_FSM_TX_EN_TEST_MODE,2725 DMUB_PHY_FSM_FAST_LP,2726 DMUB_PHY_FSM_P2_PLL_OFF_CPM,2727 DMUB_PHY_FSM_P2_PLL_OFF_PG,2728 DMUB_PHY_FSM_P2_PLL_OFF,2729 DMUB_PHY_FSM_P2_PLL_ON,2730};2731 2732/**2733 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.2734 */2735struct dmub_cmd_psr_copy_settings_data {2736 /**2737 * Flags that can be set by driver to change some PSR behaviour.2738 */2739 union dmub_psr_debug_flags debug;2740 /**2741 * 16-bit value dicated by driver that will enable/disable different functionality.2742 */2743 uint16_t psr_level;2744 /**2745 * DPP HW instance.2746 */2747 uint8_t dpp_inst;2748 /**2749 * MPCC HW instance.2750 * Not used in dmub fw,2751 * dmub fw will get active opp by reading odm registers.2752 */2753 uint8_t mpcc_inst;2754 /**2755 * OPP HW instance.2756 * Not used in dmub fw,2757 * dmub fw will get active opp by reading odm registers.2758 */2759 uint8_t opp_inst;2760 /**2761 * OTG HW instance.2762 */2763 uint8_t otg_inst;2764 /**2765 * DIG FE HW instance.2766 */2767 uint8_t digfe_inst;2768 /**2769 * DIG BE HW instance.2770 */2771 uint8_t digbe_inst;2772 /**2773 * DP PHY HW instance.2774 */2775 uint8_t dpphy_inst;2776 /**2777 * AUX HW instance.2778 */2779 uint8_t aux_inst;2780 /**2781 * Determines if SMU optimzations are enabled/disabled.2782 */2783 uint8_t smu_optimizations_en;2784 /**2785 * Unused.2786 * TODO: Remove.2787 */2788 uint8_t frame_delay;2789 /**2790 * If RFB setup time is greater than the total VBLANK time,2791 * it is not possible for the sink to capture the video frame2792 * in the same frame the SDP is sent. In this case,2793 * the frame capture indication bit should be set and an extra2794 * static frame should be transmitted to the sink.2795 */2796 uint8_t frame_cap_ind;2797 /**2798 * Granularity of Y offset supported by sink.2799 */2800 uint8_t su_y_granularity;2801 /**2802 * Indicates whether sink should start capturing2803 * immediately following active scan line,2804 * or starting with the 2nd active scan line.2805 */2806 uint8_t line_capture_indication;2807 /**2808 * Multi-display optimizations are implemented on certain ASICs.2809 */2810 uint8_t multi_disp_optimizations_en;2811 /**2812 * The last possible line SDP may be transmitted without violating2813 * the RFB setup time or entering the active video frame.2814 */2815 uint16_t init_sdp_deadline;2816 /**2817 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities2818 */2819 uint8_t rate_control_caps ;2820 /*2821 * Force PSRSU always doing full frame update2822 */2823 uint8_t force_ffu_mode;2824 /**2825 * Length of each horizontal line in us.2826 */2827 uint32_t line_time_in_us;2828 /**2829 * FEC enable status in driver2830 */2831 uint8_t fec_enable_status;2832 /**2833 * FEC re-enable delay when PSR exit.2834 * unit is 100us, range form 0~255(0xFF).2835 */2836 uint8_t fec_enable_delay_in100us;2837 /**2838 * PSR control version.2839 */2840 uint8_t cmd_version;2841 /**2842 * Panel Instance.2843 * Panel instance to identify which psr_state to use2844 * Currently the support is only for 0 or 12845 */2846 uint8_t panel_inst;2847 /*2848 * DSC enable status in driver2849 */2850 uint8_t dsc_enable_status;2851 /*2852 * Use FSM state for PSR power up/down2853 */2854 uint8_t use_phy_fsm;2855 /**2856 * frame delay for frame re-lock2857 */2858 uint8_t relock_delay_frame_cnt;2859 /**2860 * esd recovery indicate.2861 */2862 uint8_t esd_recovery;2863 /**2864 * DSC Slice height.2865 */2866 uint16_t dsc_slice_height;2867 /**2868 * Some panels request main link off before xth vertical line2869 */2870 uint16_t poweroff_before_vertical_line;2871};2872 2873/**2874 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.2875 */2876struct dmub_rb_cmd_psr_copy_settings {2877 /**2878 * Command header.2879 */2880 struct dmub_cmd_header header;2881 /**2882 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.2883 */2884 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;2885};2886 2887/**2888 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.2889 */2890struct dmub_cmd_psr_set_level_data {2891 /**2892 * 16-bit value dicated by driver that will enable/disable different functionality.2893 */2894 uint16_t psr_level;2895 /**2896 * PSR control version.2897 */2898 uint8_t cmd_version;2899 /**2900 * Panel Instance.2901 * Panel instance to identify which psr_state to use2902 * Currently the support is only for 0 or 12903 */2904 uint8_t panel_inst;2905};2906 2907/**2908 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.2909 */2910struct dmub_rb_cmd_psr_set_level {2911 /**2912 * Command header.2913 */2914 struct dmub_cmd_header header;2915 /**2916 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.2917 */2918 struct dmub_cmd_psr_set_level_data psr_set_level_data;2919};2920 2921struct dmub_rb_cmd_psr_enable_data {2922 /**2923 * PSR control version.2924 */2925 uint8_t cmd_version;2926 /**2927 * Panel Instance.2928 * Panel instance to identify which psr_state to use2929 * Currently the support is only for 0 or 12930 */2931 uint8_t panel_inst;2932 /**2933 * Phy state to enter.2934 * Values to use are defined in dmub_phy_fsm_state2935 */2936 uint8_t phy_fsm_state;2937 /**2938 * Phy rate for DP - RBR/HBR/HBR2/HBR3.2939 * Set this using enum phy_link_rate.2940 * This does not support HDMI/DP2 for now.2941 */2942 uint8_t phy_rate;2943};2944 2945/**2946 * Definition of a DMUB_CMD__PSR_ENABLE command.2947 * PSR enable/disable is controlled using the sub_type.2948 */2949struct dmub_rb_cmd_psr_enable {2950 /**2951 * Command header.2952 */2953 struct dmub_cmd_header header;2954 2955 struct dmub_rb_cmd_psr_enable_data data;2956};2957 2958/**2959 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.2960 */2961struct dmub_cmd_psr_set_version_data {2962 /**2963 * PSR version that FW should implement.2964 */2965 enum psr_version version;2966 /**2967 * PSR control version.2968 */2969 uint8_t cmd_version;2970 /**2971 * Panel Instance.2972 * Panel instance to identify which psr_state to use2973 * Currently the support is only for 0 or 12974 */2975 uint8_t panel_inst;2976 /**2977 * Explicit padding to 4 byte boundary.2978 */2979 uint8_t pad[2];2980};2981 2982/**2983 * Definition of a DMUB_CMD__PSR_SET_VERSION command.2984 */2985struct dmub_rb_cmd_psr_set_version {2986 /**2987 * Command header.2988 */2989 struct dmub_cmd_header header;2990 /**2991 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.2992 */2993 struct dmub_cmd_psr_set_version_data psr_set_version_data;2994};2995 2996struct dmub_cmd_psr_force_static_data {2997 /**2998 * PSR control version.2999 */3000 uint8_t cmd_version;3001 /**3002 * Panel Instance.3003 * Panel instance to identify which psr_state to use3004 * Currently the support is only for 0 or 13005 */3006 uint8_t panel_inst;3007 /**3008 * Explicit padding to 4 byte boundary.3009 */3010 uint8_t pad[2];3011};3012 3013/**3014 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.3015 */3016struct dmub_rb_cmd_psr_force_static {3017 /**3018 * Command header.3019 */3020 struct dmub_cmd_header header;3021 /**3022 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.3023 */3024 struct dmub_cmd_psr_force_static_data psr_force_static_data;3025};3026 3027/**3028 * PSR SU debug flags.3029 */3030union dmub_psr_su_debug_flags {3031 /**3032 * PSR SU debug flags.3033 */3034 struct {3035 /**3036 * Update dirty rect in SW only.3037 */3038 uint8_t update_dirty_rect_only : 1;3039 /**3040 * Reset the cursor/plane state before processing the call.3041 */3042 uint8_t reset_state : 1;3043 } bitfields;3044 3045 /**3046 * Union for debug flags.3047 */3048 uint32_t u32All;3049};3050 3051/**3052 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.3053 * This triggers a selective update for PSR SU.3054 */3055struct dmub_cmd_update_dirty_rect_data {3056 /**3057 * Dirty rects from OS.3058 */3059 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];3060 /**3061 * PSR SU debug flags.3062 */3063 union dmub_psr_su_debug_flags debug_flags;3064 /**3065 * OTG HW instance.3066 */3067 uint8_t pipe_idx;3068 /**3069 * Number of dirty rects.3070 */3071 uint8_t dirty_rect_count;3072 /**3073 * PSR control version.3074 */3075 uint8_t cmd_version;3076 /**3077 * Panel Instance.3078 * Panel instance to identify which psr_state to use3079 * Currently the support is only for 0 or 13080 */3081 uint8_t panel_inst;3082};3083 3084/**3085 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.3086 */3087struct dmub_rb_cmd_update_dirty_rect {3088 /**3089 * Command header.3090 */3091 struct dmub_cmd_header header;3092 /**3093 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.3094 */3095 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;3096};3097 3098/**3099 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.3100 */3101union dmub_reg_cursor_control_cfg {3102 struct {3103 uint32_t cur_enable: 1;3104 uint32_t reser0: 3;3105 uint32_t cur_2x_magnify: 1;3106 uint32_t reser1: 3;3107 uint32_t mode: 3;3108 uint32_t reser2: 5;3109 uint32_t pitch: 2;3110 uint32_t reser3: 6;3111 uint32_t line_per_chunk: 5;3112 uint32_t reser4: 3;3113 } bits;3114 uint32_t raw;3115};3116struct dmub_cursor_position_cache_hubp {3117 union dmub_reg_cursor_control_cfg cur_ctl;3118 union dmub_reg_position_cfg {3119 struct {3120 uint32_t cur_x_pos: 16;3121 uint32_t cur_y_pos: 16;3122 } bits;3123 uint32_t raw;3124 } position;3125 union dmub_reg_hot_spot_cfg {3126 struct {3127 uint32_t hot_x: 16;3128 uint32_t hot_y: 16;3129 } bits;3130 uint32_t raw;3131 } hot_spot;3132 union dmub_reg_dst_offset_cfg {3133 struct {3134 uint32_t dst_x_offset: 13;3135 uint32_t reserved: 19;3136 } bits;3137 uint32_t raw;3138 } dst_offset;3139};3140 3141union dmub_reg_cur0_control_cfg {3142 struct {3143 uint32_t cur0_enable: 1;3144 uint32_t expansion_mode: 1;3145 uint32_t reser0: 1;3146 uint32_t cur0_rom_en: 1;3147 uint32_t mode: 3;3148 uint32_t reserved: 25;3149 } bits;3150 uint32_t raw;3151};3152struct dmub_cursor_position_cache_dpp {3153 union dmub_reg_cur0_control_cfg cur0_ctl;3154};3155struct dmub_cursor_position_cfg {3156 struct dmub_cursor_position_cache_hubp pHubp;3157 struct dmub_cursor_position_cache_dpp pDpp;3158 uint8_t pipe_idx;3159 /*3160 * Padding is required. To be 4 Bytes Aligned.3161 */3162 uint8_t padding[3];3163};3164 3165struct dmub_cursor_attribute_cache_hubp {3166 uint32_t SURFACE_ADDR_HIGH;3167 uint32_t SURFACE_ADDR;3168 union dmub_reg_cursor_control_cfg cur_ctl;3169 union dmub_reg_cursor_size_cfg {3170 struct {3171 uint32_t width: 16;3172 uint32_t height: 16;3173 } bits;3174 uint32_t raw;3175 } size;3176 union dmub_reg_cursor_settings_cfg {3177 struct {3178 uint32_t dst_y_offset: 8;3179 uint32_t chunk_hdl_adjust: 2;3180 uint32_t reserved: 22;3181 } bits;3182 uint32_t raw;3183 } settings;3184};3185struct dmub_cursor_attribute_cache_dpp {3186 union dmub_reg_cur0_control_cfg cur0_ctl;3187};3188struct dmub_cursor_attributes_cfg {3189 struct dmub_cursor_attribute_cache_hubp aHubp;3190 struct dmub_cursor_attribute_cache_dpp aDpp;3191};3192 3193struct dmub_cmd_update_cursor_payload0 {3194 /**3195 * Cursor dirty rects.3196 */3197 struct dmub_rect cursor_rect;3198 /**3199 * PSR SU debug flags.3200 */3201 union dmub_psr_su_debug_flags debug_flags;3202 /**3203 * Cursor enable/disable.3204 */3205 uint8_t enable;3206 /**3207 * OTG HW instance.3208 */3209 uint8_t pipe_idx;3210 /**3211 * PSR control version.3212 */3213 uint8_t cmd_version;3214 /**3215 * Panel Instance.3216 * Panel instance to identify which psr_state to use3217 * Currently the support is only for 0 or 13218 */3219 uint8_t panel_inst;3220 /**3221 * Cursor Position Register.3222 * Registers contains Hubp & Dpp modules3223 */3224 struct dmub_cursor_position_cfg position_cfg;3225};3226 3227struct dmub_cmd_update_cursor_payload1 {3228 struct dmub_cursor_attributes_cfg attribute_cfg;3229};3230 3231union dmub_cmd_update_cursor_info_data {3232 struct dmub_cmd_update_cursor_payload0 payload0;3233 struct dmub_cmd_update_cursor_payload1 payload1;3234};3235/**3236 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.3237 */3238struct dmub_rb_cmd_update_cursor_info {3239 /**3240 * Command header.3241 */3242 struct dmub_cmd_header header;3243 /**3244 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.3245 */3246 union dmub_cmd_update_cursor_info_data update_cursor_info_data;3247};3248 3249/**3250 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.3251 */3252struct dmub_cmd_psr_set_vtotal_data {3253 /**3254 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..3255 */3256 uint16_t psr_vtotal_idle;3257 /**3258 * PSR control version.3259 */3260 uint8_t cmd_version;3261 /**3262 * Panel Instance.3263 * Panel instance to identify which psr_state to use3264 * Currently the support is only for 0 or 13265 */3266 uint8_t panel_inst;3267 /*3268 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.3269 */3270 uint16_t psr_vtotal_su;3271 /**3272 * Explicit padding to 4 byte boundary.3273 */3274 uint8_t pad2[2];3275};3276 3277/**3278 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.3279 */3280struct dmub_rb_cmd_psr_set_vtotal {3281 /**3282 * Command header.3283 */3284 struct dmub_cmd_header header;3285 /**3286 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.3287 */3288 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;3289};3290 3291/**3292 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.3293 */3294struct dmub_cmd_psr_set_power_opt_data {3295 /**3296 * PSR control version.3297 */3298 uint8_t cmd_version;3299 /**3300 * Panel Instance.3301 * Panel instance to identify which psr_state to use3302 * Currently the support is only for 0 or 13303 */3304 uint8_t panel_inst;3305 /**3306 * Explicit padding to 4 byte boundary.3307 */3308 uint8_t pad[2];3309 /**3310 * PSR power option3311 */3312 uint32_t power_opt;3313};3314 3315/**3316 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.3317 */3318struct dmub_rb_cmd_psr_set_power_opt {3319 /**3320 * Command header.3321 */3322 struct dmub_cmd_header header;3323 /**3324 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.3325 */3326 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;3327};3328 3329/**3330 * Definition of Replay Residency GPINT command.3331 * Bit[0] - Residency mode for Revision 03332 * Bit[1] - Enable/Disable state3333 * Bit[2-3] - Revision number3334 * Bit[4-7] - Residency mode for Revision 13335 * Bit[8] - Panel instance3336 * Bit[9-15] - Reserved3337 */3338 3339enum pr_residency_mode {3340 PR_RESIDENCY_MODE_PHY = 0x0,3341 PR_RESIDENCY_MODE_ALPM,3342 PR_RESIDENCY_MODE_IPS2,3343 PR_RESIDENCY_MODE_FRAME_CNT,3344 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,3345};3346 3347#define REPLAY_RESIDENCY_MODE_SHIFT (0)3348#define REPLAY_RESIDENCY_ENABLE_SHIFT (1)3349#define REPLAY_RESIDENCY_REVISION_SHIFT (2)3350#define REPLAY_RESIDENCY_MODE2_SHIFT (4)3351 3352#define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)3353# define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)3354# define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)3355 3356#define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)3357# define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)3358# define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)3359# define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)3360 3361#define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)3362# define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)3363# define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)3364 3365#define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)3366# define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)3367# define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)3368 3369/**3370 * Definition of a replay_state.3371 */3372enum replay_state {3373 REPLAY_STATE_0 = 0x0,3374 REPLAY_STATE_1 = 0x10,3375 REPLAY_STATE_1A = 0x11,3376 REPLAY_STATE_2 = 0x20,3377 REPLAY_STATE_2A = 0x21,3378 REPLAY_STATE_3 = 0x30,3379 REPLAY_STATE_3INIT = 0x31,3380 REPLAY_STATE_4 = 0x40,3381 REPLAY_STATE_4A = 0x41,3382 REPLAY_STATE_4B = 0x42,3383 REPLAY_STATE_4C = 0x43,3384 REPLAY_STATE_4D = 0x44,3385 REPLAY_STATE_4E = 0x45,3386 REPLAY_STATE_4B_LOCKED = 0x4A,3387 REPLAY_STATE_4C_UNLOCKED = 0x4B,3388 REPLAY_STATE_5 = 0x50,3389 REPLAY_STATE_5A = 0x51,3390 REPLAY_STATE_5B = 0x52,3391 REPLAY_STATE_5A_LOCKED = 0x5A,3392 REPLAY_STATE_5B_UNLOCKED = 0x5B,3393 REPLAY_STATE_6 = 0x60,3394 REPLAY_STATE_6A = 0x61,3395 REPLAY_STATE_6B = 0x62,3396 REPLAY_STATE_INVALID = 0xFF,3397};3398 3399/**3400 * Replay command sub-types.3401 */3402enum dmub_cmd_replay_type {3403 /**3404 * Copy driver-calculated parameters to REPLAY state.3405 */3406 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,3407 /**3408 * Enable REPLAY.3409 */3410 DMUB_CMD__REPLAY_ENABLE = 1,3411 /**3412 * Set Replay power option.3413 */3414 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,3415 /**3416 * Set coasting vtotal.3417 */3418 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,3419 /**3420 * Set power opt and coasting vtotal.3421 */3422 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,3423 /**3424 * Set disabled iiming sync.3425 */3426 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,3427 /**3428 * Set Residency Frameupdate Timer.3429 */3430 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,3431 /**3432 * Set pseudo vtotal3433 */3434 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,3435 /**3436 * Set adaptive sync sdp enabled3437 */3438 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,3439 /**3440 * Set Replay General command.3441 */3442 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,3443};3444 3445/**3446 * Replay general command sub-types.3447 */3448enum dmub_cmd_replay_general_subtype {3449 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,3450 /**3451 * TODO: For backward compatible, allow new command only.3452 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,3453 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,3454 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,3455 */3456 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,3457 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,3458};3459 3460/**3461 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.3462 */3463struct dmub_cmd_replay_copy_settings_data {3464 /**3465 * Flags that can be set by driver to change some replay behaviour.3466 */3467 union replay_debug_flags debug;3468 3469 /**3470 * @flags: Flags used to determine feature functionality.3471 */3472 union replay_hw_flags flags;3473 3474 /**3475 * DPP HW instance.3476 */3477 uint8_t dpp_inst;3478 /**3479 * OTG HW instance.3480 */3481 uint8_t otg_inst;3482 /**3483 * DIG FE HW instance.3484 */3485 uint8_t digfe_inst;3486 /**3487 * DIG BE HW instance.3488 */3489 uint8_t digbe_inst;3490 /**3491 * AUX HW instance.3492 */3493 uint8_t aux_inst;3494 /**3495 * Panel Instance.3496 * Panel isntance to identify which psr_state to use3497 * Currently the support is only for 0 or 13498 */3499 uint8_t panel_inst;3500 /**3501 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare3502 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode3503 */3504 uint8_t pixel_deviation_per_line;3505 /**3506 * @max_deviation_line: The max number of deviation line that can keep the timing3507 * synchronized between the Source and Sink during Replay normal sleep mode.3508 */3509 uint8_t max_deviation_line;3510 /**3511 * Length of each horizontal line in ns.3512 */3513 uint32_t line_time_in_ns;3514 /**3515 * PHY instance.3516 */3517 uint8_t dpphy_inst;3518 /**3519 * Determines if SMU optimzations are enabled/disabled.3520 */3521 uint8_t smu_optimizations_en;3522 /**3523 * Determines if timing sync are enabled/disabled.3524 */3525 uint8_t replay_timing_sync_supported;3526 /*3527 * Use FSM state for Replay power up/down3528 */3529 uint8_t use_phy_fsm;3530};3531 3532/**3533 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.3534 */3535struct dmub_rb_cmd_replay_copy_settings {3536 /**3537 * Command header.3538 */3539 struct dmub_cmd_header header;3540 /**3541 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.3542 */3543 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;3544};3545 3546/**3547 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable3548 */3549enum replay_enable {3550 /**3551 * Disable REPLAY.3552 */3553 REPLAY_DISABLE = 0,3554 /**3555 * Enable REPLAY.3556 */3557 REPLAY_ENABLE = 1,3558};3559 3560/**3561 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.3562 */3563struct dmub_rb_cmd_replay_enable_data {3564 /**3565 * Replay enable or disable.3566 */3567 uint8_t enable;3568 /**3569 * Panel Instance.3570 * Panel isntance to identify which replay_state to use3571 * Currently the support is only for 0 or 13572 */3573 uint8_t panel_inst;3574 /**3575 * Phy state to enter.3576 * Values to use are defined in dmub_phy_fsm_state3577 */3578 uint8_t phy_fsm_state;3579 /**3580 * Phy rate for DP - RBR/HBR/HBR2/HBR3.3581 * Set this using enum phy_link_rate.3582 * This does not support HDMI/DP2 for now.3583 */3584 uint8_t phy_rate;3585};3586 3587/**3588 * Definition of a DMUB_CMD__REPLAY_ENABLE command.3589 * Replay enable/disable is controlled using action in data.3590 */3591struct dmub_rb_cmd_replay_enable {3592 /**3593 * Command header.3594 */3595 struct dmub_cmd_header header;3596 3597 struct dmub_rb_cmd_replay_enable_data data;3598};3599 3600/**3601 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.3602 */3603struct dmub_cmd_replay_set_power_opt_data {3604 /**3605 * Panel Instance.3606 * Panel isntance to identify which replay_state to use3607 * Currently the support is only for 0 or 13608 */3609 uint8_t panel_inst;3610 /**3611 * Explicit padding to 4 byte boundary.3612 */3613 uint8_t pad[3];3614 /**3615 * REPLAY power option3616 */3617 uint32_t power_opt;3618};3619 3620/**3621 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.3622 */3623struct dmub_cmd_replay_set_timing_sync_data {3624 /**3625 * Panel Instance.3626 * Panel isntance to identify which replay_state to use3627 * Currently the support is only for 0 or 13628 */3629 uint8_t panel_inst;3630 /**3631 * REPLAY set_timing_sync3632 */3633 uint8_t timing_sync_supported;3634 /**3635 * Explicit padding to 4 byte boundary.3636 */3637 uint8_t pad[2];3638};3639 3640/**3641 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.3642 */3643struct dmub_cmd_replay_set_pseudo_vtotal {3644 /**3645 * Panel Instance.3646 * Panel isntance to identify which replay_state to use3647 * Currently the support is only for 0 or 13648 */3649 uint8_t panel_inst;3650 /**3651 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal3652 */3653 uint16_t vtotal;3654 /**3655 * Explicit padding to 4 byte boundary.3656 */3657 uint8_t pad;3658};3659struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {3660 /**3661 * Panel Instance.3662 * Panel isntance to identify which replay_state to use3663 * Currently the support is only for 0 or 13664 */3665 uint8_t panel_inst;3666 /**3667 * enabled: set adaptive sync sdp enabled3668 */3669 uint8_t force_disabled;3670 3671 uint8_t pad[2];3672};3673struct dmub_cmd_replay_set_general_cmd_data {3674 /**3675 * Panel Instance.3676 * Panel isntance to identify which replay_state to use3677 * Currently the support is only for 0 or 13678 */3679 uint8_t panel_inst;3680 /**3681 * subtype: replay general cmd sub type3682 */3683 uint8_t subtype;3684 3685 uint8_t pad[2];3686 /**3687 * config data with param1 and param23688 */3689 uint32_t param1;3690 3691 uint32_t param2;3692};3693 3694/**3695 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.3696 */3697struct dmub_rb_cmd_replay_set_power_opt {3698 /**3699 * Command header.3700 */3701 struct dmub_cmd_header header;3702 /**3703 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.3704 */3705 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;3706};3707 3708/**3709 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.3710 */3711struct dmub_cmd_replay_set_coasting_vtotal_data {3712 /**3713 * 16-bit value dicated by driver that indicates the coasting vtotal.3714 */3715 uint16_t coasting_vtotal;3716 /**3717 * REPLAY control version.3718 */3719 uint8_t cmd_version;3720 /**3721 * Panel Instance.3722 * Panel isntance to identify which replay_state to use3723 * Currently the support is only for 0 or 13724 */3725 uint8_t panel_inst;3726 /**3727 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.3728 */3729 uint16_t coasting_vtotal_high;3730 /**3731 * Explicit padding to 4 byte boundary.3732 */3733 uint8_t pad[2];3734};3735 3736/**3737 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.3738 */3739struct dmub_rb_cmd_replay_set_coasting_vtotal {3740 /**3741 * Command header.3742 */3743 struct dmub_cmd_header header;3744 /**3745 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.3746 */3747 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;3748};3749 3750/**3751 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.3752 */3753struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {3754 /**3755 * Command header.3756 */3757 struct dmub_cmd_header header;3758 /**3759 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.3760 */3761 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;3762 /**3763 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.3764 */3765 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;3766};3767 3768/**3769 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.3770 */3771struct dmub_rb_cmd_replay_set_timing_sync {3772 /**3773 * Command header.3774 */3775 struct dmub_cmd_header header;3776 /**3777 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.3778 */3779 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;3780};3781 3782/**3783 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.3784 */3785struct dmub_rb_cmd_replay_set_pseudo_vtotal {3786 /**3787 * Command header.3788 */3789 struct dmub_cmd_header header;3790 /**3791 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.3792 */3793 struct dmub_cmd_replay_set_pseudo_vtotal data;3794};3795 3796/**3797 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.3798 */3799struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {3800 /**3801 * Command header.3802 */3803 struct dmub_cmd_header header;3804 /**3805 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.3806 */3807 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;3808};3809 3810/**3811 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.3812 */3813struct dmub_rb_cmd_replay_set_general_cmd {3814 /**3815 * Command header.3816 */3817 struct dmub_cmd_header header;3818 /**3819 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.3820 */3821 struct dmub_cmd_replay_set_general_cmd_data data;3822};3823 3824/**3825 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.3826 */3827struct dmub_cmd_replay_frameupdate_timer_data {3828 /**3829 * Panel Instance.3830 * Panel isntance to identify which replay_state to use3831 * Currently the support is only for 0 or 13832 */3833 uint8_t panel_inst;3834 /**3835 * Replay Frameupdate Timer Enable or not3836 */3837 uint8_t enable;3838 /**3839 * REPLAY force reflash frame update number3840 */3841 uint16_t frameupdate_count;3842};3843/**3844 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER3845 */3846struct dmub_rb_cmd_replay_set_frameupdate_timer {3847 /**3848 * Command header.3849 */3850 struct dmub_cmd_header header;3851 /**3852 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.3853 */3854 struct dmub_cmd_replay_frameupdate_timer_data data;3855};3856 3857/**3858 * Definition union of replay command set3859 */3860union dmub_replay_cmd_set {3861 /**3862 * Panel Instance.3863 * Panel isntance to identify which replay_state to use3864 * Currently the support is only for 0 or 13865 */3866 uint8_t panel_inst;3867 /**3868 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.3869 */3870 struct dmub_cmd_replay_set_timing_sync_data sync_data;3871 /**3872 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.3873 */3874 struct dmub_cmd_replay_frameupdate_timer_data timer_data;3875 /**3876 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.3877 */3878 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;3879 /**3880 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.3881 */3882 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;3883 /**3884 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.3885 */3886 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;3887};3888 3889/**3890 * Set of HW components that can be locked.3891 *3892 * Note: If updating with more HW components, fields3893 * in dmub_inbox0_cmd_lock_hw must be updated to match.3894 */3895union dmub_hw_lock_flags {3896 /**3897 * Set of HW components that can be locked.3898 */3899 struct {3900 /**3901 * Lock/unlock OTG master update lock.3902 */3903 uint8_t lock_pipe : 1;3904 /**3905 * Lock/unlock cursor.3906 */3907 uint8_t lock_cursor : 1;3908 /**3909 * Lock/unlock global update lock.3910 */3911 uint8_t lock_dig : 1;3912 /**3913 * Triple buffer lock requires additional hw programming to usual OTG master lock.3914 */3915 uint8_t triple_buffer_lock : 1;3916 } bits;3917 3918 /**3919 * Union for HW Lock flags.3920 */3921 uint8_t u8All;3922};3923 3924/**3925 * Instances of HW to be locked.3926 *3927 * Note: If updating with more HW components, fields3928 * in dmub_inbox0_cmd_lock_hw must be updated to match.3929 */3930struct dmub_hw_lock_inst_flags {3931 /**3932 * OTG HW instance for OTG master update lock.3933 */3934 uint8_t otg_inst;3935 /**3936 * OPP instance for cursor lock.3937 */3938 uint8_t opp_inst;3939 /**3940 * OTG HW instance for global update lock.3941 * TODO: Remove, and re-use otg_inst.3942 */3943 uint8_t dig_inst;3944 /**3945 * Explicit pad to 4 byte boundary.3946 */3947 uint8_t pad;3948};3949 3950/**3951 * Clients that can acquire the HW Lock Manager.3952 *3953 * Note: If updating with more clients, fields in3954 * dmub_inbox0_cmd_lock_hw must be updated to match.3955 */3956enum hw_lock_client {3957 /**3958 * Driver is the client of HW Lock Manager.3959 */3960 HW_LOCK_CLIENT_DRIVER = 0,3961 /**3962 * PSR SU is the client of HW Lock Manager.3963 */3964 HW_LOCK_CLIENT_PSR_SU = 1,3965 HW_LOCK_CLIENT_SUBVP = 3,3966 /**3967 * Replay is the client of HW Lock Manager.3968 */3969 HW_LOCK_CLIENT_REPLAY = 4,3970 HW_LOCK_CLIENT_FAMS2 = 5,3971 /**3972 * Invalid client.3973 */3974 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,3975};3976 3977/**3978 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.3979 */3980struct dmub_cmd_lock_hw_data {3981 /**3982 * Specifies the client accessing HW Lock Manager.3983 */3984 enum hw_lock_client client;3985 /**3986 * HW instances to be locked.3987 */3988 struct dmub_hw_lock_inst_flags inst_flags;3989 /**3990 * Which components to be locked.3991 */3992 union dmub_hw_lock_flags hw_locks;3993 /**3994 * Specifies lock/unlock.3995 */3996 uint8_t lock;3997 /**3998 * HW can be unlocked separately from releasing the HW Lock Mgr.3999 * This flag is set if the client wishes to release the object.4000 */4001 uint8_t should_release;4002 /**4003 * Explicit padding to 4 byte boundary.4004 */4005 uint8_t pad;4006};4007 4008/**4009 * Definition of a DMUB_CMD__HW_LOCK command.4010 * Command is used by driver and FW.4011 */4012struct dmub_rb_cmd_lock_hw {4013 /**4014 * Command header.4015 */4016 struct dmub_cmd_header header;4017 /**4018 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.4019 */4020 struct dmub_cmd_lock_hw_data lock_hw_data;4021};4022 4023/**4024 * ABM command sub-types.4025 */4026enum dmub_cmd_abm_type {4027 /**4028 * Initialize parameters for ABM algorithm.4029 * Data is passed through an indirect buffer.4030 */4031 DMUB_CMD__ABM_INIT_CONFIG = 0,4032 /**4033 * Set OTG and panel HW instance.4034 */4035 DMUB_CMD__ABM_SET_PIPE = 1,4036 /**4037 * Set user requested backklight level.4038 */4039 DMUB_CMD__ABM_SET_BACKLIGHT = 2,4040 /**4041 * Set ABM operating/aggression level.4042 */4043 DMUB_CMD__ABM_SET_LEVEL = 3,4044 /**4045 * Set ambient light level.4046 */4047 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,4048 /**4049 * Enable/disable fractional duty cycle for backlight PWM.4050 */4051 DMUB_CMD__ABM_SET_PWM_FRAC = 5,4052 4053 /**4054 * unregister vertical interrupt after steady state is reached4055 */4056 DMUB_CMD__ABM_PAUSE = 6,4057 4058 /**4059 * Save and Restore ABM state. On save we save parameters, and4060 * on restore we update state with passed in data.4061 */4062 DMUB_CMD__ABM_SAVE_RESTORE = 7,4063 4064 /**4065 * Query ABM caps.4066 */4067 DMUB_CMD__ABM_QUERY_CAPS = 8,4068 4069 /**4070 * Set ABM Events4071 */4072 DMUB_CMD__ABM_SET_EVENT = 9,4073 4074 /**4075 * Get the current ACE curve.4076 */4077 DMUB_CMD__ABM_GET_ACE_CURVE = 10,4078};4079 4080struct abm_ace_curve {4081 /**4082 * @offsets: ACE curve offsets.4083 */4084 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];4085 4086 /**4087 * @thresholds: ACE curve thresholds.4088 */4089 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];4090 4091 /**4092 * @slopes: ACE curve slopes.4093 */4094 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];4095};4096 4097struct fixed_pt_format {4098 /**4099 * @sign_bit: Indicates whether one bit is reserved for the sign.4100 */4101 bool sign_bit;4102 4103 /**4104 * @num_int_bits: Number of bits used for integer part.4105 */4106 uint8_t num_int_bits;4107 4108 /**4109 * @num_frac_bits: Number of bits used for fractional part.4110 */4111 uint8_t num_frac_bits;4112 4113 /**4114 * @pad: Explicit padding to 4 byte boundary.4115 */4116 uint8_t pad;4117};4118 4119struct abm_caps {4120 /**4121 * @num_hg_bins: Number of histogram bins.4122 */4123 uint8_t num_hg_bins;4124 4125 /**4126 * @num_ace_segments: Number of ACE curve segments.4127 */4128 uint8_t num_ace_segments;4129 4130 /**4131 * @pad: Explicit padding to 4 byte boundary.4132 */4133 uint8_t pad[2];4134 4135 /**4136 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.4137 */4138 struct fixed_pt_format ace_thresholds_format;4139 4140 /**4141 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.4142 */4143 struct fixed_pt_format ace_offsets_format;4144 4145 /**4146 * @ace_slopes_format: Format of the ACE slopes.4147 */4148 struct fixed_pt_format ace_slopes_format;4149};4150 4151/**4152 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.4153 * Requirements:4154 * - Padded explicitly to 32-bit boundary.4155 * - Must ensure this structure matches the one on driver-side,4156 * otherwise it won't be aligned.4157 */4158struct abm_config_table {4159 /**4160 * Gamma curve thresholds, used for crgb conversion.4161 */4162 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B4163 /**4164 * Gamma curve offsets, used for crgb conversion.4165 */4166 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B4167 /**4168 * Gamma curve slopes, used for crgb conversion.4169 */4170 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B4171 /**4172 * Custom backlight curve thresholds.4173 */4174 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B4175 /**4176 * Custom backlight curve offsets.4177 */4178 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B4179 /**4180 * Ambient light thresholds.4181 */4182 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B4183 /**4184 * Minimum programmable backlight.4185 */4186 uint16_t min_abm_backlight; // 122B4187 /**4188 * Minimum reduction values.4189 */4190 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B4191 /**4192 * Maximum reduction values.4193 */4194 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B4195 /**4196 * Bright positive gain.4197 */4198 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B4199 /**4200 * Dark negative gain.4201 */4202 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B4203 /**4204 * Hybrid factor.4205 */4206 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B4207 /**4208 * Contrast factor.4209 */4210 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B4211 /**4212 * Deviation gain.4213 */4214 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B4215 /**4216 * Minimum knee.4217 */4218 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B4219 /**4220 * Maximum knee.4221 */4222 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B4223 /**4224 * Unused.4225 */4226 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B4227 /**4228 * Explicit padding to 4 byte boundary.4229 */4230 uint8_t pad3[3]; // 229B4231 /**4232 * Backlight ramp reduction.4233 */4234 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B4235 /**4236 * Backlight ramp start.4237 */4238 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B4239};4240 4241/**4242 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.4243 */4244struct dmub_cmd_abm_set_pipe_data {4245 /**4246 * OTG HW instance.4247 */4248 uint8_t otg_inst;4249 4250 /**4251 * Panel Control HW instance.4252 */4253 uint8_t panel_inst;4254 4255 /**4256 * Controls how ABM will interpret a set pipe or set level command.4257 */4258 uint8_t set_pipe_option;4259 4260 /**4261 * Unused.4262 * TODO: Remove.4263 */4264 uint8_t ramping_boundary;4265 4266 /**4267 * PwrSeq HW Instance.4268 */4269 uint8_t pwrseq_inst;4270 4271 /**4272 * Explicit padding to 4 byte boundary.4273 */4274 uint8_t pad[3];4275};4276 4277/**4278 * Definition of a DMUB_CMD__ABM_SET_PIPE command.4279 */4280struct dmub_rb_cmd_abm_set_pipe {4281 /**4282 * Command header.4283 */4284 struct dmub_cmd_header header;4285 4286 /**4287 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.4288 */4289 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;4290};4291 4292/**4293 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.4294 */4295struct dmub_cmd_abm_set_backlight_data {4296 /**4297 * Number of frames to ramp to backlight user level.4298 */4299 uint32_t frame_ramp;4300 4301 /**4302 * Requested backlight level from user.4303 */4304 uint32_t backlight_user_level;4305 4306 /**4307 * ABM control version.4308 */4309 uint8_t version;4310 4311 /**4312 * Panel Control HW instance mask.4313 * Bit 0 is Panel Control HW instance 0.4314 * Bit 1 is Panel Control HW instance 1.4315 */4316 uint8_t panel_mask;4317 4318 /**4319 * Explicit padding to 4 byte boundary.4320 */4321 uint8_t pad[2];4322};4323 4324/**4325 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.4326 */4327struct dmub_rb_cmd_abm_set_backlight {4328 /**4329 * Command header.4330 */4331 struct dmub_cmd_header header;4332 4333 /**4334 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.4335 */4336 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;4337};4338 4339/**4340 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.4341 */4342struct dmub_cmd_abm_set_level_data {4343 /**4344 * Set current ABM operating/aggression level.4345 */4346 uint32_t level;4347 4348 /**4349 * ABM control version.4350 */4351 uint8_t version;4352 4353 /**4354 * Panel Control HW instance mask.4355 * Bit 0 is Panel Control HW instance 0.4356 * Bit 1 is Panel Control HW instance 1.4357 */4358 uint8_t panel_mask;4359 4360 /**4361 * Explicit padding to 4 byte boundary.4362 */4363 uint8_t pad[2];4364};4365 4366/**4367 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.4368 */4369struct dmub_rb_cmd_abm_set_level {4370 /**4371 * Command header.4372 */4373 struct dmub_cmd_header header;4374 4375 /**4376 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.4377 */4378 struct dmub_cmd_abm_set_level_data abm_set_level_data;4379};4380 4381/**4382 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.4383 */4384struct dmub_cmd_abm_set_ambient_level_data {4385 /**4386 * Ambient light sensor reading from OS.4387 */4388 uint32_t ambient_lux;4389 4390 /**4391 * ABM control version.4392 */4393 uint8_t version;4394 4395 /**4396 * Panel Control HW instance mask.4397 * Bit 0 is Panel Control HW instance 0.4398 * Bit 1 is Panel Control HW instance 1.4399 */4400 uint8_t panel_mask;4401 4402 /**4403 * Explicit padding to 4 byte boundary.4404 */4405 uint8_t pad[2];4406};4407 4408/**4409 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.4410 */4411struct dmub_rb_cmd_abm_set_ambient_level {4412 /**4413 * Command header.4414 */4415 struct dmub_cmd_header header;4416 4417 /**4418 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.4419 */4420 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;4421};4422 4423/**4424 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.4425 */4426struct dmub_cmd_abm_set_pwm_frac_data {4427 /**4428 * Enable/disable fractional duty cycle for backlight PWM.4429 * TODO: Convert to uint8_t.4430 */4431 uint32_t fractional_pwm;4432 4433 /**4434 * ABM control version.4435 */4436 uint8_t version;4437 4438 /**4439 * Panel Control HW instance mask.4440 * Bit 0 is Panel Control HW instance 0.4441 * Bit 1 is Panel Control HW instance 1.4442 */4443 uint8_t panel_mask;4444 4445 /**4446 * Explicit padding to 4 byte boundary.4447 */4448 uint8_t pad[2];4449};4450 4451/**4452 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.4453 */4454struct dmub_rb_cmd_abm_set_pwm_frac {4455 /**4456 * Command header.4457 */4458 struct dmub_cmd_header header;4459 4460 /**4461 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.4462 */4463 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;4464};4465 4466/**4467 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.4468 */4469struct dmub_cmd_abm_init_config_data {4470 /**4471 * Location of indirect buffer used to pass init data to ABM.4472 */4473 union dmub_addr src;4474 4475 /**4476 * Indirect buffer length.4477 */4478 uint16_t bytes;4479 4480 4481 /**4482 * ABM control version.4483 */4484 uint8_t version;4485 4486 /**4487 * Panel Control HW instance mask.4488 * Bit 0 is Panel Control HW instance 0.4489 * Bit 1 is Panel Control HW instance 1.4490 */4491 uint8_t panel_mask;4492 4493 /**4494 * Explicit padding to 4 byte boundary.4495 */4496 uint8_t pad[2];4497};4498 4499/**4500 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.4501 */4502struct dmub_rb_cmd_abm_init_config {4503 /**4504 * Command header.4505 */4506 struct dmub_cmd_header header;4507 4508 /**4509 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.4510 */4511 struct dmub_cmd_abm_init_config_data abm_init_config_data;4512};4513 4514/**4515 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.4516 */4517 4518struct dmub_cmd_abm_pause_data {4519 4520 /**4521 * Panel Control HW instance mask.4522 * Bit 0 is Panel Control HW instance 0.4523 * Bit 1 is Panel Control HW instance 1.4524 */4525 uint8_t panel_mask;4526 4527 /**4528 * OTG hw instance4529 */4530 uint8_t otg_inst;4531 4532 /**4533 * Enable or disable ABM pause4534 */4535 uint8_t enable;4536 4537 /**4538 * Explicit padding to 4 byte boundary.4539 */4540 uint8_t pad[1];4541};4542 4543/**4544 * Definition of a DMUB_CMD__ABM_PAUSE command.4545 */4546struct dmub_rb_cmd_abm_pause {4547 /**4548 * Command header.4549 */4550 struct dmub_cmd_header header;4551 4552 /**4553 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.4554 */4555 struct dmub_cmd_abm_pause_data abm_pause_data;4556};4557 4558/**4559 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.4560 */4561struct dmub_cmd_abm_query_caps_in {4562 /**4563 * Panel instance.4564 */4565 uint8_t panel_inst;4566 4567 /**4568 * Explicit padding to 4 byte boundary.4569 */4570 uint8_t pad[3];4571};4572 4573/**4574 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.4575 */4576struct dmub_cmd_abm_query_caps_out {4577 /**4578 * SW Algorithm caps.4579 */4580 struct abm_caps sw_caps;4581 4582 /**4583 * ABM HW caps.4584 */4585 struct abm_caps hw_caps;4586};4587 4588/**4589 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.4590 */4591struct dmub_rb_cmd_abm_query_caps {4592 /**4593 * Command header.4594 */4595 struct dmub_cmd_header header;4596 4597 /**4598 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.4599 */4600 union {4601 struct dmub_cmd_abm_query_caps_in abm_query_caps_in;4602 struct dmub_cmd_abm_query_caps_out abm_query_caps_out;4603 } data;4604};4605 4606/**4607 * enum dmub_abm_ace_curve_type - ACE curve type.4608 */4609enum dmub_abm_ace_curve_type {4610 /**4611 * ACE curve as defined by the SW layer.4612 */4613 ABM_ACE_CURVE_TYPE__SW = 0,4614 /**4615 * ACE curve as defined by the SW to HW translation interface layer.4616 */4617 ABM_ACE_CURVE_TYPE__SW_IF = 1,4618};4619 4620/**4621 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.4622 */4623struct dmub_rb_cmd_abm_get_ace_curve {4624 /**4625 * Command header.4626 */4627 struct dmub_cmd_header header;4628 4629 /**4630 * Address where ACE curve should be copied.4631 */4632 union dmub_addr dest;4633 4634 /**4635 * Type of ACE curve being queried.4636 */4637 enum dmub_abm_ace_curve_type ace_type;4638 4639 /**4640 * Indirect buffer length.4641 */4642 uint16_t bytes;4643 4644 /**4645 * eDP panel instance.4646 */4647 uint8_t panel_inst;4648 4649 /**4650 * Explicit padding to 4 byte boundary.4651 */4652 uint8_t pad;4653};4654 4655/**4656 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.4657 */4658struct dmub_rb_cmd_abm_save_restore {4659 /**4660 * Command header.4661 */4662 struct dmub_cmd_header header;4663 4664 /**4665 * OTG hw instance4666 */4667 uint8_t otg_inst;4668 4669 /**4670 * Enable or disable ABM pause4671 */4672 uint8_t freeze;4673 4674 /**4675 * Explicit padding to 4 byte boundary.4676 */4677 uint8_t debug;4678 4679 /**4680 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.4681 */4682 struct dmub_cmd_abm_init_config_data abm_init_config_data;4683};4684 4685/**4686 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.4687 */4688 4689struct dmub_cmd_abm_set_event_data {4690 4691 /**4692 * VB Scaling Init. Strength Mapping4693 * Byte 0: 0~255 for VB level 04694 * Byte 1: 0~255 for VB level 14695 * Byte 2: 0~255 for VB level 24696 * Byte 3: 0~255 for VB level 34697 */4698 uint32_t vb_scaling_strength_mapping;4699 /**4700 * VariBright Scaling Enable4701 */4702 uint8_t vb_scaling_enable;4703 /**4704 * Panel Control HW instance mask.4705 * Bit 0 is Panel Control HW instance 0.4706 * Bit 1 is Panel Control HW instance 1.4707 */4708 uint8_t panel_mask;4709 4710 /**4711 * Explicit padding to 4 byte boundary.4712 */4713 uint8_t pad[2];4714};4715 4716/**4717 * Definition of a DMUB_CMD__ABM_SET_EVENT command.4718 */4719struct dmub_rb_cmd_abm_set_event {4720 /**4721 * Command header.4722 */4723 struct dmub_cmd_header header;4724 4725 /**4726 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.4727 */4728 struct dmub_cmd_abm_set_event_data abm_set_event_data;4729};4730 4731/**4732 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.4733 */4734struct dmub_cmd_query_feature_caps_data {4735 /**4736 * DMUB feature capabilities.4737 * After DMUB init, driver will query FW capabilities prior to enabling certain features.4738 */4739 struct dmub_feature_caps feature_caps;4740};4741 4742/**4743 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.4744 */4745struct dmub_rb_cmd_query_feature_caps {4746 /**4747 * Command header.4748 */4749 struct dmub_cmd_header header;4750 /**4751 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.4752 */4753 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;4754};4755 4756/**4757 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.4758 */4759struct dmub_cmd_visual_confirm_color_data {4760 /**4761 * DMUB visual confirm color4762 */4763 struct dmub_visual_confirm_color visual_confirm_color;4764};4765 4766/**4767 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.4768 */4769struct dmub_rb_cmd_get_visual_confirm_color {4770 /**4771 * Command header.4772 */4773 struct dmub_cmd_header header;4774 /**4775 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.4776 */4777 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;4778};4779 4780/**4781 * enum dmub_cmd_panel_cntl_type - Panel control command.4782 */4783enum dmub_cmd_panel_cntl_type {4784 /**4785 * Initializes embedded panel hardware blocks.4786 */4787 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,4788 /**4789 * Queries backlight info for the embedded panel.4790 */4791 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,4792 /**4793 * Sets the PWM Freq as per user's requirement.4794 */4795 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,4796};4797 4798/**4799 * struct dmub_cmd_panel_cntl_data - Panel control data.4800 */4801struct dmub_cmd_panel_cntl_data {4802 uint32_t pwrseq_inst; /**< pwrseq instance */4803 uint32_t current_backlight; /* in/out */4804 uint32_t bl_pwm_cntl; /* in/out */4805 uint32_t bl_pwm_period_cntl; /* in/out */4806 uint32_t bl_pwm_ref_div1; /* in/out */4807 uint8_t is_backlight_on : 1; /* in/out */4808 uint8_t is_powered_on : 1; /* in/out */4809 uint8_t padding[3];4810 uint32_t bl_pwm_ref_div2; /* in/out */4811 uint8_t reserved[4];4812};4813 4814/**4815 * struct dmub_rb_cmd_panel_cntl - Panel control command.4816 */4817struct dmub_rb_cmd_panel_cntl {4818 struct dmub_cmd_header header; /**< header */4819 struct dmub_cmd_panel_cntl_data data; /**< payload */4820};4821 4822struct dmub_optc_state {4823 uint32_t v_total_max;4824 uint32_t v_total_min;4825 uint32_t tg_inst;4826};4827 4828struct dmub_rb_cmd_drr_update {4829 struct dmub_cmd_header header;4830 struct dmub_optc_state dmub_optc_state_req;4831};4832 4833struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {4834 uint32_t pix_clk_100hz;4835 uint8_t max_ramp_step;4836 uint8_t pipes;4837 uint8_t min_refresh_in_hz;4838 uint8_t pipe_count;4839 uint8_t pipe_index[4];4840};4841 4842struct dmub_cmd_fw_assisted_mclk_switch_config {4843 uint8_t fams_enabled;4844 uint8_t visual_confirm_enabled;4845 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive4846 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];4847};4848 4849struct dmub_rb_cmd_fw_assisted_mclk_switch {4850 struct dmub_cmd_header header;4851 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;4852};4853 4854/**4855 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.4856 */4857struct dmub_cmd_lvtma_control_data {4858 uint8_t uc_pwr_action; /**< LVTMA_ACTION */4859 uint8_t bypass_panel_control_wait;4860 uint8_t reserved_0[2]; /**< For future use */4861 uint8_t pwrseq_inst; /**< LVTMA control instance */4862 uint8_t reserved_1[3]; /**< For future use */4863};4864 4865/**4866 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.4867 */4868struct dmub_rb_cmd_lvtma_control {4869 /**4870 * Command header.4871 */4872 struct dmub_cmd_header header;4873 /**4874 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.4875 */4876 struct dmub_cmd_lvtma_control_data data;4877};4878 4879/**4880 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.4881 */4882struct dmub_rb_cmd_transmitter_query_dp_alt_data {4883 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */4884 uint8_t is_usb; /**< is phy is usb */4885 uint8_t is_dp_alt_disable; /**< is dp alt disable */4886 uint8_t is_dp4; /**< is dp in 4 lane */4887};4888 4889/**4890 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.4891 */4892struct dmub_rb_cmd_transmitter_query_dp_alt {4893 struct dmub_cmd_header header; /**< header */4894 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */4895};4896 4897struct phy_test_mode {4898 uint8_t mode;4899 uint8_t pat0;4900 uint8_t pad[2];4901};4902 4903/**4904 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.4905 */4906struct dmub_rb_cmd_transmitter_set_phy_fsm_data {4907 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */4908 uint8_t mode; /**< HDMI/DP/DP2 etc */4909 uint8_t lane_num; /**< Number of lanes */4910 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */4911 struct phy_test_mode test_mode;4912 enum dmub_phy_fsm_state state;4913 uint32_t status;4914 uint8_t pad;4915};4916 4917/**4918 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.4919 */4920struct dmub_rb_cmd_transmitter_set_phy_fsm {4921 struct dmub_cmd_header header; /**< header */4922 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */4923};4924 4925/**4926 * Maximum number of bytes a chunk sent to DMUB for parsing4927 */4928#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 84929 4930/**4931 * Represent a chunk of CEA blocks sent to DMUB for parsing4932 */4933struct dmub_cmd_send_edid_cea {4934 uint16_t offset; /**< offset into the CEA block */4935 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */4936 uint16_t cea_total_length; /**< total length of the CEA block */4937 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */4938 uint8_t pad[3]; /**< padding and for future expansion */4939};4940 4941/**4942 * Result of VSDB parsing from CEA block4943 */4944struct dmub_cmd_edid_cea_amd_vsdb {4945 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */4946 uint8_t freesync_supported; /**< 1 if Freesync is supported */4947 uint16_t amd_vsdb_version; /**< AMD VSDB version */4948 uint16_t min_frame_rate; /**< Maximum frame rate */4949 uint16_t max_frame_rate; /**< Minimum frame rate */4950};4951 4952/**4953 * Result of sending a CEA chunk4954 */4955struct dmub_cmd_edid_cea_ack {4956 uint16_t offset; /**< offset of the chunk into the CEA block */4957 uint8_t success; /**< 1 if this sending of chunk succeeded */4958 uint8_t pad; /**< padding and for future expansion */4959};4960 4961/**4962 * Specify whether the result is an ACK/NACK or the parsing has finished4963 */4964enum dmub_cmd_edid_cea_reply_type {4965 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */4966 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */4967};4968 4969/**4970 * Definition of a DMUB_CMD__EDID_CEA command.4971 */4972struct dmub_rb_cmd_edid_cea {4973 struct dmub_cmd_header header; /**< Command header */4974 union dmub_cmd_edid_cea_data {4975 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */4976 struct dmub_cmd_edid_cea_output { /**< output with results */4977 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */4978 union {4979 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;4980 struct dmub_cmd_edid_cea_ack ack;4981 };4982 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */4983 } data; /**< Command data */4984 4985};4986 4987/**4988 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.4989 */4990struct dmub_cmd_cable_id_input {4991 uint8_t phy_inst; /**< phy inst for cable id data */4992};4993 4994/**4995 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.4996 */4997struct dmub_cmd_cable_id_output {4998 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */4999 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */5000 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */5001 uint8_t RESERVED :2; /**< reserved means not defined */5002};5003 5004/**5005 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command5006 */5007struct dmub_rb_cmd_get_usbc_cable_id {5008 struct dmub_cmd_header header; /**< Command header */5009 /**5010 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.5011 */5012 union dmub_cmd_cable_id_data {5013 struct dmub_cmd_cable_id_input input; /**< Input */5014 struct dmub_cmd_cable_id_output output; /**< Output */5015 uint8_t output_raw; /**< Raw data output */5016 } data;5017};5018 5019/**5020 * Command type of a DMUB_CMD__SECURE_DISPLAY command5021 */5022enum dmub_cmd_secure_display_type {5023 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */5024 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,5025 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY5026};5027 5028/**5029 * Definition of a DMUB_CMD__SECURE_DISPLAY command5030 */5031struct dmub_rb_cmd_secure_display {5032 struct dmub_cmd_header header;5033 /**5034 * Data passed from driver to dmub firmware.5035 */5036 struct dmub_cmd_roi_info {5037 uint16_t x_start;5038 uint16_t x_end;5039 uint16_t y_start;5040 uint16_t y_end;5041 uint8_t otg_id;5042 uint8_t phy_id;5043 } roi_info;5044};5045 5046/**5047 * Command type of a DMUB_CMD__PSP command5048 */5049enum dmub_cmd_psp_type {5050 DMUB_CMD__PSP_ASSR_ENABLE = 05051};5052 5053/**5054 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.5055 */5056struct dmub_cmd_assr_enable_data {5057 /**5058 * ASSR enable or disable.5059 */5060 uint8_t enable;5061 /**5062 * PHY port type.5063 * Indicates eDP / non-eDP port type5064 */5065 uint8_t phy_port_type;5066 /**5067 * PHY port ID.5068 */5069 uint8_t phy_port_id;5070 /**5071 * Link encoder index.5072 */5073 uint8_t link_enc_index;5074 /**5075 * HPO mode.5076 */5077 uint8_t hpo_mode;5078 5079 /**5080 * Reserved field.5081 */5082 uint8_t reserved[7];5083};5084 5085/**5086 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.5087 */5088struct dmub_rb_cmd_assr_enable {5089 /**5090 * Command header.5091 */5092 struct dmub_cmd_header header;5093 5094 /**5095 * Assr data.5096 */5097 struct dmub_cmd_assr_enable_data assr_data;5098 5099 /**5100 * Reserved field.5101 */5102 uint32_t reserved[3];5103};5104 5105/**5106 * union dmub_rb_cmd - DMUB inbox command.5107 */5108union dmub_rb_cmd {5109 /**5110 * Elements shared with all commands.5111 */5112 struct dmub_rb_cmd_common cmd_common;5113 /**5114 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.5115 */5116 struct dmub_rb_cmd_read_modify_write read_modify_write;5117 /**5118 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.5119 */5120 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;5121 /**5122 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.5123 */5124 struct dmub_rb_cmd_burst_write burst_write;5125 /**5126 * Definition of a DMUB_CMD__REG_REG_WAIT command.5127 */5128 struct dmub_rb_cmd_reg_wait reg_wait;5129 /**5130 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.5131 */5132 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;5133 /**5134 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.5135 */5136 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;5137 /**5138 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.5139 */5140 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;5141 /**5142 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.5143 */5144 struct dmub_rb_cmd_dpphy_init dpphy_init;5145 /**5146 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.5147 */5148 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;5149 /**5150 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.5151 */5152 struct dmub_rb_cmd_domain_control domain_control;5153 /**5154 * Definition of a DMUB_CMD__PSR_SET_VERSION command.5155 */5156 struct dmub_rb_cmd_psr_set_version psr_set_version;5157 /**5158 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.5159 */5160 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;5161 /**5162 * Definition of a DMUB_CMD__PSR_ENABLE command.5163 */5164 struct dmub_rb_cmd_psr_enable psr_enable;5165 /**5166 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.5167 */5168 struct dmub_rb_cmd_psr_set_level psr_set_level;5169 /**5170 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.5171 */5172 struct dmub_rb_cmd_psr_force_static psr_force_static;5173 /**5174 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.5175 */5176 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;5177 /**5178 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.5179 */5180 struct dmub_rb_cmd_update_cursor_info update_cursor_info;5181 /**5182 * Definition of a DMUB_CMD__HW_LOCK command.5183 * Command is used by driver and FW.5184 */5185 struct dmub_rb_cmd_lock_hw lock_hw;5186 /**5187 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.5188 */5189 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;5190 /**5191 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.5192 */5193 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;5194 /**5195 * Definition of a DMUB_CMD__PLAT_54186_WA command.5196 */5197 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;5198 /**5199 * Definition of a DMUB_CMD__MALL command.5200 */5201 struct dmub_rb_cmd_mall mall;5202 5203 /**5204 * Definition of a DMUB_CMD__CAB command.5205 */5206 struct dmub_rb_cmd_cab_for_ss cab;5207 5208 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;5209 5210 /**5211 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.5212 */5213 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;5214 5215 /**5216 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.5217 */5218 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;5219 5220 /**5221 * Definition of DMUB_CMD__PANEL_CNTL commands.5222 */5223 struct dmub_rb_cmd_panel_cntl panel_cntl;5224 5225 /**5226 * Definition of a DMUB_CMD__ABM_SET_PIPE command.5227 */5228 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;5229 5230 /**5231 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.5232 */5233 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;5234 5235 /**5236 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.5237 */5238 struct dmub_rb_cmd_abm_set_level abm_set_level;5239 5240 /**5241 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.5242 */5243 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;5244 5245 /**5246 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.5247 */5248 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;5249 5250 /**5251 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.5252 */5253 struct dmub_rb_cmd_abm_init_config abm_init_config;5254 5255 /**5256 * Definition of a DMUB_CMD__ABM_PAUSE command.5257 */5258 struct dmub_rb_cmd_abm_pause abm_pause;5259 5260 /**5261 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.5262 */5263 struct dmub_rb_cmd_abm_save_restore abm_save_restore;5264 5265 /**5266 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.5267 */5268 struct dmub_rb_cmd_abm_query_caps abm_query_caps;5269 5270 /**5271 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.5272 */5273 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;5274 5275 /**5276 * Definition of a DMUB_CMD__ABM_SET_EVENT command.5277 */5278 struct dmub_rb_cmd_abm_set_event abm_set_event;5279 5280 /**5281 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.5282 */5283 struct dmub_rb_cmd_dp_aux_access dp_aux_access;5284 5285 /**5286 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.5287 */5288 struct dmub_rb_cmd_outbox1_enable outbox1_enable;5289 5290 /**5291 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.5292 */5293 struct dmub_rb_cmd_query_feature_caps query_feature_caps;5294 5295 /**5296 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.5297 */5298 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;5299 struct dmub_rb_cmd_drr_update drr_update;5300 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;5301 5302 /**5303 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.5304 */5305 struct dmub_rb_cmd_lvtma_control lvtma_control;5306 /**5307 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.5308 */5309 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;5310 /**5311 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.5312 */5313 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;5314 /**5315 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.5316 */5317 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;5318 /**5319 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.5320 */5321 struct dmub_rb_cmd_set_config_access set_config_access;5322 /**5323 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.5324 */5325 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;5326 /**5327 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.5328 */5329 struct dmub_rb_cmd_set_tps_notification set_tps_notification;5330 /**5331 * Definition of a DMUB_CMD__EDID_CEA command.5332 */5333 struct dmub_rb_cmd_edid_cea edid_cea;5334 /**5335 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.5336 */5337 struct dmub_rb_cmd_get_usbc_cable_id cable_id;5338 5339 /**5340 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.5341 */5342 struct dmub_rb_cmd_query_hpd_state query_hpd;5343 /**5344 * Definition of a DMUB_CMD__SECURE_DISPLAY command.5345 */5346 struct dmub_rb_cmd_secure_display secure_display;5347 5348 /**5349 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.5350 */5351 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;5352 /**5353 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.5354 */5355 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;5356 /**5357 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.5358 */5359 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;5360 /*5361 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.5362 */5363 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;5364 /**5365 * Definition of a DMUB_CMD__REPLAY_ENABLE command.5366 */5367 struct dmub_rb_cmd_replay_enable replay_enable;5368 /**5369 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.5370 */5371 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;5372 /**5373 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.5374 */5375 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;5376 /**5377 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.5378 */5379 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;5380 5381 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;5382 /**5383 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.5384 */5385 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;5386 /**5387 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.5388 */5389 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;5390 /**5391 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.5392 */5393 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;5394 /**5395 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.5396 */5397 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;5398 /**5399 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.5400 */5401 struct dmub_rb_cmd_assr_enable assr_enable;5402 struct dmub_rb_cmd_fams2 fams2_config;5403 5404 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;5405 5406 struct dmub_rb_cmd_fams2_flip fams2_flip;5407};5408 5409/**5410 * union dmub_rb_out_cmd - Outbox command5411 */5412union dmub_rb_out_cmd {5413 /**5414 * Parameters common to every command.5415 */5416 struct dmub_rb_cmd_common cmd_common;5417 /**5418 * AUX reply command.5419 */5420 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;5421 /**5422 * HPD notify command.5423 */5424 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;5425 /**5426 * SET_CONFIG reply command.5427 */5428 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;5429 /**5430 * DPIA notification command.5431 */5432 struct dmub_rb_cmd_dpia_notification dpia_notification;5433 /**5434 * HPD sense notification command.5435 */5436 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;5437};5438#pragma pack(pop)5439 5440 5441//==============================================================================5442//</DMUB_CMD>===================================================================5443//==============================================================================5444//< DMUB_RB>====================================================================5445//==============================================================================5446 5447/**5448 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer5449 */5450struct dmub_rb_init_params {5451 void *ctx; /**< Caller provided context pointer */5452 void *base_address; /**< CPU base address for ring's data */5453 uint32_t capacity; /**< Ringbuffer capacity in bytes */5454 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */5455 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */5456};5457 5458/**5459 * struct dmub_rb - Inbox or outbox DMUB ringbuffer5460 */5461struct dmub_rb {5462 void *base_address; /**< CPU address for the ring's data */5463 uint32_t rptr; /**< Read pointer for consumer in bytes */5464 uint32_t wrpt; /**< Write pointer for producer in bytes */5465 uint32_t capacity; /**< Ringbuffer capacity in bytes */5466 5467 void *ctx; /**< Caller provided context pointer */5468 void *dmub; /**< Pointer to the DMUB interface */5469};5470 5471/**5472 * @brief Checks if the ringbuffer is empty.5473 *5474 * @param rb DMUB Ringbuffer5475 * @return true if empty5476 * @return false otherwise5477 */5478static inline bool dmub_rb_empty(struct dmub_rb *rb)5479{5480 return (rb->wrpt == rb->rptr);5481}5482 5483/**5484 * @brief Checks if the ringbuffer is full5485 *5486 * @param rb DMUB Ringbuffer5487 * @return true if full5488 * @return false otherwise5489 */5490static inline bool dmub_rb_full(struct dmub_rb *rb)5491{5492 uint32_t data_count;5493 5494 if (rb->wrpt >= rb->rptr)5495 data_count = rb->wrpt - rb->rptr;5496 else5497 data_count = rb->capacity - (rb->rptr - rb->wrpt);5498 5499 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));5500}5501 5502/**5503 * @brief Pushes a command into the ringbuffer5504 *5505 * @param rb DMUB ringbuffer5506 * @param cmd The command to push5507 * @return true if the ringbuffer was not full5508 * @return false otherwise5509 */5510static inline bool dmub_rb_push_front(struct dmub_rb *rb,5511 const union dmub_rb_cmd *cmd)5512{5513 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);5514 const uint64_t *src = (const uint64_t *)cmd;5515 uint8_t i;5516 5517 if (dmub_rb_full(rb))5518 return false;5519 5520 // copying data5521 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)5522 *dst++ = *src++;5523 5524 rb->wrpt += DMUB_RB_CMD_SIZE;5525 5526 if (rb->wrpt >= rb->capacity)5527 rb->wrpt %= rb->capacity;5528 5529 return true;5530}5531 5532/**5533 * @brief Pushes a command into the DMUB outbox ringbuffer5534 *5535 * @param rb DMUB outbox ringbuffer5536 * @param cmd Outbox command5537 * @return true if not full5538 * @return false otherwise5539 */5540static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,5541 const union dmub_rb_out_cmd *cmd)5542{5543 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;5544 const uint8_t *src = (const uint8_t *)cmd;5545 5546 if (dmub_rb_full(rb))5547 return false;5548 5549 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);5550 5551 rb->wrpt += DMUB_RB_CMD_SIZE;5552 5553 if (rb->wrpt >= rb->capacity)5554 rb->wrpt %= rb->capacity;5555 5556 return true;5557}5558 5559/**5560 * @brief Returns the next unprocessed command in the ringbuffer.5561 *5562 * @param rb DMUB ringbuffer5563 * @param cmd The command to return5564 * @return true if not empty5565 * @return false otherwise5566 */5567static inline bool dmub_rb_front(struct dmub_rb *rb,5568 union dmub_rb_cmd **cmd)5569{5570 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;5571 5572 if (dmub_rb_empty(rb))5573 return false;5574 5575 *cmd = (union dmub_rb_cmd *)rb_cmd;5576 5577 return true;5578}5579 5580/**5581 * @brief Determines the next ringbuffer offset.5582 *5583 * @param rb DMUB inbox ringbuffer5584 * @param num_cmds Number of commands5585 * @param next_rptr The next offset in the ringbuffer5586 */5587static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,5588 uint32_t num_cmds,5589 uint32_t *next_rptr)5590{5591 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;5592 5593 if (*next_rptr >= rb->capacity)5594 *next_rptr %= rb->capacity;5595}5596 5597/**5598 * @brief Returns a pointer to a command in the inbox.5599 *5600 * @param rb DMUB inbox ringbuffer5601 * @param cmd The inbox command to return5602 * @param rptr The ringbuffer offset5603 * @return true if not empty5604 * @return false otherwise5605 */5606static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,5607 union dmub_rb_cmd **cmd,5608 uint32_t rptr)5609{5610 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;5611 5612 if (dmub_rb_empty(rb))5613 return false;5614 5615 *cmd = (union dmub_rb_cmd *)rb_cmd;5616 5617 return true;5618}5619 5620/**5621 * @brief Returns the next unprocessed command in the outbox.5622 *5623 * @param rb DMUB outbox ringbuffer5624 * @param cmd The outbox command to return5625 * @return true if not empty5626 * @return false otherwise5627 */5628static inline bool dmub_rb_out_front(struct dmub_rb *rb,5629 union dmub_rb_out_cmd *cmd)5630{5631 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);5632 uint64_t *dst = (uint64_t *)cmd;5633 uint8_t i;5634 5635 if (dmub_rb_empty(rb))5636 return false;5637 5638 // copying data5639 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)5640 *dst++ = *src++;5641 5642 return true;5643}5644 5645/**5646 * @brief Removes the front entry in the ringbuffer.5647 *5648 * @param rb DMUB ringbuffer5649 * @return true if the command was removed5650 * @return false if there were no commands5651 */5652static inline bool dmub_rb_pop_front(struct dmub_rb *rb)5653{5654 if (dmub_rb_empty(rb))5655 return false;5656 5657 rb->rptr += DMUB_RB_CMD_SIZE;5658 5659 if (rb->rptr >= rb->capacity)5660 rb->rptr %= rb->capacity;5661 5662 return true;5663}5664 5665/**5666 * @brief Flushes commands in the ringbuffer to framebuffer memory.5667 *5668 * Avoids a race condition where DMCUB accesses memory while5669 * there are still writes in flight to framebuffer.5670 *5671 * @param rb DMUB ringbuffer5672 */5673static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)5674{5675 uint32_t rptr = rb->rptr;5676 uint32_t wptr = rb->wrpt;5677 5678 while (rptr != wptr) {5679 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);5680 uint8_t i;5681 5682 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)5683 (void)READ_ONCE(*data++);5684 5685 rptr += DMUB_RB_CMD_SIZE;5686 if (rptr >= rb->capacity)5687 rptr %= rb->capacity;5688 }5689}5690 5691/**5692 * @brief Initializes a DMCUB ringbuffer5693 *5694 * @param rb DMUB ringbuffer5695 * @param init_params initial configuration for the ringbuffer5696 */5697static inline void dmub_rb_init(struct dmub_rb *rb,5698 struct dmub_rb_init_params *init_params)5699{5700 rb->base_address = init_params->base_address;5701 rb->capacity = init_params->capacity;5702 rb->rptr = init_params->read_ptr;5703 rb->wrpt = init_params->write_ptr;5704}5705 5706/**5707 * @brief Copies output data from in/out commands into the given command.5708 *5709 * @param rb DMUB ringbuffer5710 * @param cmd Command to copy data into5711 */5712static inline void dmub_rb_get_return_data(struct dmub_rb *rb,5713 union dmub_rb_cmd *cmd)5714{5715 // Copy rb entry back into command5716 uint8_t *rd_ptr = (rb->rptr == 0) ?5717 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :5718 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;5719 5720 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);5721}5722 5723//==============================================================================5724//</DMUB_RB>====================================================================5725//==============================================================================5726#endif /* _DMUB_CMD_H_ */5727