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1// SPDX-License-Identifier: MIT2//3// Copyright 2024 Advanced Micro Devices, Inc.4 5#include "../dmub_srv.h"6#include "dmub_reg.h"7#include "dmub_dcn401.h"8 9#include "dcn/dcn_4_1_0_offset.h"10#include "dcn/dcn_4_1_0_sh_mask.h"11 12#define DCN_BASE__INST0_SEG2 0x000034C013 14#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg15#define CTX dmub16#define REGS dmub->regs_dcn40117#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)18 19const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs = {20#define DMUB_SR(reg) REG_OFFSET_EXP(reg),21 {22 DMUB_DCN401_REGS()23 DMCUB_INTERNAL_REGS()24 },25#undef DMUB_SR26 27#define DMUB_SF(reg, field) FD_MASK(reg, field),28 { DMUB_DCN401_FIELDS() },29#undef DMUB_SF30 31#define DMUB_SF(reg, field) FD_SHIFT(reg, field),32 { DMUB_DCN401_FIELDS() },33#undef DMUB_SF34};35 36static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,37 uint64_t *fb_base,38 uint64_t *fb_offset)39{40 uint32_t tmp;41 42 if (dmub->fb_base || dmub->fb_offset) {43 *fb_base = dmub->fb_base;44 *fb_offset = dmub->fb_offset;45 return;46 }47 48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);49 *fb_base = (uint64_t)tmp << 24;50 51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);52 *fb_offset = (uint64_t)tmp << 24;53}54 55static inline void dmub_dcn401_translate_addr(const union dmub_addr *addr_in,56 uint64_t fb_base,57 uint64_t fb_offset,58 union dmub_addr *addr_out)59{60 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;61}62 63void dmub_dcn401_reset(struct dmub_srv *dmub)64{65 union dmub_gpint_data_register cmd;66 const uint32_t timeout = 30;67 uint32_t in_reset, scratch, i;68 69 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);70 71 if (in_reset == 0) {72 cmd.bits.status = 1;73 cmd.bits.command_code = DMUB_GPINT__STOP_FW;74 cmd.bits.param = 0;75 76 dmub->hw_funcs.set_gpint(dmub, cmd);77 78 /**79 * Timeout covers both the ACK and the wait80 * for remaining work to finish.81 *82 * This is mostly bound by the PHY disable sequence.83 * Each register check will be greater than 1us, so84 * don't bother using udelay.85 */86 87 for (i = 0; i < timeout; ++i) {88 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))89 break;90 }91 92 for (i = 0; i < timeout; ++i) {93 scratch = dmub->hw_funcs.get_gpint_response(dmub);94 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)95 break;96 }97 98 /* Force reset in case we timed out, DMCUB is likely hung. */99 }100 101 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);102 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);103 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);104 REG_WRITE(DMCUB_INBOX1_RPTR, 0);105 REG_WRITE(DMCUB_INBOX1_WPTR, 0);106 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);107 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);108 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);109 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);110 REG_WRITE(DMCUB_SCRATCH0, 0);111 112 /* Clear the GPINT command manually so we don't reset again. */113 cmd.all = 0;114 dmub->hw_funcs.set_gpint(dmub, cmd);115}116 117void dmub_dcn401_reset_release(struct dmub_srv *dmub)118{119 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);120 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);121 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);122 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);123}124 125void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,126 const struct dmub_window *cw0,127 const struct dmub_window *cw1)128{129 union dmub_addr offset;130 uint64_t fb_base, fb_offset;131 132 dmub_dcn401_get_fb_base_offset(dmub, &fb_base, &fb_offset);133 134 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);135 136 dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);137 138 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);139 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);140 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);141 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,142 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,143 DMCUB_REGION3_CW0_ENABLE, 1);144 145 dmub_dcn401_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);146 147 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);148 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);149 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);150 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,151 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,152 DMCUB_REGION3_CW1_ENABLE, 1);153 154 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,155 0x20);156}157 158void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,159 const struct dmub_window *cw0,160 const struct dmub_window *cw1)161{162 union dmub_addr offset;163 164 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);165 166 offset = cw0->offset;167 168 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);169 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);170 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);171 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,172 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,173 DMCUB_REGION3_CW0_ENABLE, 1);174 175 offset = cw1->offset;176 177 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);178 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);179 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);180 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,181 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,182 DMCUB_REGION3_CW1_ENABLE, 1);183 184 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,185 0x20);186}187 188void dmub_dcn401_setup_windows(struct dmub_srv *dmub,189 const struct dmub_window *cw2,190 const struct dmub_window *cw3,191 const struct dmub_window *cw4,192 const struct dmub_window *cw5,193 const struct dmub_window *cw6,194 const struct dmub_window *region6)195{196 union dmub_addr offset;197 198 offset = cw3->offset;199 200 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);201 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);202 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);203 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,204 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,205 DMCUB_REGION3_CW3_ENABLE, 1);206 207 offset = cw4->offset;208 209 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);210 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);211 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);212 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,213 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,214 DMCUB_REGION3_CW4_ENABLE, 1);215 216 offset = cw5->offset;217 218 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);219 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);220 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);221 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,222 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,223 DMCUB_REGION3_CW5_ENABLE, 1);224 225 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);226 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);227 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,228 DMCUB_REGION5_TOP_ADDRESS,229 cw5->region.top - cw5->region.base - 1,230 DMCUB_REGION5_ENABLE, 1);231 232 offset = cw6->offset;233 234 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);235 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);236 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);237 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,238 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,239 DMCUB_REGION3_CW6_ENABLE, 1);240 241 offset = region6->offset;242 243 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);244 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);245 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,246 DMCUB_REGION6_TOP_ADDRESS,247 region6->region.top - region6->region.base - 1,248 DMCUB_REGION6_ENABLE, 1);249}250 251void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,252 const struct dmub_region *inbox1)253{254 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);255 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);256}257 258uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)259{260 return REG_READ(DMCUB_INBOX1_WPTR);261}262 263uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)264{265 return REG_READ(DMCUB_INBOX1_RPTR);266}267 268void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)269{270 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);271}272 273void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,274 const struct dmub_region *outbox1)275{276 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);277 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);278}279 280uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)281{282 /**283 * outbox1 wptr register is accessed without locks (dal & dc)284 * and to be called only by dmub_srv_stat_get_notification()285 */286 return REG_READ(DMCUB_OUTBOX1_WPTR);287}288 289void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)290{291 /**292 * outbox1 rptr register is accessed without locks (dal & dc)293 * and to be called only by dmub_srv_stat_get_notification()294 */295 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);296}297 298bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)299{300 union dmub_fw_boot_status status;301 uint32_t is_hw_init;302 303 status.all = REG_READ(DMCUB_SCRATCH0);304 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);305 306 return is_hw_init != 0 && status.bits.dal_fw;307}308 309bool dmub_dcn401_is_supported(struct dmub_srv *dmub)310{311 uint32_t supported = 0;312 313 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);314 315 return supported;316}317 318void dmub_dcn401_set_gpint(struct dmub_srv *dmub,319 union dmub_gpint_data_register reg)320{321 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);322}323 324bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,325 union dmub_gpint_data_register reg)326{327 union dmub_gpint_data_register test;328 329 reg.bits.status = 0;330 test.all = REG_READ(DMCUB_GPINT_DATAIN1);331 332 return test.all == reg.all;333}334 335uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)336{337 return REG_READ(DMCUB_SCRATCH7);338}339 340uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)341{342 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);343 344 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);345 346 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);347 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);348 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);349 350 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);351 352 return dataout;353}354 355union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)356{357 union dmub_fw_boot_status status;358 359 status.all = REG_READ(DMCUB_SCRATCH0);360 return status;361}362 363void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)364{365 union dmub_fw_boot_options boot_options = {0};366 367 boot_options.bits.z10_disable = params->disable_z10;368 369 boot_options.bits.skip_phy_access = params->disallow_phy_access;370 371 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);372}373 374void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)375{376 union dmub_fw_boot_options boot_options;377 boot_options.all = REG_READ(DMCUB_SCRATCH14);378 boot_options.bits.skip_phy_init_panel_sequence = skip;379 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);380}381 382void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,383 const struct dmub_region *outbox0)384{385 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);386 387 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);388}389 390uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)391{392 return REG_READ(DMCUB_OUTBOX0_WPTR);393}394 395void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)396{397 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);398}399 400uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)401{402 return REG_READ(DMCUB_TIMER_CURRENT);403}404 405void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)406{407 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;408 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;409 410 if (!dmub || !diag_data)411 return;412 413 memset(diag_data, 0, sizeof(*diag_data));414 415 diag_data->dmcub_version = dmub->fw_version;416 417 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);418 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);419 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);420 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);421 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);422 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);423 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);424 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);425 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);426 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);427 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);428 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);429 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);430 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);431 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);432 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);433 diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16);434 435 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);436 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);437 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);438 439 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);440 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);441 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);442 443 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);444 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);445 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);446 447 diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);448 diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);449 diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);450 451 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);452 diag_data->is_dmcub_enabled = is_dmub_enabled;453 454 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);455 diag_data->is_dmcub_soft_reset = is_soft_reset;456 457 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);458 diag_data->is_dmcub_secure_reset = is_sec_reset;459 460 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);461 diag_data->is_traceport_en = is_traceport_enabled;462 463 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);464 diag_data->is_cw0_enabled = is_cw0_enabled;465 466 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);467 diag_data->is_cw6_enabled = is_cw6_enabled;468 469 diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);470 diag_data->timeout_info = dmub->debug;471}472void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)473{474 /* DMCUB_REGION3_TMR_AXI_SPACE values:475 * 0b011 (0x3) - FB physical address476 * 0b100 (0x4) - GPU virtual address477 *478 * Default value is 0x3 (FB Physical address for TMR). When programming479 * DMUB to be in system memory, change to 0x4. The system memory allocated480 * is accessible by both GPU and CPU, so we use GPU virtual address.481 */482 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);483}484 485void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)486{487 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);488}489 490void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)491{492 REG_WRITE(DMCUB_SCRATCH17, 0);493}494 495uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)496{497 return REG_READ(DMCUB_SCRATCH17);498}499 500void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,501 union dmub_rb_cmd *cmd)502{503 uint32_t *dwords = (uint32_t *)cmd;504 505 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");506 507 REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[0]);508 REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[1]);509 REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[2]);510 REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[3]);511 REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[4]);512 REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[5]);513 REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[6]);514 REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[7]);515 REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[8]);516 REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[9]);517 REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[10]);518 REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[11]);519 REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[12]);520 REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[13]);521 REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[14]);522 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY523 * interrupt.524 */525 REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[15]);526}527 528uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)529{530 uint32_t status;531 532 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);533 return status;534}535 536void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,537 union dmub_rb_cmd *cmd)538{539 uint32_t *dwords = (uint32_t *)cmd;540 541 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");542 543 dwords[0] = REG_READ(DMCUB_REG_INBOX0_MSG0);544 dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG1);545 dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG2);546 dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG3);547 dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG4);548 dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG5);549 dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG6);550 dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG7);551 dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG8);552 dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG9);553 dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG10);554 dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG11);555 dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG12);556 dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG13);557 dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG14);558 dwords[15] = REG_READ(DMCUB_REG_INBOX0_RSP);559}560 561void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)562{563 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);564 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);565}566 567void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)568{569 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);570 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);571}572 573void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)574{575 *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);576}577 578void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)579{580 REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);581}582 583uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)584{585 uint32_t status;586 587 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);588 return status;589}590 591void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)592{593 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);594}595 596void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)597{598 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);599}600 601uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)602{603 uint32_t status;604 605 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);606 return status;607}608