443 lines · c
1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__27#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__28 29#include "grph_object_defs.h"30 31/*32 * #####################################################33 * #####################################################34 *35 * These defines shared between asic_control/bios_parser and other36 * DAL components37 *38 * #####################################################39 * #####################################################40 */41 42enum display_output_bit_depth {43 PANEL_UNDEFINE = 0,44 PANEL_6BIT_COLOR = 1,45 PANEL_8BIT_COLOR = 2,46 PANEL_10BIT_COLOR = 3,47 PANEL_12BIT_COLOR = 4,48 PANEL_16BIT_COLOR = 5,49};50 51 52/* Device type as abstracted by ATOM BIOS */53enum dal_device_type {54 DEVICE_TYPE_UNKNOWN = 0,55 DEVICE_TYPE_LCD,56 DEVICE_TYPE_CRT,57 DEVICE_TYPE_DFP,58 DEVICE_TYPE_CV,59 DEVICE_TYPE_TV,60 DEVICE_TYPE_CF,61 DEVICE_TYPE_WIRELESS62};63 64/* Device ID as abstracted by ATOM BIOS */65struct device_id {66 enum dal_device_type device_type:16;67 uint32_t enum_id:16; /* 1 based enum */68 uint16_t raw_device_tag;69};70 71struct graphics_object_i2c_info {72 struct gpio_info {73 uint32_t clk_mask_register_index;74 uint32_t clk_en_register_index;75 uint32_t clk_y_register_index;76 uint32_t clk_a_register_index;77 uint32_t data_mask_register_index;78 uint32_t data_en_register_index;79 uint32_t data_y_register_index;80 uint32_t data_a_register_index;81 82 uint32_t clk_mask_shift;83 uint32_t clk_en_shift;84 uint32_t clk_y_shift;85 uint32_t clk_a_shift;86 uint32_t data_mask_shift;87 uint32_t data_en_shift;88 uint32_t data_y_shift;89 uint32_t data_a_shift;90 } gpio_info;91 92 bool i2c_hw_assist;93 uint32_t i2c_line;94 uint32_t i2c_engine_id;95 uint32_t i2c_slave_address;96};97 98struct graphics_object_hpd_info {99 uint8_t hpd_int_gpio_uid;100 uint8_t hpd_active;101};102 103struct connector_device_tag_info {104 uint32_t acpi_device;105 struct device_id dev_id;106};107 108struct device_timing {109 struct misc_info {110 uint32_t HORIZONTAL_CUT_OFF:1;111 /* 0=Active High, 1=Active Low */112 uint32_t H_SYNC_POLARITY:1;113 /* 0=Active High, 1=Active Low */114 uint32_t V_SYNC_POLARITY:1;115 uint32_t VERTICAL_CUT_OFF:1;116 uint32_t H_REPLICATION_BY2:1;117 uint32_t V_REPLICATION_BY2:1;118 uint32_t COMPOSITE_SYNC:1;119 uint32_t INTERLACE:1;120 uint32_t DOUBLE_CLOCK:1;121 uint32_t RGB888:1;122 uint32_t GREY_LEVEL:2;123 uint32_t SPATIAL:1;124 uint32_t TEMPORAL:1;125 uint32_t API_ENABLED:1;126 } misc_info;127 128 uint32_t pixel_clk; /* in KHz */129 uint32_t horizontal_addressable;130 uint32_t horizontal_blanking_time;131 uint32_t vertical_addressable;132 uint32_t vertical_blanking_time;133 uint32_t horizontal_sync_offset;134 uint32_t horizontal_sync_width;135 uint32_t vertical_sync_offset;136 uint32_t vertical_sync_width;137 uint32_t horizontal_border;138 uint32_t vertical_border;139};140 141struct supported_refresh_rate {142 uint32_t REFRESH_RATE_30HZ:1;143 uint32_t REFRESH_RATE_40HZ:1;144 uint32_t REFRESH_RATE_48HZ:1;145 uint32_t REFRESH_RATE_50HZ:1;146 uint32_t REFRESH_RATE_60HZ:1;147};148 149struct embedded_panel_info {150 struct device_timing lcd_timing;151 uint32_t ss_id;152 struct supported_refresh_rate supported_rr;153 uint32_t drr_enabled;154 uint32_t min_drr_refresh_rate;155 bool realtek_eDPToLVDS;156};157 158struct dc_firmware_info {159 struct pll_info {160 uint32_t crystal_frequency; /* in KHz */161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */165 } pll_info;166 167 struct firmware_feature {168 uint32_t memory_clk_ss_percentage;169 uint32_t engine_clk_ss_percentage;170 } feature;171 172 uint32_t default_display_engine_pll_frequency; /* in KHz */173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */174 uint32_t smu_gpu_pll_output_freq; /* in KHz */175 uint8_t min_allowed_bl_level;176 uint8_t remote_display_config;177 uint32_t default_memory_clk; /* in KHz */178 uint32_t default_engine_clk; /* in KHz */179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */181 bool oem_i2c_present;182 uint8_t oem_i2c_obj_id;183 184};185 186struct dc_vram_info {187 unsigned int num_chans;188 unsigned int dram_channel_width_bytes;189};190 191struct step_and_delay_info {192 uint32_t step;193 uint32_t delay;194 uint32_t recommended_ref_div;195};196 197struct spread_spectrum_info {198 struct spread_spectrum_type {199 bool CENTER_MODE:1;200 bool EXTERNAL:1;201 bool STEP_AND_DELAY_INFO:1;202 } type;203 204 /* in unit of 0.01% (spreadPercentageDivider = 100),205 otherwise in 0.001% units (spreadPercentageDivider = 1000); */206 uint32_t spread_spectrum_percentage;207 uint32_t spread_percentage_divider; /* 100 or 1000 */208 uint32_t spread_spectrum_range; /* modulation freq (HZ)*/209 210 union {211 struct step_and_delay_info step_and_delay_info;212 /* For mem/engine/uvd, Clock Out frequence (VCO ),213 in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,214 for DP, it is link clock ( 270000 or 162000 ) */215 uint32_t target_clock_range; /* in KHz */216 };217 218};219 220struct graphics_object_encoder_cap_info {221 uint32_t dp_hbr2_cap:1;222 uint32_t dp_hbr2_validated:1;223 /*224 * TODO: added MST and HDMI 6G capable flags225 */226 uint32_t reserved:15;227};228 229struct din_connector_info {230 uint32_t gpio_id;231 bool gpio_tv_active_state;232};233 234/* Invalid channel mapping */235enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };236 237/**238 * DDI PHY channel mapping reflecting XBAR setting239 */240union ddi_channel_mapping {241 struct mapping {242 uint8_t lane0:2; /* Mapping for lane 0 */243 uint8_t lane1:2; /* Mapping for lane 1 */244 uint8_t lane2:2; /* Mapping for lane 2 */245 uint8_t lane3:2; /* Mapping for lane 3 */246 } mapping;247 uint8_t raw;248};249 250/**251* Transmitter output configuration description252*/253struct transmitter_configuration_info {254 /* DDI PHY ID for the transmitter */255 enum transmitter transmitter_phy_id;256 /* DDI PHY channel mapping reflecting crossbar setting */257 union ddi_channel_mapping output_channel_mapping;258};259 260struct transmitter_configuration {261 /* Configuration for the primary transmitter */262 struct transmitter_configuration_info primary_transmitter_config;263 /* Secondary transmitter configuration for Dual-link DVI */264 struct transmitter_configuration_info secondary_transmitter_config;265};266 267/* These size should be sufficient to store info coming from BIOS */268#define NUMBER_OF_UCHAR_FOR_GUID 16269#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7270#define NUMBER_OF_CSR_M3_ARB 10271#define NUMBER_OF_DISP_CLK_VOLTAGE 4272#define NUMBER_OF_AVAILABLE_SCLK 5273 274struct i2c_reg_info {275 unsigned char i2c_reg_index;276 unsigned char i2c_reg_val;277};278 279struct ext_hdmi_settings {280 unsigned char slv_addr;281 unsigned char reg_num;282 struct i2c_reg_info reg_settings[9];283 unsigned char reg_num_6g;284 struct i2c_reg_info reg_settings_6g[3];285};286 287struct edp_info {288 uint16_t edp_backlight_pwm_hz;289 uint16_t edp_ss_percentage;290 uint16_t edp_ss_rate_10hz;291 uint8_t edp_pwr_on_off_delay;292 uint8_t edp_pwr_on_vary_bl_to_blon;293 uint8_t edp_pwr_down_bloff_to_vary_bloff;294 uint8_t edp_panel_bpc;295 uint8_t edp_bootup_bl_level;296};297 298/* V6 */299struct integrated_info {300 struct clock_voltage_caps {301 /* The Voltage Index indicated by FUSE, same voltage index302 shared with SCLK DPM fuse table */303 uint32_t voltage_index;304 /* Maximum clock supported with specified voltage index */305 uint32_t max_supported_clk; /* in KHz */306 } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];307 308 struct display_connection_info {309 struct external_display_path {310 /* A bit vector to show what devices are supported */311 uint32_t device_tag;312 /* 16bit device ACPI id. */313 uint32_t device_acpi_enum;314 /* A physical connector for displays to plug in,315 using object connector definitions */316 struct graphics_object_id device_connector_id;317 /* An index into external AUX/DDC channel LUT */318 uint8_t ext_aux_ddc_lut_index;319 /* An index into external HPD pin LUT */320 uint8_t ext_hpd_pin_lut_index;321 /* external encoder object id */322 struct graphics_object_id ext_encoder_obj_id;323 /* XBAR mapping of the PHY channels */324 union ddi_channel_mapping channel_mapping;325 326 unsigned short caps;327 } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];328 329 uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];330 uint8_t checksum;331 uint8_t fixdpvoltageswing;332 } ext_disp_conn_info; /* exiting long long time */333 334 struct available_s_clk_list {335 /* Maximum clock supported with specified voltage index */336 uint32_t supported_s_clk; /* in KHz */337 /* The Voltage Index indicated by FUSE for specified SCLK */338 uint32_t voltage_index;339 /* The Voltage ID indicated by FUSE for specified SCLK */340 uint32_t voltage_id;341 } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];342 343 uint8_t memory_type;344 uint8_t ma_channel_number;345 uint32_t boot_up_engine_clock; /* in KHz */346 uint32_t dentist_vco_freq; /* in KHz */347 uint32_t boot_up_uma_clock; /* in KHz */348 uint32_t boot_up_req_display_vector;349 uint32_t other_display_misc;350 uint32_t gpu_cap_info;351 uint32_t sb_mmio_base_addr;352 uint32_t system_config;353 uint32_t cpu_cap_info;354 uint32_t max_nb_voltage;355 uint32_t min_nb_voltage;356 uint32_t boot_up_nb_voltage;357 uint32_t ext_disp_conn_info_offset;358 uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];359 uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];360 uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];361 uint32_t gmc_restore_reset_time;362 uint32_t minimum_n_clk;363 uint32_t idle_n_clk;364 uint32_t ddr_dll_power_up_time;365 uint32_t ddr_pll_power_up_time;366 /* start for V6 */367 uint32_t pcie_clk_ss_type;368 uint32_t lvds_ss_percentage;369 uint32_t lvds_sspread_rate_in_10hz;370 uint32_t hdmi_ss_percentage;371 uint32_t hdmi_sspread_rate_in_10hz;372 uint32_t dvi_ss_percentage;373 uint32_t dvi_sspread_rate_in_10_hz;374 uint32_t sclk_dpm_boost_margin;375 uint32_t sclk_dpm_throttle_margin;376 uint32_t sclk_dpm_tdp_limit_pg;377 uint32_t sclk_dpm_tdp_limit_boost;378 uint32_t boost_engine_clock;379 uint32_t boost_vid_2bit;380 uint32_t enable_boost;381 uint32_t gnb_tdp_limit;382 /* Start from V7 */383 uint32_t max_lvds_pclk_freq_in_single_link;384 uint32_t lvds_misc;385 uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;386 uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;387 uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;388 uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;389 uint32_t lvds_off_to_on_delay_in_4ms;390 uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;391 uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;392 uint32_t lvds_reserved1;393 uint32_t lvds_bit_depth_control_val;394 //Start from V9395 unsigned char dp0_ext_hdmi_slv_addr;396 unsigned char dp0_ext_hdmi_reg_num;397 struct i2c_reg_info dp0_ext_hdmi_reg_settings[9];398 unsigned char dp0_ext_hdmi_6g_reg_num;399 struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3];400 unsigned char dp1_ext_hdmi_slv_addr;401 unsigned char dp1_ext_hdmi_reg_num;402 struct i2c_reg_info dp1_ext_hdmi_reg_settings[9];403 unsigned char dp1_ext_hdmi_6g_reg_num;404 struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3];405 unsigned char dp2_ext_hdmi_slv_addr;406 unsigned char dp2_ext_hdmi_reg_num;407 struct i2c_reg_info dp2_ext_hdmi_reg_settings[9];408 unsigned char dp2_ext_hdmi_6g_reg_num;409 struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3];410 unsigned char dp3_ext_hdmi_slv_addr;411 unsigned char dp3_ext_hdmi_reg_num;412 struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];413 unsigned char dp3_ext_hdmi_6g_reg_num;414 struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];415 /* V11 */416 uint32_t dp_ss_control;417 /* V2.1 */418 struct edp_info edp1_info;419 struct edp_info edp2_info;420 uint32_t gpuclk_ss_percentage;421 uint32_t gpuclk_ss_type;422};423 424/*425 * DFS-bypass flag426 */427/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */428enum {429 DFS_BYPASS_ENABLE = 0x10430};431 432enum {433 INVALID_BACKLIGHT = -1434};435 436struct panel_backlight_boundaries {437 uint32_t min_signal_level;438 uint32_t max_signal_level;439};440 441 442#endif443