1739 lines · c
1/*2 * Copyright (C) 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included12 * in all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.20 */21#ifndef _aldebaran_ip_offset_HEADER22#define _aldebaran_ip_offset_HEADER23 24#define MAX_INSTANCE 725#define MAX_SEGMENT 626 27struct IP_BASE_INSTANCE {28 unsigned int segment[MAX_SEGMENT];29};30 31struct IP_BASE {32 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];33} __maybe_unused;34 35static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },36 { { 0, 0, 0, 0, 0, 0 } },37 { { 0, 0, 0, 0, 0, 0 } },38 { { 0, 0, 0, 0, 0, 0 } },39 { { 0, 0, 0, 0, 0, 0 } },40 { { 0, 0, 0, 0, 0, 0 } },41 { { 0, 0, 0, 0, 0, 0 } } } };42static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },43 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },44 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },45 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },46 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },47 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },48 { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };49static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },50 { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },51 { { 0x00000280, 0x02416000, 0, 0, 0, 0 } },52 { { 0, 0, 0, 0, 0, 0 } },53 { { 0, 0, 0, 0, 0, 0 } },54 { { 0, 0, 0, 0, 0, 0 } },55 { { 0, 0, 0, 0, 0, 0 } } } };56static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } },57 { { 0, 0, 0, 0, 0, 0 } },58 { { 0, 0, 0, 0, 0, 0 } },59 { { 0, 0, 0, 0, 0, 0 } },60 { { 0, 0, 0, 0, 0, 0 } },61 { { 0, 0, 0, 0, 0, 0 } },62 { { 0, 0, 0, 0, 0, 0 } } } };63static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },64 { { 0, 0, 0, 0, 0, 0 } },65 { { 0, 0, 0, 0, 0, 0 } },66 { { 0, 0, 0, 0, 0, 0 } },67 { { 0, 0, 0, 0, 0, 0 } },68 { { 0, 0, 0, 0, 0, 0 } },69 { { 0, 0, 0, 0, 0, 0 } } } };70static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } },71 { { 0, 0, 0, 0, 0, 0 } },72 { { 0, 0, 0, 0, 0, 0 } },73 { { 0, 0, 0, 0, 0, 0 } },74 { { 0, 0, 0, 0, 0, 0 } },75 { { 0, 0, 0, 0, 0, 0 } },76 { { 0, 0, 0, 0, 0, 0 } } } };77static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },78 { { 0, 0, 0, 0, 0, 0 } },79 { { 0, 0, 0, 0, 0, 0 } },80 { { 0, 0, 0, 0, 0, 0 } },81 { { 0, 0, 0, 0, 0, 0 } },82 { { 0, 0, 0, 0, 0, 0 } },83 { { 0, 0, 0, 0, 0, 0 } } } };84static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } },85 { { 0, 0, 0, 0, 0, 0 } },86 { { 0, 0, 0, 0, 0, 0 } },87 { { 0, 0, 0, 0, 0, 0 } },88 { { 0, 0, 0, 0, 0, 0 } },89 { { 0, 0, 0, 0, 0, 0 } },90 { { 0, 0, 0, 0, 0, 0 } } } };91static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } },92 { { 0, 0, 0, 0, 0, 0 } },93 { { 0, 0, 0, 0, 0, 0 } },94 { { 0, 0, 0, 0, 0, 0 } },95 { { 0, 0, 0, 0, 0, 0 } },96 { { 0, 0, 0, 0, 0, 0 } },97 { { 0, 0, 0, 0, 0, 0 } } } };98static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },99 { { 0, 0, 0, 0, 0, 0 } },100 { { 0, 0, 0, 0, 0, 0 } },101 { { 0, 0, 0, 0, 0, 0 } },102 { { 0, 0, 0, 0, 0, 0 } },103 { { 0, 0, 0, 0, 0, 0 } },104 { { 0, 0, 0, 0, 0, 0 } } } };105static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } },106 { { 0, 0, 0, 0, 0, 0 } },107 { { 0, 0, 0, 0, 0, 0 } },108 { { 0, 0, 0, 0, 0, 0 } },109 { { 0, 0, 0, 0, 0, 0 } },110 { { 0, 0, 0, 0, 0, 0 } },111 { { 0, 0, 0, 0, 0, 0 } } } };112static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } },113 { { 0, 0, 0, 0, 0, 0 } },114 { { 0, 0, 0, 0, 0, 0 } },115 { { 0, 0, 0, 0, 0, 0 } },116 { { 0, 0, 0, 0, 0, 0 } },117 { { 0, 0, 0, 0, 0, 0 } },118 { { 0, 0, 0, 0, 0, 0 } } } };119static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } },120 { { 0, 0, 0, 0, 0, 0 } },121 { { 0, 0, 0, 0, 0, 0 } },122 { { 0, 0, 0, 0, 0, 0 } },123 { { 0, 0, 0, 0, 0, 0 } },124 { { 0, 0, 0, 0, 0, 0 } },125 { { 0, 0, 0, 0, 0, 0 } } } };126static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },127 { { 0, 0, 0, 0, 0, 0 } },128 { { 0, 0, 0, 0, 0, 0 } },129 { { 0, 0, 0, 0, 0, 0 } },130 { { 0, 0, 0, 0, 0, 0 } },131 { { 0, 0, 0, 0, 0, 0 } },132 { { 0, 0, 0, 0, 0, 0 } } } };133static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },134 { { 0, 0, 0, 0, 0, 0 } },135 { { 0, 0, 0, 0, 0, 0 } },136 { { 0, 0, 0, 0, 0, 0 } },137 { { 0, 0, 0, 0, 0, 0 } },138 { { 0, 0, 0, 0, 0, 0 } },139 { { 0, 0, 0, 0, 0, 0 } } } };140static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },141 { { 0, 0, 0, 0, 0, 0 } },142 { { 0, 0, 0, 0, 0, 0 } },143 { { 0, 0, 0, 0, 0, 0 } },144 { { 0, 0, 0, 0, 0, 0 } },145 { { 0, 0, 0, 0, 0, 0 } },146 { { 0, 0, 0, 0, 0, 0 } } } };147static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },148 { { 0, 0, 0, 0, 0, 0 } },149 { { 0, 0, 0, 0, 0, 0 } },150 { { 0, 0, 0, 0, 0, 0 } },151 { { 0, 0, 0, 0, 0, 0 } },152 { { 0, 0, 0, 0, 0, 0 } },153 { { 0, 0, 0, 0, 0, 0 } } } };154static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },155 { { 0, 0, 0, 0, 0, 0 } },156 { { 0, 0, 0, 0, 0, 0 } },157 { { 0, 0, 0, 0, 0, 0 } },158 { { 0, 0, 0, 0, 0, 0 } },159 { { 0, 0, 0, 0, 0, 0 } },160 { { 0, 0, 0, 0, 0, 0 } } } };161static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },162 { { 0, 0, 0, 0, 0, 0 } },163 { { 0, 0, 0, 0, 0, 0 } },164 { { 0, 0, 0, 0, 0, 0 } },165 { { 0, 0, 0, 0, 0, 0 } },166 { { 0, 0, 0, 0, 0, 0 } },167 { { 0, 0, 0, 0, 0, 0 } } } };168static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },169 { { 0, 0, 0, 0, 0, 0 } },170 { { 0, 0, 0, 0, 0, 0 } },171 { { 0, 0, 0, 0, 0, 0 } },172 { { 0, 0, 0, 0, 0, 0 } },173 { { 0, 0, 0, 0, 0, 0 } },174 { { 0, 0, 0, 0, 0, 0 } } } };175static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },176 { { 0, 0, 0, 0, 0, 0 } },177 { { 0, 0, 0, 0, 0, 0 } },178 { { 0, 0, 0, 0, 0, 0 } },179 { { 0, 0, 0, 0, 0, 0 } },180 { { 0, 0, 0, 0, 0, 0 } },181 { { 0, 0, 0, 0, 0, 0 } } } };182static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },183 { { 0, 0, 0, 0, 0, 0 } },184 { { 0, 0, 0, 0, 0, 0 } },185 { { 0, 0, 0, 0, 0, 0 } },186 { { 0, 0, 0, 0, 0, 0 } },187 { { 0, 0, 0, 0, 0, 0 } },188 { { 0, 0, 0, 0, 0, 0 } } } };189static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },190 { { 0, 0, 0, 0, 0, 0 } },191 { { 0, 0, 0, 0, 0, 0 } },192 { { 0, 0, 0, 0, 0, 0 } },193 { { 0, 0, 0, 0, 0, 0 } },194 { { 0, 0, 0, 0, 0, 0 } },195 { { 0, 0, 0, 0, 0, 0 } } } };196static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },197 { { 0, 0, 0, 0, 0, 0 } },198 { { 0, 0, 0, 0, 0, 0 } },199 { { 0, 0, 0, 0, 0, 0 } },200 { { 0, 0, 0, 0, 0, 0 } },201 { { 0, 0, 0, 0, 0, 0 } },202 { { 0, 0, 0, 0, 0, 0 } } } };203static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } },204 { { 0, 0, 0, 0, 0, 0 } },205 { { 0, 0, 0, 0, 0, 0 } },206 { { 0, 0, 0, 0, 0, 0 } },207 { { 0, 0, 0, 0, 0, 0 } },208 { { 0, 0, 0, 0, 0, 0 } },209 { { 0, 0, 0, 0, 0, 0 } } } };210static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },211 { { 0, 0, 0, 0, 0, 0 } },212 { { 0, 0, 0, 0, 0, 0 } },213 { { 0, 0, 0, 0, 0, 0 } },214 { { 0, 0, 0, 0, 0, 0 } },215 { { 0, 0, 0, 0, 0, 0 } },216 { { 0, 0, 0, 0, 0, 0 } } } };217static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } },218 { { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } },219 { { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } },220 { { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } },221 { { 0, 0, 0, 0, 0, 0 } },222 { { 0, 0, 0, 0, 0, 0 } },223 { { 0, 0, 0, 0, 0, 0 } } } };224static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },225 { { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } },226 { { 0, 0, 0, 0, 0, 0 } },227 { { 0, 0, 0, 0, 0, 0 } },228 { { 0, 0, 0, 0, 0, 0 } },229 { { 0, 0, 0, 0, 0, 0 } },230 { { 0, 0, 0, 0, 0, 0 } } } };231static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } },232 { { 0, 0, 0, 0, 0, 0 } },233 { { 0, 0, 0, 0, 0, 0 } },234 { { 0, 0, 0, 0, 0, 0 } },235 { { 0, 0, 0, 0, 0, 0 } },236 { { 0, 0, 0, 0, 0, 0 } },237 { { 0, 0, 0, 0, 0, 0 } } } };238static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } },239 { { 0, 0, 0, 0, 0, 0 } },240 { { 0, 0, 0, 0, 0, 0 } },241 { { 0, 0, 0, 0, 0, 0 } },242 { { 0, 0, 0, 0, 0, 0 } },243 { { 0, 0, 0, 0, 0, 0 } },244 { { 0, 0, 0, 0, 0, 0 } } } };245static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } },246 { { 0, 0, 0, 0, 0, 0 } },247 { { 0, 0, 0, 0, 0, 0 } },248 { { 0, 0, 0, 0, 0, 0 } },249 { { 0, 0, 0, 0, 0, 0 } },250 { { 0, 0, 0, 0, 0, 0 } },251 { { 0, 0, 0, 0, 0, 0 } } } };252static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } },253 { { 0, 0, 0, 0, 0, 0 } },254 { { 0, 0, 0, 0, 0, 0 } },255 { { 0, 0, 0, 0, 0, 0 } },256 { { 0, 0, 0, 0, 0, 0 } },257 { { 0, 0, 0, 0, 0, 0 } },258 { { 0, 0, 0, 0, 0, 0 } } } };259static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } },260 { { 0x04740000, 0x04A00000, 0, 0, 0, 0 } },261 { { 0x04780000, 0x04A40000, 0, 0, 0, 0 } },262 { { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } },263 { { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } },264 { { 0x04840000, 0x04B00000, 0, 0, 0, 0 } },265 { { 0, 0, 0, 0, 0, 0 } } } };266 267 268#define ATHUB_BASE__INST0_SEG0 0x00000C20269#define ATHUB_BASE__INST0_SEG1 0x02408C00270#define ATHUB_BASE__INST0_SEG2 0271#define ATHUB_BASE__INST0_SEG3 0272#define ATHUB_BASE__INST0_SEG4 0273#define ATHUB_BASE__INST0_SEG5 0274 275#define ATHUB_BASE__INST1_SEG0 0276#define ATHUB_BASE__INST1_SEG1 0277#define ATHUB_BASE__INST1_SEG2 0278#define ATHUB_BASE__INST1_SEG3 0279#define ATHUB_BASE__INST1_SEG4 0280#define ATHUB_BASE__INST1_SEG5 0281 282#define ATHUB_BASE__INST2_SEG0 0283#define ATHUB_BASE__INST2_SEG1 0284#define ATHUB_BASE__INST2_SEG2 0285#define ATHUB_BASE__INST2_SEG3 0286#define ATHUB_BASE__INST2_SEG4 0287#define ATHUB_BASE__INST2_SEG5 0288 289#define ATHUB_BASE__INST3_SEG0 0290#define ATHUB_BASE__INST3_SEG1 0291#define ATHUB_BASE__INST3_SEG2 0292#define ATHUB_BASE__INST3_SEG3 0293#define ATHUB_BASE__INST3_SEG4 0294#define ATHUB_BASE__INST3_SEG5 0295 296#define ATHUB_BASE__INST4_SEG0 0297#define ATHUB_BASE__INST4_SEG1 0298#define ATHUB_BASE__INST4_SEG2 0299#define ATHUB_BASE__INST4_SEG3 0300#define ATHUB_BASE__INST4_SEG4 0301#define ATHUB_BASE__INST4_SEG5 0302 303#define ATHUB_BASE__INST5_SEG0 0304#define ATHUB_BASE__INST5_SEG1 0305#define ATHUB_BASE__INST5_SEG2 0306#define ATHUB_BASE__INST5_SEG3 0307#define ATHUB_BASE__INST5_SEG4 0308#define ATHUB_BASE__INST5_SEG5 0309 310#define ATHUB_BASE__INST6_SEG0 0311#define ATHUB_BASE__INST6_SEG1 0312#define ATHUB_BASE__INST6_SEG2 0313#define ATHUB_BASE__INST6_SEG3 0314#define ATHUB_BASE__INST6_SEG4 0315#define ATHUB_BASE__INST6_SEG5 0316 317#define CLK_BASE__INST0_SEG0 0x00016C00318#define CLK_BASE__INST0_SEG1 0x02401800319#define CLK_BASE__INST0_SEG2 0320#define CLK_BASE__INST0_SEG3 0321#define CLK_BASE__INST0_SEG4 0322#define CLK_BASE__INST0_SEG5 0323 324#define CLK_BASE__INST1_SEG0 0x00016E00325#define CLK_BASE__INST1_SEG1 0x02401C00326#define CLK_BASE__INST1_SEG2 0327#define CLK_BASE__INST1_SEG3 0328#define CLK_BASE__INST1_SEG4 0329#define CLK_BASE__INST1_SEG5 0330 331#define CLK_BASE__INST2_SEG0 0x00017000332#define CLK_BASE__INST2_SEG1 0x02402000333#define CLK_BASE__INST2_SEG2 0334#define CLK_BASE__INST2_SEG3 0335#define CLK_BASE__INST2_SEG4 0336#define CLK_BASE__INST2_SEG5 0337 338#define CLK_BASE__INST3_SEG0 0x00017200339#define CLK_BASE__INST3_SEG1 0x02402400340#define CLK_BASE__INST3_SEG2 0341#define CLK_BASE__INST3_SEG3 0342#define CLK_BASE__INST3_SEG4 0343#define CLK_BASE__INST3_SEG5 0344 345#define CLK_BASE__INST4_SEG0 0x0001B000346#define CLK_BASE__INST4_SEG1 0x0242D800347#define CLK_BASE__INST4_SEG2 0348#define CLK_BASE__INST4_SEG3 0349#define CLK_BASE__INST4_SEG4 0350#define CLK_BASE__INST4_SEG5 0351 352#define CLK_BASE__INST5_SEG0 0x0001B200353#define CLK_BASE__INST5_SEG1 0x0242DC00354#define CLK_BASE__INST5_SEG2 0355#define CLK_BASE__INST5_SEG3 0356#define CLK_BASE__INST5_SEG4 0357#define CLK_BASE__INST5_SEG5 0358 359#define CLK_BASE__INST6_SEG0 0x00017E00360#define CLK_BASE__INST6_SEG1 0x0240BC00361#define CLK_BASE__INST6_SEG2 0362#define CLK_BASE__INST6_SEG3 0363#define CLK_BASE__INST6_SEG4 0364#define CLK_BASE__INST6_SEG5 0365 366#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0367#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400368#define DBGU_IO0_BASE__INST0_SEG2 0369#define DBGU_IO0_BASE__INST0_SEG3 0370#define DBGU_IO0_BASE__INST0_SEG4 0371#define DBGU_IO0_BASE__INST0_SEG5 0372 373#define DBGU_IO0_BASE__INST1_SEG0 0x00000260374#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00375#define DBGU_IO0_BASE__INST1_SEG2 0376#define DBGU_IO0_BASE__INST1_SEG3 0377#define DBGU_IO0_BASE__INST1_SEG4 0378#define DBGU_IO0_BASE__INST1_SEG5 0379 380#define DBGU_IO0_BASE__INST2_SEG0 0x00000280381#define DBGU_IO0_BASE__INST2_SEG1 0x02416000382#define DBGU_IO0_BASE__INST2_SEG2 0383#define DBGU_IO0_BASE__INST2_SEG3 0384#define DBGU_IO0_BASE__INST2_SEG4 0385#define DBGU_IO0_BASE__INST2_SEG5 0386 387#define DBGU_IO0_BASE__INST3_SEG0 0388#define DBGU_IO0_BASE__INST3_SEG1 0389#define DBGU_IO0_BASE__INST3_SEG2 0390#define DBGU_IO0_BASE__INST3_SEG3 0391#define DBGU_IO0_BASE__INST3_SEG4 0392#define DBGU_IO0_BASE__INST3_SEG5 0393 394#define DBGU_IO0_BASE__INST4_SEG0 0395#define DBGU_IO0_BASE__INST4_SEG1 0396#define DBGU_IO0_BASE__INST4_SEG2 0397#define DBGU_IO0_BASE__INST4_SEG3 0398#define DBGU_IO0_BASE__INST4_SEG4 0399#define DBGU_IO0_BASE__INST4_SEG5 0400 401#define DBGU_IO0_BASE__INST5_SEG0 0402#define DBGU_IO0_BASE__INST5_SEG1 0403#define DBGU_IO0_BASE__INST5_SEG2 0404#define DBGU_IO0_BASE__INST5_SEG3 0405#define DBGU_IO0_BASE__INST5_SEG4 0406#define DBGU_IO0_BASE__INST5_SEG5 0407 408#define DBGU_IO0_BASE__INST6_SEG0 0409#define DBGU_IO0_BASE__INST6_SEG1 0410#define DBGU_IO0_BASE__INST6_SEG2 0411#define DBGU_IO0_BASE__INST6_SEG3 0412#define DBGU_IO0_BASE__INST6_SEG4 0413#define DBGU_IO0_BASE__INST6_SEG5 0414 415#define DF_BASE__INST0_SEG0 0x00007000416#define DF_BASE__INST0_SEG1 0x0240B800417#define DF_BASE__INST0_SEG2 0x07C00000418#define DF_BASE__INST0_SEG3 0419#define DF_BASE__INST0_SEG4 0420#define DF_BASE__INST0_SEG5 0421 422#define DF_BASE__INST1_SEG0 0423#define DF_BASE__INST1_SEG1 0424#define DF_BASE__INST1_SEG2 0425#define DF_BASE__INST1_SEG3 0426#define DF_BASE__INST1_SEG4 0427#define DF_BASE__INST1_SEG5 0428 429#define DF_BASE__INST2_SEG0 0430#define DF_BASE__INST2_SEG1 0431#define DF_BASE__INST2_SEG2 0432#define DF_BASE__INST2_SEG3 0433#define DF_BASE__INST2_SEG4 0434#define DF_BASE__INST2_SEG5 0435 436#define DF_BASE__INST3_SEG0 0437#define DF_BASE__INST3_SEG1 0438#define DF_BASE__INST3_SEG2 0439#define DF_BASE__INST3_SEG3 0440#define DF_BASE__INST3_SEG4 0441#define DF_BASE__INST3_SEG5 0442 443#define DF_BASE__INST4_SEG0 0444#define DF_BASE__INST4_SEG1 0445#define DF_BASE__INST4_SEG2 0446#define DF_BASE__INST4_SEG3 0447#define DF_BASE__INST4_SEG4 0448#define DF_BASE__INST4_SEG5 0449 450#define DF_BASE__INST5_SEG0 0451#define DF_BASE__INST5_SEG1 0452#define DF_BASE__INST5_SEG2 0453#define DF_BASE__INST5_SEG3 0454#define DF_BASE__INST5_SEG4 0455#define DF_BASE__INST5_SEG5 0456 457#define DF_BASE__INST6_SEG0 0458#define DF_BASE__INST6_SEG1 0459#define DF_BASE__INST6_SEG2 0460#define DF_BASE__INST6_SEG3 0461#define DF_BASE__INST6_SEG4 0462#define DF_BASE__INST6_SEG5 0463 464#define FUSE_BASE__INST0_SEG0 0x00017400465#define FUSE_BASE__INST0_SEG1 0x02401400466#define FUSE_BASE__INST0_SEG2 0467#define FUSE_BASE__INST0_SEG3 0468#define FUSE_BASE__INST0_SEG4 0469#define FUSE_BASE__INST0_SEG5 0470 471#define FUSE_BASE__INST1_SEG0 0472#define FUSE_BASE__INST1_SEG1 0473#define FUSE_BASE__INST1_SEG2 0474#define FUSE_BASE__INST1_SEG3 0475#define FUSE_BASE__INST1_SEG4 0476#define FUSE_BASE__INST1_SEG5 0477 478#define FUSE_BASE__INST2_SEG0 0479#define FUSE_BASE__INST2_SEG1 0480#define FUSE_BASE__INST2_SEG2 0481#define FUSE_BASE__INST2_SEG3 0482#define FUSE_BASE__INST2_SEG4 0483#define FUSE_BASE__INST2_SEG5 0484 485#define FUSE_BASE__INST3_SEG0 0486#define FUSE_BASE__INST3_SEG1 0487#define FUSE_BASE__INST3_SEG2 0488#define FUSE_BASE__INST3_SEG3 0489#define FUSE_BASE__INST3_SEG4 0490#define FUSE_BASE__INST3_SEG5 0491 492#define FUSE_BASE__INST4_SEG0 0493#define FUSE_BASE__INST4_SEG1 0494#define FUSE_BASE__INST4_SEG2 0495#define FUSE_BASE__INST4_SEG3 0496#define FUSE_BASE__INST4_SEG4 0497#define FUSE_BASE__INST4_SEG5 0498 499#define FUSE_BASE__INST5_SEG0 0500#define FUSE_BASE__INST5_SEG1 0501#define FUSE_BASE__INST5_SEG2 0502#define FUSE_BASE__INST5_SEG3 0503#define FUSE_BASE__INST5_SEG4 0504#define FUSE_BASE__INST5_SEG5 0505 506#define FUSE_BASE__INST6_SEG0 0507#define FUSE_BASE__INST6_SEG1 0508#define FUSE_BASE__INST6_SEG2 0509#define FUSE_BASE__INST6_SEG3 0510#define FUSE_BASE__INST6_SEG4 0511#define FUSE_BASE__INST6_SEG5 0512 513#define GC_BASE__INST0_SEG0 0x00002000514#define GC_BASE__INST0_SEG1 0x0000A000515#define GC_BASE__INST0_SEG2 0x02402C00516#define GC_BASE__INST0_SEG3 0517#define GC_BASE__INST0_SEG4 0518#define GC_BASE__INST0_SEG5 0519 520#define GC_BASE__INST1_SEG0 0521#define GC_BASE__INST1_SEG1 0522#define GC_BASE__INST1_SEG2 0523#define GC_BASE__INST1_SEG3 0524#define GC_BASE__INST1_SEG4 0525#define GC_BASE__INST1_SEG5 0526 527#define GC_BASE__INST2_SEG0 0528#define GC_BASE__INST2_SEG1 0529#define GC_BASE__INST2_SEG2 0530#define GC_BASE__INST2_SEG3 0531#define GC_BASE__INST2_SEG4 0532#define GC_BASE__INST2_SEG5 0533 534#define GC_BASE__INST3_SEG0 0535#define GC_BASE__INST3_SEG1 0536#define GC_BASE__INST3_SEG2 0537#define GC_BASE__INST3_SEG3 0538#define GC_BASE__INST3_SEG4 0539#define GC_BASE__INST3_SEG5 0540 541#define GC_BASE__INST4_SEG0 0542#define GC_BASE__INST4_SEG1 0543#define GC_BASE__INST4_SEG2 0544#define GC_BASE__INST4_SEG3 0545#define GC_BASE__INST4_SEG4 0546#define GC_BASE__INST4_SEG5 0547 548#define GC_BASE__INST5_SEG0 0549#define GC_BASE__INST5_SEG1 0550#define GC_BASE__INST5_SEG2 0551#define GC_BASE__INST5_SEG3 0552#define GC_BASE__INST5_SEG4 0553#define GC_BASE__INST5_SEG5 0554 555#define GC_BASE__INST6_SEG0 0556#define GC_BASE__INST6_SEG1 0557#define GC_BASE__INST6_SEG2 0558#define GC_BASE__INST6_SEG3 0559#define GC_BASE__INST6_SEG4 0560#define GC_BASE__INST6_SEG5 0561 562#define HDP_BASE__INST0_SEG0 0x00000F20563#define HDP_BASE__INST0_SEG1 0x0240A400564#define HDP_BASE__INST0_SEG2 0565#define HDP_BASE__INST0_SEG3 0566#define HDP_BASE__INST0_SEG4 0567#define HDP_BASE__INST0_SEG5 0568 569#define HDP_BASE__INST1_SEG0 0570#define HDP_BASE__INST1_SEG1 0571#define HDP_BASE__INST1_SEG2 0572#define HDP_BASE__INST1_SEG3 0573#define HDP_BASE__INST1_SEG4 0574#define HDP_BASE__INST1_SEG5 0575 576#define HDP_BASE__INST2_SEG0 0577#define HDP_BASE__INST2_SEG1 0578#define HDP_BASE__INST2_SEG2 0579#define HDP_BASE__INST2_SEG3 0580#define HDP_BASE__INST2_SEG4 0581#define HDP_BASE__INST2_SEG5 0582 583#define HDP_BASE__INST3_SEG0 0584#define HDP_BASE__INST3_SEG1 0585#define HDP_BASE__INST3_SEG2 0586#define HDP_BASE__INST3_SEG3 0587#define HDP_BASE__INST3_SEG4 0588#define HDP_BASE__INST3_SEG5 0589 590#define HDP_BASE__INST4_SEG0 0591#define HDP_BASE__INST4_SEG1 0592#define HDP_BASE__INST4_SEG2 0593#define HDP_BASE__INST4_SEG3 0594#define HDP_BASE__INST4_SEG4 0595#define HDP_BASE__INST4_SEG5 0596 597#define HDP_BASE__INST5_SEG0 0598#define HDP_BASE__INST5_SEG1 0599#define HDP_BASE__INST5_SEG2 0600#define HDP_BASE__INST5_SEG3 0601#define HDP_BASE__INST5_SEG4 0602#define HDP_BASE__INST5_SEG5 0603 604#define HDP_BASE__INST6_SEG0 0605#define HDP_BASE__INST6_SEG1 0606#define HDP_BASE__INST6_SEG2 0607#define HDP_BASE__INST6_SEG3 0608#define HDP_BASE__INST6_SEG4 0609#define HDP_BASE__INST6_SEG5 0610 611#define IOAGR0_BASE__INST0_SEG0 0x02419000612#define IOAGR0_BASE__INST0_SEG1 0x056C0000613#define IOAGR0_BASE__INST0_SEG2 0614#define IOAGR0_BASE__INST0_SEG3 0615#define IOAGR0_BASE__INST0_SEG4 0616#define IOAGR0_BASE__INST0_SEG5 0617 618#define IOAGR0_BASE__INST1_SEG0 0619#define IOAGR0_BASE__INST1_SEG1 0620#define IOAGR0_BASE__INST1_SEG2 0621#define IOAGR0_BASE__INST1_SEG3 0622#define IOAGR0_BASE__INST1_SEG4 0623#define IOAGR0_BASE__INST1_SEG5 0624 625#define IOAGR0_BASE__INST2_SEG0 0626#define IOAGR0_BASE__INST2_SEG1 0627#define IOAGR0_BASE__INST2_SEG2 0628#define IOAGR0_BASE__INST2_SEG3 0629#define IOAGR0_BASE__INST2_SEG4 0630#define IOAGR0_BASE__INST2_SEG5 0631 632#define IOAGR0_BASE__INST3_SEG0 0633#define IOAGR0_BASE__INST3_SEG1 0634#define IOAGR0_BASE__INST3_SEG2 0635#define IOAGR0_BASE__INST3_SEG3 0636#define IOAGR0_BASE__INST3_SEG4 0637#define IOAGR0_BASE__INST3_SEG5 0638 639#define IOAGR0_BASE__INST4_SEG0 0640#define IOAGR0_BASE__INST4_SEG1 0641#define IOAGR0_BASE__INST4_SEG2 0642#define IOAGR0_BASE__INST4_SEG3 0643#define IOAGR0_BASE__INST4_SEG4 0644#define IOAGR0_BASE__INST4_SEG5 0645 646#define IOAGR0_BASE__INST5_SEG0 0647#define IOAGR0_BASE__INST5_SEG1 0648#define IOAGR0_BASE__INST5_SEG2 0649#define IOAGR0_BASE__INST5_SEG3 0650#define IOAGR0_BASE__INST5_SEG4 0651#define IOAGR0_BASE__INST5_SEG5 0652 653#define IOAGR0_BASE__INST6_SEG0 0654#define IOAGR0_BASE__INST6_SEG1 0655#define IOAGR0_BASE__INST6_SEG2 0656#define IOAGR0_BASE__INST6_SEG3 0657#define IOAGR0_BASE__INST6_SEG4 0658#define IOAGR0_BASE__INST6_SEG5 0659 660#define IOAPIC0_BASE__INST0_SEG0 0x00A00000661#define IOAPIC0_BASE__INST0_SEG1 0x0241F000662#define IOAPIC0_BASE__INST0_SEG2 0x050C0000663#define IOAPIC0_BASE__INST0_SEG3 0664#define IOAPIC0_BASE__INST0_SEG4 0665#define IOAPIC0_BASE__INST0_SEG5 0666 667#define IOAPIC0_BASE__INST1_SEG0 0668#define IOAPIC0_BASE__INST1_SEG1 0669#define IOAPIC0_BASE__INST1_SEG2 0670#define IOAPIC0_BASE__INST1_SEG3 0671#define IOAPIC0_BASE__INST1_SEG4 0672#define IOAPIC0_BASE__INST1_SEG5 0673 674#define IOAPIC0_BASE__INST2_SEG0 0675#define IOAPIC0_BASE__INST2_SEG1 0676#define IOAPIC0_BASE__INST2_SEG2 0677#define IOAPIC0_BASE__INST2_SEG3 0678#define IOAPIC0_BASE__INST2_SEG4 0679#define IOAPIC0_BASE__INST2_SEG5 0680 681#define IOAPIC0_BASE__INST3_SEG0 0682#define IOAPIC0_BASE__INST3_SEG1 0683#define IOAPIC0_BASE__INST3_SEG2 0684#define IOAPIC0_BASE__INST3_SEG3 0685#define IOAPIC0_BASE__INST3_SEG4 0686#define IOAPIC0_BASE__INST3_SEG5 0687 688#define IOAPIC0_BASE__INST4_SEG0 0689#define IOAPIC0_BASE__INST4_SEG1 0690#define IOAPIC0_BASE__INST4_SEG2 0691#define IOAPIC0_BASE__INST4_SEG3 0692#define IOAPIC0_BASE__INST4_SEG4 0693#define IOAPIC0_BASE__INST4_SEG5 0694 695#define IOAPIC0_BASE__INST5_SEG0 0696#define IOAPIC0_BASE__INST5_SEG1 0697#define IOAPIC0_BASE__INST5_SEG2 0698#define IOAPIC0_BASE__INST5_SEG3 0699#define IOAPIC0_BASE__INST5_SEG4 0700#define IOAPIC0_BASE__INST5_SEG5 0701 702#define IOAPIC0_BASE__INST6_SEG0 0703#define IOAPIC0_BASE__INST6_SEG1 0704#define IOAPIC0_BASE__INST6_SEG2 0705#define IOAPIC0_BASE__INST6_SEG3 0706#define IOAPIC0_BASE__INST6_SEG4 0707#define IOAPIC0_BASE__INST6_SEG5 0708 709#define IOHC0_BASE__INST0_SEG0 0x00010000710#define IOHC0_BASE__INST0_SEG1 0x02406000711#define IOHC0_BASE__INST0_SEG2 0x04EC0000712#define IOHC0_BASE__INST0_SEG3 0713#define IOHC0_BASE__INST0_SEG4 0714#define IOHC0_BASE__INST0_SEG5 0715 716#define IOHC0_BASE__INST1_SEG0 0717#define IOHC0_BASE__INST1_SEG1 0718#define IOHC0_BASE__INST1_SEG2 0719#define IOHC0_BASE__INST1_SEG3 0720#define IOHC0_BASE__INST1_SEG4 0721#define IOHC0_BASE__INST1_SEG5 0722 723#define IOHC0_BASE__INST2_SEG0 0724#define IOHC0_BASE__INST2_SEG1 0725#define IOHC0_BASE__INST2_SEG2 0726#define IOHC0_BASE__INST2_SEG3 0727#define IOHC0_BASE__INST2_SEG4 0728#define IOHC0_BASE__INST2_SEG5 0729 730#define IOHC0_BASE__INST3_SEG0 0731#define IOHC0_BASE__INST3_SEG1 0732#define IOHC0_BASE__INST3_SEG2 0733#define IOHC0_BASE__INST3_SEG3 0734#define IOHC0_BASE__INST3_SEG4 0735#define IOHC0_BASE__INST3_SEG5 0736 737#define IOHC0_BASE__INST4_SEG0 0738#define IOHC0_BASE__INST4_SEG1 0739#define IOHC0_BASE__INST4_SEG2 0740#define IOHC0_BASE__INST4_SEG3 0741#define IOHC0_BASE__INST4_SEG4 0742#define IOHC0_BASE__INST4_SEG5 0743 744#define IOHC0_BASE__INST5_SEG0 0745#define IOHC0_BASE__INST5_SEG1 0746#define IOHC0_BASE__INST5_SEG2 0747#define IOHC0_BASE__INST5_SEG3 0748#define IOHC0_BASE__INST5_SEG4 0749#define IOHC0_BASE__INST5_SEG5 0750 751#define IOHC0_BASE__INST6_SEG0 0752#define IOHC0_BASE__INST6_SEG1 0753#define IOHC0_BASE__INST6_SEG2 0754#define IOHC0_BASE__INST6_SEG3 0755#define IOHC0_BASE__INST6_SEG4 0756#define IOHC0_BASE__INST6_SEG5 0757 758#define L1IMUIOAGR0_BASE__INST0_SEG0 0x0240CC00759#define L1IMUIOAGR0_BASE__INST0_SEG1 0x05200000760#define L1IMUIOAGR0_BASE__INST0_SEG2 0761#define L1IMUIOAGR0_BASE__INST0_SEG3 0762#define L1IMUIOAGR0_BASE__INST0_SEG4 0763#define L1IMUIOAGR0_BASE__INST0_SEG5 0764 765#define L1IMUIOAGR0_BASE__INST1_SEG0 0766#define L1IMUIOAGR0_BASE__INST1_SEG1 0767#define L1IMUIOAGR0_BASE__INST1_SEG2 0768#define L1IMUIOAGR0_BASE__INST1_SEG3 0769#define L1IMUIOAGR0_BASE__INST1_SEG4 0770#define L1IMUIOAGR0_BASE__INST1_SEG5 0771 772#define L1IMUIOAGR0_BASE__INST2_SEG0 0773#define L1IMUIOAGR0_BASE__INST2_SEG1 0774#define L1IMUIOAGR0_BASE__INST2_SEG2 0775#define L1IMUIOAGR0_BASE__INST2_SEG3 0776#define L1IMUIOAGR0_BASE__INST2_SEG4 0777#define L1IMUIOAGR0_BASE__INST2_SEG5 0778 779#define L1IMUIOAGR0_BASE__INST3_SEG0 0780#define L1IMUIOAGR0_BASE__INST3_SEG1 0781#define L1IMUIOAGR0_BASE__INST3_SEG2 0782#define L1IMUIOAGR0_BASE__INST3_SEG3 0783#define L1IMUIOAGR0_BASE__INST3_SEG4 0784#define L1IMUIOAGR0_BASE__INST3_SEG5 0785 786#define L1IMUIOAGR0_BASE__INST4_SEG0 0787#define L1IMUIOAGR0_BASE__INST4_SEG1 0788#define L1IMUIOAGR0_BASE__INST4_SEG2 0789#define L1IMUIOAGR0_BASE__INST4_SEG3 0790#define L1IMUIOAGR0_BASE__INST4_SEG4 0791#define L1IMUIOAGR0_BASE__INST4_SEG5 0792 793#define L1IMUIOAGR0_BASE__INST5_SEG0 0794#define L1IMUIOAGR0_BASE__INST5_SEG1 0795#define L1IMUIOAGR0_BASE__INST5_SEG2 0796#define L1IMUIOAGR0_BASE__INST5_SEG3 0797#define L1IMUIOAGR0_BASE__INST5_SEG4 0798#define L1IMUIOAGR0_BASE__INST5_SEG5 0799 800#define L1IMUIOAGR0_BASE__INST6_SEG0 0801#define L1IMUIOAGR0_BASE__INST6_SEG1 0802#define L1IMUIOAGR0_BASE__INST6_SEG2 0803#define L1IMUIOAGR0_BASE__INST6_SEG3 0804#define L1IMUIOAGR0_BASE__INST6_SEG4 0805#define L1IMUIOAGR0_BASE__INST6_SEG5 0806 807#define L1IMUPCIE0_BASE__INST0_SEG0 0x0240C800808#define L1IMUPCIE0_BASE__INST0_SEG1 0x051C0000809#define L1IMUPCIE0_BASE__INST0_SEG2 0810#define L1IMUPCIE0_BASE__INST0_SEG3 0811#define L1IMUPCIE0_BASE__INST0_SEG4 0812#define L1IMUPCIE0_BASE__INST0_SEG5 0813 814#define L1IMUPCIE0_BASE__INST1_SEG0 0815#define L1IMUPCIE0_BASE__INST1_SEG1 0816#define L1IMUPCIE0_BASE__INST1_SEG2 0817#define L1IMUPCIE0_BASE__INST1_SEG3 0818#define L1IMUPCIE0_BASE__INST1_SEG4 0819#define L1IMUPCIE0_BASE__INST1_SEG5 0820 821#define L1IMUPCIE0_BASE__INST2_SEG0 0822#define L1IMUPCIE0_BASE__INST2_SEG1 0823#define L1IMUPCIE0_BASE__INST2_SEG2 0824#define L1IMUPCIE0_BASE__INST2_SEG3 0825#define L1IMUPCIE0_BASE__INST2_SEG4 0826#define L1IMUPCIE0_BASE__INST2_SEG5 0827 828#define L1IMUPCIE0_BASE__INST3_SEG0 0829#define L1IMUPCIE0_BASE__INST3_SEG1 0830#define L1IMUPCIE0_BASE__INST3_SEG2 0831#define L1IMUPCIE0_BASE__INST3_SEG3 0832#define L1IMUPCIE0_BASE__INST3_SEG4 0833#define L1IMUPCIE0_BASE__INST3_SEG5 0834 835#define L1IMUPCIE0_BASE__INST4_SEG0 0836#define L1IMUPCIE0_BASE__INST4_SEG1 0837#define L1IMUPCIE0_BASE__INST4_SEG2 0838#define L1IMUPCIE0_BASE__INST4_SEG3 0839#define L1IMUPCIE0_BASE__INST4_SEG4 0840#define L1IMUPCIE0_BASE__INST4_SEG5 0841 842#define L1IMUPCIE0_BASE__INST5_SEG0 0843#define L1IMUPCIE0_BASE__INST5_SEG1 0844#define L1IMUPCIE0_BASE__INST5_SEG2 0845#define L1IMUPCIE0_BASE__INST5_SEG3 0846#define L1IMUPCIE0_BASE__INST5_SEG4 0847#define L1IMUPCIE0_BASE__INST5_SEG5 0848 849#define L1IMUPCIE0_BASE__INST6_SEG0 0850#define L1IMUPCIE0_BASE__INST6_SEG1 0851#define L1IMUPCIE0_BASE__INST6_SEG2 0852#define L1IMUPCIE0_BASE__INST6_SEG3 0853#define L1IMUPCIE0_BASE__INST6_SEG4 0854#define L1IMUPCIE0_BASE__INST6_SEG5 0855 856#define L2IMU0_BASE__INST0_SEG0 0x00007DC0857#define L2IMU0_BASE__INST0_SEG1 0x00900000858#define L2IMU0_BASE__INST0_SEG2 0x02407000859#define L2IMU0_BASE__INST0_SEG3 0x04FC0000860#define L2IMU0_BASE__INST0_SEG4 0x055C0000861#define L2IMU0_BASE__INST0_SEG5 0862 863#define L2IMU0_BASE__INST1_SEG0 0864#define L2IMU0_BASE__INST1_SEG1 0865#define L2IMU0_BASE__INST1_SEG2 0866#define L2IMU0_BASE__INST1_SEG3 0867#define L2IMU0_BASE__INST1_SEG4 0868#define L2IMU0_BASE__INST1_SEG5 0869 870#define L2IMU0_BASE__INST2_SEG0 0871#define L2IMU0_BASE__INST2_SEG1 0872#define L2IMU0_BASE__INST2_SEG2 0873#define L2IMU0_BASE__INST2_SEG3 0874#define L2IMU0_BASE__INST2_SEG4 0875#define L2IMU0_BASE__INST2_SEG5 0876 877#define L2IMU0_BASE__INST3_SEG0 0878#define L2IMU0_BASE__INST3_SEG1 0879#define L2IMU0_BASE__INST3_SEG2 0880#define L2IMU0_BASE__INST3_SEG3 0881#define L2IMU0_BASE__INST3_SEG4 0882#define L2IMU0_BASE__INST3_SEG5 0883 884#define L2IMU0_BASE__INST4_SEG0 0885#define L2IMU0_BASE__INST4_SEG1 0886#define L2IMU0_BASE__INST4_SEG2 0887#define L2IMU0_BASE__INST4_SEG3 0888#define L2IMU0_BASE__INST4_SEG4 0889#define L2IMU0_BASE__INST4_SEG5 0890 891#define L2IMU0_BASE__INST5_SEG0 0892#define L2IMU0_BASE__INST5_SEG1 0893#define L2IMU0_BASE__INST5_SEG2 0894#define L2IMU0_BASE__INST5_SEG3 0895#define L2IMU0_BASE__INST5_SEG4 0896#define L2IMU0_BASE__INST5_SEG5 0897 898#define L2IMU0_BASE__INST6_SEG0 0899#define L2IMU0_BASE__INST6_SEG1 0900#define L2IMU0_BASE__INST6_SEG2 0901#define L2IMU0_BASE__INST6_SEG3 0902#define L2IMU0_BASE__INST6_SEG4 0903#define L2IMU0_BASE__INST6_SEG5 0904 905#define MMHUB_BASE__INST0_SEG0 0x0001A000906#define MMHUB_BASE__INST0_SEG1 0x02408800907#define MMHUB_BASE__INST0_SEG2 0908#define MMHUB_BASE__INST0_SEG3 0909#define MMHUB_BASE__INST0_SEG4 0910#define MMHUB_BASE__INST0_SEG5 0911 912#define MMHUB_BASE__INST1_SEG0 0913#define MMHUB_BASE__INST1_SEG1 0914#define MMHUB_BASE__INST1_SEG2 0915#define MMHUB_BASE__INST1_SEG3 0916#define MMHUB_BASE__INST1_SEG4 0917#define MMHUB_BASE__INST1_SEG5 0918 919#define MMHUB_BASE__INST2_SEG0 0920#define MMHUB_BASE__INST2_SEG1 0921#define MMHUB_BASE__INST2_SEG2 0922#define MMHUB_BASE__INST2_SEG3 0923#define MMHUB_BASE__INST2_SEG4 0924#define MMHUB_BASE__INST2_SEG5 0925 926#define MMHUB_BASE__INST3_SEG0 0927#define MMHUB_BASE__INST3_SEG1 0928#define MMHUB_BASE__INST3_SEG2 0929#define MMHUB_BASE__INST3_SEG3 0930#define MMHUB_BASE__INST3_SEG4 0931#define MMHUB_BASE__INST3_SEG5 0932 933#define MMHUB_BASE__INST4_SEG0 0934#define MMHUB_BASE__INST4_SEG1 0935#define MMHUB_BASE__INST4_SEG2 0936#define MMHUB_BASE__INST4_SEG3 0937#define MMHUB_BASE__INST4_SEG4 0938#define MMHUB_BASE__INST4_SEG5 0939 940#define MMHUB_BASE__INST5_SEG0 0941#define MMHUB_BASE__INST5_SEG1 0942#define MMHUB_BASE__INST5_SEG2 0943#define MMHUB_BASE__INST5_SEG3 0944#define MMHUB_BASE__INST5_SEG4 0945#define MMHUB_BASE__INST5_SEG5 0946 947#define MMHUB_BASE__INST6_SEG0 0948#define MMHUB_BASE__INST6_SEG1 0949#define MMHUB_BASE__INST6_SEG2 0950#define MMHUB_BASE__INST6_SEG3 0951#define MMHUB_BASE__INST6_SEG4 0952#define MMHUB_BASE__INST6_SEG5 0953 954#define MP0_BASE__INST0_SEG0 0x00016000955#define MP0_BASE__INST0_SEG1 0x00DC0000956#define MP0_BASE__INST0_SEG2 0x00E00000957#define MP0_BASE__INST0_SEG3 0x00E40000958#define MP0_BASE__INST0_SEG4 0x0243FC00959#define MP0_BASE__INST0_SEG5 0960 961#define MP0_BASE__INST1_SEG0 0962#define MP0_BASE__INST1_SEG1 0963#define MP0_BASE__INST1_SEG2 0964#define MP0_BASE__INST1_SEG3 0965#define MP0_BASE__INST1_SEG4 0966#define MP0_BASE__INST1_SEG5 0967 968#define MP0_BASE__INST2_SEG0 0969#define MP0_BASE__INST2_SEG1 0970#define MP0_BASE__INST2_SEG2 0971#define MP0_BASE__INST2_SEG3 0972#define MP0_BASE__INST2_SEG4 0973#define MP0_BASE__INST2_SEG5 0974 975#define MP0_BASE__INST3_SEG0 0976#define MP0_BASE__INST3_SEG1 0977#define MP0_BASE__INST3_SEG2 0978#define MP0_BASE__INST3_SEG3 0979#define MP0_BASE__INST3_SEG4 0980#define MP0_BASE__INST3_SEG5 0981 982#define MP0_BASE__INST4_SEG0 0983#define MP0_BASE__INST4_SEG1 0984#define MP0_BASE__INST4_SEG2 0985#define MP0_BASE__INST4_SEG3 0986#define MP0_BASE__INST4_SEG4 0987#define MP0_BASE__INST4_SEG5 0988 989#define MP0_BASE__INST5_SEG0 0990#define MP0_BASE__INST5_SEG1 0991#define MP0_BASE__INST5_SEG2 0992#define MP0_BASE__INST5_SEG3 0993#define MP0_BASE__INST5_SEG4 0994#define MP0_BASE__INST5_SEG5 0995 996#define MP0_BASE__INST6_SEG0 0997#define MP0_BASE__INST6_SEG1 0998#define MP0_BASE__INST6_SEG2 0999#define MP0_BASE__INST6_SEG3 01000#define MP0_BASE__INST6_SEG4 01001#define MP0_BASE__INST6_SEG5 01002 1003#define MP1_BASE__INST0_SEG0 0x000160001004#define MP1_BASE__INST0_SEG1 0x00DC00001005#define MP1_BASE__INST0_SEG2 0x00E000001006#define MP1_BASE__INST0_SEG3 0x00E400001007#define MP1_BASE__INST0_SEG4 0x0243FC001008#define MP1_BASE__INST0_SEG5 01009 1010#define MP1_BASE__INST1_SEG0 01011#define MP1_BASE__INST1_SEG1 01012#define MP1_BASE__INST1_SEG2 01013#define MP1_BASE__INST1_SEG3 01014#define MP1_BASE__INST1_SEG4 01015#define MP1_BASE__INST1_SEG5 01016 1017#define MP1_BASE__INST2_SEG0 01018#define MP1_BASE__INST2_SEG1 01019#define MP1_BASE__INST2_SEG2 01020#define MP1_BASE__INST2_SEG3 01021#define MP1_BASE__INST2_SEG4 01022#define MP1_BASE__INST2_SEG5 01023 1024#define MP1_BASE__INST3_SEG0 01025#define MP1_BASE__INST3_SEG1 01026#define MP1_BASE__INST3_SEG2 01027#define MP1_BASE__INST3_SEG3 01028#define MP1_BASE__INST3_SEG4 01029#define MP1_BASE__INST3_SEG5 01030 1031#define MP1_BASE__INST4_SEG0 01032#define MP1_BASE__INST4_SEG1 01033#define MP1_BASE__INST4_SEG2 01034#define MP1_BASE__INST4_SEG3 01035#define MP1_BASE__INST4_SEG4 01036#define MP1_BASE__INST4_SEG5 01037 1038#define MP1_BASE__INST5_SEG0 01039#define MP1_BASE__INST5_SEG1 01040#define MP1_BASE__INST5_SEG2 01041#define MP1_BASE__INST5_SEG3 01042#define MP1_BASE__INST5_SEG4 01043#define MP1_BASE__INST5_SEG5 01044 1045#define MP1_BASE__INST6_SEG0 01046#define MP1_BASE__INST6_SEG1 01047#define MP1_BASE__INST6_SEG2 01048#define MP1_BASE__INST6_SEG3 01049#define MP1_BASE__INST6_SEG4 01050#define MP1_BASE__INST6_SEG5 01051 1052#define NBIO_BASE__INST0_SEG0 0x000000001053#define NBIO_BASE__INST0_SEG1 0x000000141054#define NBIO_BASE__INST0_SEG2 0x00000D201055#define NBIO_BASE__INST0_SEG3 0x000104001056#define NBIO_BASE__INST0_SEG4 0x0241B0001057#define NBIO_BASE__INST0_SEG5 0x040400001058 1059#define NBIO_BASE__INST1_SEG0 01060#define NBIO_BASE__INST1_SEG1 01061#define NBIO_BASE__INST1_SEG2 01062#define NBIO_BASE__INST1_SEG3 01063#define NBIO_BASE__INST1_SEG4 01064#define NBIO_BASE__INST1_SEG5 01065 1066#define NBIO_BASE__INST2_SEG0 01067#define NBIO_BASE__INST2_SEG1 01068#define NBIO_BASE__INST2_SEG2 01069#define NBIO_BASE__INST2_SEG3 01070#define NBIO_BASE__INST2_SEG4 01071#define NBIO_BASE__INST2_SEG5 01072 1073#define NBIO_BASE__INST3_SEG0 01074#define NBIO_BASE__INST3_SEG1 01075#define NBIO_BASE__INST3_SEG2 01076#define NBIO_BASE__INST3_SEG3 01077#define NBIO_BASE__INST3_SEG4 01078#define NBIO_BASE__INST3_SEG5 01079 1080#define NBIO_BASE__INST4_SEG0 01081#define NBIO_BASE__INST4_SEG1 01082#define NBIO_BASE__INST4_SEG2 01083#define NBIO_BASE__INST4_SEG3 01084#define NBIO_BASE__INST4_SEG4 01085#define NBIO_BASE__INST4_SEG5 01086 1087#define NBIO_BASE__INST5_SEG0 01088#define NBIO_BASE__INST5_SEG1 01089#define NBIO_BASE__INST5_SEG2 01090#define NBIO_BASE__INST5_SEG3 01091#define NBIO_BASE__INST5_SEG4 01092#define NBIO_BASE__INST5_SEG5 01093 1094#define NBIO_BASE__INST6_SEG0 01095#define NBIO_BASE__INST6_SEG1 01096#define NBIO_BASE__INST6_SEG2 01097#define NBIO_BASE__INST6_SEG3 01098#define NBIO_BASE__INST6_SEG4 01099#define NBIO_BASE__INST6_SEG5 01100 1101#define OSSSYS_BASE__INST0_SEG0 0x000010A01102#define OSSSYS_BASE__INST0_SEG1 0x0240A0001103#define OSSSYS_BASE__INST0_SEG2 01104#define OSSSYS_BASE__INST0_SEG3 01105#define OSSSYS_BASE__INST0_SEG4 01106#define OSSSYS_BASE__INST0_SEG5 01107 1108#define OSSSYS_BASE__INST1_SEG0 01109#define OSSSYS_BASE__INST1_SEG1 01110#define OSSSYS_BASE__INST1_SEG2 01111#define OSSSYS_BASE__INST1_SEG3 01112#define OSSSYS_BASE__INST1_SEG4 01113#define OSSSYS_BASE__INST1_SEG5 01114 1115#define OSSSYS_BASE__INST2_SEG0 01116#define OSSSYS_BASE__INST2_SEG1 01117#define OSSSYS_BASE__INST2_SEG2 01118#define OSSSYS_BASE__INST2_SEG3 01119#define OSSSYS_BASE__INST2_SEG4 01120#define OSSSYS_BASE__INST2_SEG5 01121 1122#define OSSSYS_BASE__INST3_SEG0 01123#define OSSSYS_BASE__INST3_SEG1 01124#define OSSSYS_BASE__INST3_SEG2 01125#define OSSSYS_BASE__INST3_SEG3 01126#define OSSSYS_BASE__INST3_SEG4 01127#define OSSSYS_BASE__INST3_SEG5 01128 1129#define OSSSYS_BASE__INST4_SEG0 01130#define OSSSYS_BASE__INST4_SEG1 01131#define OSSSYS_BASE__INST4_SEG2 01132#define OSSSYS_BASE__INST4_SEG3 01133#define OSSSYS_BASE__INST4_SEG4 01134#define OSSSYS_BASE__INST4_SEG5 01135 1136#define OSSSYS_BASE__INST5_SEG0 01137#define OSSSYS_BASE__INST5_SEG1 01138#define OSSSYS_BASE__INST5_SEG2 01139#define OSSSYS_BASE__INST5_SEG3 01140#define OSSSYS_BASE__INST5_SEG4 01141#define OSSSYS_BASE__INST5_SEG5 01142 1143#define OSSSYS_BASE__INST6_SEG0 01144#define OSSSYS_BASE__INST6_SEG1 01145#define OSSSYS_BASE__INST6_SEG2 01146#define OSSSYS_BASE__INST6_SEG3 01147#define OSSSYS_BASE__INST6_SEG4 01148#define OSSSYS_BASE__INST6_SEG5 01149 1150#define PCIE0_BASE__INST0_SEG0 0x024118001151#define PCIE0_BASE__INST0_SEG1 0x044400001152#define PCIE0_BASE__INST0_SEG2 01153#define PCIE0_BASE__INST0_SEG3 01154#define PCIE0_BASE__INST0_SEG4 01155#define PCIE0_BASE__INST0_SEG5 01156 1157#define PCIE0_BASE__INST1_SEG0 01158#define PCIE0_BASE__INST1_SEG1 01159#define PCIE0_BASE__INST1_SEG2 01160#define PCIE0_BASE__INST1_SEG3 01161#define PCIE0_BASE__INST1_SEG4 01162#define PCIE0_BASE__INST1_SEG5 01163 1164#define PCIE0_BASE__INST2_SEG0 01165#define PCIE0_BASE__INST2_SEG1 01166#define PCIE0_BASE__INST2_SEG2 01167#define PCIE0_BASE__INST2_SEG3 01168#define PCIE0_BASE__INST2_SEG4 01169#define PCIE0_BASE__INST2_SEG5 01170 1171#define PCIE0_BASE__INST3_SEG0 01172#define PCIE0_BASE__INST3_SEG1 01173#define PCIE0_BASE__INST3_SEG2 01174#define PCIE0_BASE__INST3_SEG3 01175#define PCIE0_BASE__INST3_SEG4 01176#define PCIE0_BASE__INST3_SEG5 01177 1178#define PCIE0_BASE__INST4_SEG0 01179#define PCIE0_BASE__INST4_SEG1 01180#define PCIE0_BASE__INST4_SEG2 01181#define PCIE0_BASE__INST4_SEG3 01182#define PCIE0_BASE__INST4_SEG4 01183#define PCIE0_BASE__INST4_SEG5 01184 1185#define PCIE0_BASE__INST5_SEG0 01186#define PCIE0_BASE__INST5_SEG1 01187#define PCIE0_BASE__INST5_SEG2 01188#define PCIE0_BASE__INST5_SEG3 01189#define PCIE0_BASE__INST5_SEG4 01190#define PCIE0_BASE__INST5_SEG5 01191 1192#define PCIE0_BASE__INST6_SEG0 01193#define PCIE0_BASE__INST6_SEG1 01194#define PCIE0_BASE__INST6_SEG2 01195#define PCIE0_BASE__INST6_SEG3 01196#define PCIE0_BASE__INST6_SEG4 01197#define PCIE0_BASE__INST6_SEG5 01198 1199#define SDMA0_BASE__INST0_SEG0 0x000012601200#define SDMA0_BASE__INST0_SEG1 0x024454001201#define SDMA0_BASE__INST0_SEG2 01202#define SDMA0_BASE__INST0_SEG3 01203#define SDMA0_BASE__INST0_SEG4 01204#define SDMA0_BASE__INST0_SEG5 01205 1206#define SDMA0_BASE__INST1_SEG0 01207#define SDMA0_BASE__INST1_SEG1 01208#define SDMA0_BASE__INST1_SEG2 01209#define SDMA0_BASE__INST1_SEG3 01210#define SDMA0_BASE__INST1_SEG4 01211#define SDMA0_BASE__INST1_SEG5 01212 1213#define SDMA0_BASE__INST2_SEG0 01214#define SDMA0_BASE__INST2_SEG1 01215#define SDMA0_BASE__INST2_SEG2 01216#define SDMA0_BASE__INST2_SEG3 01217#define SDMA0_BASE__INST2_SEG4 01218#define SDMA0_BASE__INST2_SEG5 01219 1220#define SDMA0_BASE__INST3_SEG0 01221#define SDMA0_BASE__INST3_SEG1 01222#define SDMA0_BASE__INST3_SEG2 01223#define SDMA0_BASE__INST3_SEG3 01224#define SDMA0_BASE__INST3_SEG4 01225#define SDMA0_BASE__INST3_SEG5 01226 1227#define SDMA0_BASE__INST4_SEG0 01228#define SDMA0_BASE__INST4_SEG1 01229#define SDMA0_BASE__INST4_SEG2 01230#define SDMA0_BASE__INST4_SEG3 01231#define SDMA0_BASE__INST4_SEG4 01232#define SDMA0_BASE__INST4_SEG5 01233 1234#define SDMA0_BASE__INST5_SEG0 01235#define SDMA0_BASE__INST5_SEG1 01236#define SDMA0_BASE__INST5_SEG2 01237#define SDMA0_BASE__INST5_SEG3 01238#define SDMA0_BASE__INST5_SEG4 01239#define SDMA0_BASE__INST5_SEG5 01240 1241#define SDMA0_BASE__INST6_SEG0 01242#define SDMA0_BASE__INST6_SEG1 01243#define SDMA0_BASE__INST6_SEG2 01244#define SDMA0_BASE__INST6_SEG3 01245#define SDMA0_BASE__INST6_SEG4 01246#define SDMA0_BASE__INST6_SEG5 01247 1248#define SDMA1_BASE__INST0_SEG0 0x000018601249#define SDMA1_BASE__INST0_SEG1 0x024458001250#define SDMA1_BASE__INST0_SEG2 01251#define SDMA1_BASE__INST0_SEG3 01252#define SDMA1_BASE__INST0_SEG4 01253#define SDMA1_BASE__INST0_SEG5 01254 1255#define SDMA1_BASE__INST1_SEG0 0x0001E0001256#define SDMA1_BASE__INST1_SEG1 0x024464001257#define SDMA1_BASE__INST1_SEG2 01258#define SDMA1_BASE__INST1_SEG3 01259#define SDMA1_BASE__INST1_SEG4 01260#define SDMA1_BASE__INST1_SEG5 01261 1262#define SDMA1_BASE__INST2_SEG0 0x0001E4001263#define SDMA1_BASE__INST2_SEG1 0x024468001264#define SDMA1_BASE__INST2_SEG2 01265#define SDMA1_BASE__INST2_SEG3 01266#define SDMA1_BASE__INST2_SEG4 01267#define SDMA1_BASE__INST2_SEG5 01268 1269#define SDMA1_BASE__INST3_SEG0 0x0001E8001270#define SDMA1_BASE__INST3_SEG1 0x02446C001271#define SDMA1_BASE__INST3_SEG2 01272#define SDMA1_BASE__INST3_SEG3 01273#define SDMA1_BASE__INST3_SEG4 01274#define SDMA1_BASE__INST3_SEG5 01275 1276#define SDMA1_BASE__INST4_SEG0 01277#define SDMA1_BASE__INST4_SEG1 01278#define SDMA1_BASE__INST4_SEG2 01279#define SDMA1_BASE__INST4_SEG3 01280#define SDMA1_BASE__INST4_SEG4 01281#define SDMA1_BASE__INST4_SEG5 01282 1283#define SDMA1_BASE__INST5_SEG0 01284#define SDMA1_BASE__INST5_SEG1 01285#define SDMA1_BASE__INST5_SEG2 01286#define SDMA1_BASE__INST5_SEG3 01287#define SDMA1_BASE__INST5_SEG4 01288#define SDMA1_BASE__INST5_SEG5 01289 1290#define SDMA1_BASE__INST6_SEG0 01291#define SDMA1_BASE__INST6_SEG1 01292#define SDMA1_BASE__INST6_SEG2 01293#define SDMA1_BASE__INST6_SEG3 01294#define SDMA1_BASE__INST6_SEG4 01295#define SDMA1_BASE__INST6_SEG5 01296 1297#define SMUIO_BASE__INST0_SEG0 0x000168001298#define SMUIO_BASE__INST0_SEG1 0x00016A001299#define SMUIO_BASE__INST0_SEG2 0x024010001300#define SMUIO_BASE__INST0_SEG3 0x034400001301#define SMUIO_BASE__INST0_SEG4 01302#define SMUIO_BASE__INST0_SEG5 01303 1304#define SMUIO_BASE__INST1_SEG0 01305#define SMUIO_BASE__INST1_SEG1 01306#define SMUIO_BASE__INST1_SEG2 01307#define SMUIO_BASE__INST1_SEG3 01308#define SMUIO_BASE__INST1_SEG4 01309#define SMUIO_BASE__INST1_SEG5 01310 1311#define SMUIO_BASE__INST2_SEG0 01312#define SMUIO_BASE__INST2_SEG1 01313#define SMUIO_BASE__INST2_SEG2 01314#define SMUIO_BASE__INST2_SEG3 01315#define SMUIO_BASE__INST2_SEG4 01316#define SMUIO_BASE__INST2_SEG5 01317 1318#define SMUIO_BASE__INST3_SEG0 01319#define SMUIO_BASE__INST3_SEG1 01320#define SMUIO_BASE__INST3_SEG2 01321#define SMUIO_BASE__INST3_SEG3 01322#define SMUIO_BASE__INST3_SEG4 01323#define SMUIO_BASE__INST3_SEG5 01324 1325#define SMUIO_BASE__INST4_SEG0 01326#define SMUIO_BASE__INST4_SEG1 01327#define SMUIO_BASE__INST4_SEG2 01328#define SMUIO_BASE__INST4_SEG3 01329#define SMUIO_BASE__INST4_SEG4 01330#define SMUIO_BASE__INST4_SEG5 01331 1332#define SMUIO_BASE__INST5_SEG0 01333#define SMUIO_BASE__INST5_SEG1 01334#define SMUIO_BASE__INST5_SEG2 01335#define SMUIO_BASE__INST5_SEG3 01336#define SMUIO_BASE__INST5_SEG4 01337#define SMUIO_BASE__INST5_SEG5 01338 1339#define SMUIO_BASE__INST6_SEG0 01340#define SMUIO_BASE__INST6_SEG1 01341#define SMUIO_BASE__INST6_SEG2 01342#define SMUIO_BASE__INST6_SEG3 01343#define SMUIO_BASE__INST6_SEG4 01344#define SMUIO_BASE__INST6_SEG5 01345 1346#define THM_BASE__INST0_SEG0 0x000166001347#define THM_BASE__INST0_SEG1 0x02400C001348#define THM_BASE__INST0_SEG2 01349#define THM_BASE__INST0_SEG3 01350#define THM_BASE__INST0_SEG4 01351#define THM_BASE__INST0_SEG5 01352 1353#define THM_BASE__INST1_SEG0 01354#define THM_BASE__INST1_SEG1 01355#define THM_BASE__INST1_SEG2 01356#define THM_BASE__INST1_SEG3 01357#define THM_BASE__INST1_SEG4 01358#define THM_BASE__INST1_SEG5 01359 1360#define THM_BASE__INST2_SEG0 01361#define THM_BASE__INST2_SEG1 01362#define THM_BASE__INST2_SEG2 01363#define THM_BASE__INST2_SEG3 01364#define THM_BASE__INST2_SEG4 01365#define THM_BASE__INST2_SEG5 01366 1367#define THM_BASE__INST3_SEG0 01368#define THM_BASE__INST3_SEG1 01369#define THM_BASE__INST3_SEG2 01370#define THM_BASE__INST3_SEG3 01371#define THM_BASE__INST3_SEG4 01372#define THM_BASE__INST3_SEG5 01373 1374#define THM_BASE__INST4_SEG0 01375#define THM_BASE__INST4_SEG1 01376#define THM_BASE__INST4_SEG2 01377#define THM_BASE__INST4_SEG3 01378#define THM_BASE__INST4_SEG4 01379#define THM_BASE__INST4_SEG5 01380 1381#define THM_BASE__INST5_SEG0 01382#define THM_BASE__INST5_SEG1 01383#define THM_BASE__INST5_SEG2 01384#define THM_BASE__INST5_SEG3 01385#define THM_BASE__INST5_SEG4 01386#define THM_BASE__INST5_SEG5 01387 1388#define THM_BASE__INST6_SEG0 01389#define THM_BASE__INST6_SEG1 01390#define THM_BASE__INST6_SEG2 01391#define THM_BASE__INST6_SEG3 01392#define THM_BASE__INST6_SEG4 01393#define THM_BASE__INST6_SEG5 01394 1395#define UMC_BASE__INST0_SEG0 0x000140001396#define UMC_BASE__INST0_SEG1 0x000540001397#define UMC_BASE__INST0_SEG2 0x024258001398#define UMC_BASE__INST0_SEG3 01399#define UMC_BASE__INST0_SEG4 01400#define UMC_BASE__INST0_SEG5 01401 1402#define UMC_BASE__INST1_SEG0 0x000940001403#define UMC_BASE__INST1_SEG1 0x000D40001404#define UMC_BASE__INST1_SEG2 0x02425C001405#define UMC_BASE__INST1_SEG3 01406#define UMC_BASE__INST1_SEG4 01407#define UMC_BASE__INST1_SEG5 01408 1409#define UMC_BASE__INST2_SEG0 0x001140001410#define UMC_BASE__INST2_SEG1 0x001540001411#define UMC_BASE__INST2_SEG2 0x024260001412#define UMC_BASE__INST2_SEG3 01413#define UMC_BASE__INST2_SEG4 01414#define UMC_BASE__INST2_SEG5 01415 1416#define UMC_BASE__INST3_SEG0 0x001940001417#define UMC_BASE__INST3_SEG1 0x001D40001418#define UMC_BASE__INST3_SEG2 0x024264001419#define UMC_BASE__INST3_SEG3 01420#define UMC_BASE__INST3_SEG4 01421#define UMC_BASE__INST3_SEG5 01422 1423#define UMC_BASE__INST4_SEG0 01424#define UMC_BASE__INST4_SEG1 01425#define UMC_BASE__INST4_SEG2 01426#define UMC_BASE__INST4_SEG3 01427#define UMC_BASE__INST4_SEG4 01428#define UMC_BASE__INST4_SEG5 01429 1430#define UMC_BASE__INST5_SEG0 01431#define UMC_BASE__INST5_SEG1 01432#define UMC_BASE__INST5_SEG2 01433#define UMC_BASE__INST5_SEG3 01434#define UMC_BASE__INST5_SEG4 01435#define UMC_BASE__INST5_SEG5 01436 1437#define UMC_BASE__INST6_SEG0 01438#define UMC_BASE__INST6_SEG1 01439#define UMC_BASE__INST6_SEG2 01440#define UMC_BASE__INST6_SEG3 01441#define UMC_BASE__INST6_SEG4 01442#define UMC_BASE__INST6_SEG5 01443 1444#define VCN_BASE__INST0_SEG0 0x000078001445#define VCN_BASE__INST0_SEG1 0x00007E001446#define VCN_BASE__INST0_SEG2 0x024030001447#define VCN_BASE__INST0_SEG3 01448#define VCN_BASE__INST0_SEG4 01449#define VCN_BASE__INST0_SEG5 01450 1451#define VCN_BASE__INST1_SEG0 0x00007A001452#define VCN_BASE__INST1_SEG1 0x000090001453#define VCN_BASE__INST1_SEG2 0x024450001454#define VCN_BASE__INST1_SEG3 01455#define VCN_BASE__INST1_SEG4 01456#define VCN_BASE__INST1_SEG5 01457 1458#define VCN_BASE__INST2_SEG0 01459#define VCN_BASE__INST2_SEG1 01460#define VCN_BASE__INST2_SEG2 01461#define VCN_BASE__INST2_SEG3 01462#define VCN_BASE__INST2_SEG4 01463#define VCN_BASE__INST2_SEG5 01464 1465#define VCN_BASE__INST3_SEG0 01466#define VCN_BASE__INST3_SEG1 01467#define VCN_BASE__INST3_SEG2 01468#define VCN_BASE__INST3_SEG3 01469#define VCN_BASE__INST3_SEG4 01470#define VCN_BASE__INST3_SEG5 01471 1472#define VCN_BASE__INST4_SEG0 01473#define VCN_BASE__INST4_SEG1 01474#define VCN_BASE__INST4_SEG2 01475#define VCN_BASE__INST4_SEG3 01476#define VCN_BASE__INST4_SEG4 01477#define VCN_BASE__INST4_SEG5 01478 1479#define VCN_BASE__INST5_SEG0 01480#define VCN_BASE__INST5_SEG1 01481#define VCN_BASE__INST5_SEG2 01482#define VCN_BASE__INST5_SEG3 01483#define VCN_BASE__INST5_SEG4 01484#define VCN_BASE__INST5_SEG5 01485 1486#define VCN_BASE__INST6_SEG0 01487#define VCN_BASE__INST6_SEG1 01488#define VCN_BASE__INST6_SEG2 01489#define VCN_BASE__INST6_SEG3 01490#define VCN_BASE__INST6_SEG4 01491#define VCN_BASE__INST6_SEG5 01492 1493#define WAFL0_BASE__INST0_SEG0 0x024380001494#define WAFL0_BASE__INST0_SEG1 0x048800001495#define WAFL0_BASE__INST0_SEG2 01496#define WAFL0_BASE__INST0_SEG3 01497#define WAFL0_BASE__INST0_SEG4 01498#define WAFL0_BASE__INST0_SEG5 01499 1500#define WAFL0_BASE__INST1_SEG0 01501#define WAFL0_BASE__INST1_SEG1 01502#define WAFL0_BASE__INST1_SEG2 01503#define WAFL0_BASE__INST1_SEG3 01504#define WAFL0_BASE__INST1_SEG4 01505#define WAFL0_BASE__INST1_SEG5 01506 1507#define WAFL0_BASE__INST2_SEG0 01508#define WAFL0_BASE__INST2_SEG1 01509#define WAFL0_BASE__INST2_SEG2 01510#define WAFL0_BASE__INST2_SEG3 01511#define WAFL0_BASE__INST2_SEG4 01512#define WAFL0_BASE__INST2_SEG5 01513 1514#define WAFL0_BASE__INST3_SEG0 01515#define WAFL0_BASE__INST3_SEG1 01516#define WAFL0_BASE__INST3_SEG2 01517#define WAFL0_BASE__INST3_SEG3 01518#define WAFL0_BASE__INST3_SEG4 01519#define WAFL0_BASE__INST3_SEG5 01520 1521#define WAFL0_BASE__INST4_SEG0 01522#define WAFL0_BASE__INST4_SEG1 01523#define WAFL0_BASE__INST4_SEG2 01524#define WAFL0_BASE__INST4_SEG3 01525#define WAFL0_BASE__INST4_SEG4 01526#define WAFL0_BASE__INST4_SEG5 01527 1528#define WAFL0_BASE__INST5_SEG0 01529#define WAFL0_BASE__INST5_SEG1 01530#define WAFL0_BASE__INST5_SEG2 01531#define WAFL0_BASE__INST5_SEG3 01532#define WAFL0_BASE__INST5_SEG4 01533#define WAFL0_BASE__INST5_SEG5 01534 1535#define WAFL0_BASE__INST6_SEG0 01536#define WAFL0_BASE__INST6_SEG1 01537#define WAFL0_BASE__INST6_SEG2 01538#define WAFL0_BASE__INST6_SEG3 01539#define WAFL0_BASE__INST6_SEG4 01540#define WAFL0_BASE__INST6_SEG5 01541 1542#define WAFL1_BASE__INST0_SEG0 01543#define WAFL1_BASE__INST0_SEG1 0x013000001544#define WAFL1_BASE__INST0_SEG2 0x024108001545#define WAFL1_BASE__INST0_SEG3 01546#define WAFL1_BASE__INST0_SEG4 01547#define WAFL1_BASE__INST0_SEG5 01548 1549#define WAFL1_BASE__INST1_SEG0 01550#define WAFL1_BASE__INST1_SEG1 01551#define WAFL1_BASE__INST1_SEG2 01552#define WAFL1_BASE__INST1_SEG3 01553#define WAFL1_BASE__INST1_SEG4 01554#define WAFL1_BASE__INST1_SEG5 01555 1556#define WAFL1_BASE__INST2_SEG0 01557#define WAFL1_BASE__INST2_SEG1 01558#define WAFL1_BASE__INST2_SEG2 01559#define WAFL1_BASE__INST2_SEG3 01560#define WAFL1_BASE__INST2_SEG4 01561#define WAFL1_BASE__INST2_SEG5 01562 1563#define WAFL1_BASE__INST3_SEG0 01564#define WAFL1_BASE__INST3_SEG1 01565#define WAFL1_BASE__INST3_SEG2 01566#define WAFL1_BASE__INST3_SEG3 01567#define WAFL1_BASE__INST3_SEG4 01568#define WAFL1_BASE__INST3_SEG5 01569 1570#define WAFL1_BASE__INST4_SEG0 01571#define WAFL1_BASE__INST4_SEG1 01572#define WAFL1_BASE__INST4_SEG2 01573#define WAFL1_BASE__INST4_SEG3 01574#define WAFL1_BASE__INST4_SEG4 01575#define WAFL1_BASE__INST4_SEG5 01576 1577#define WAFL1_BASE__INST5_SEG0 01578#define WAFL1_BASE__INST5_SEG1 01579#define WAFL1_BASE__INST5_SEG2 01580#define WAFL1_BASE__INST5_SEG3 01581#define WAFL1_BASE__INST5_SEG4 01582#define WAFL1_BASE__INST5_SEG5 01583 1584#define WAFL1_BASE__INST6_SEG0 01585#define WAFL1_BASE__INST6_SEG1 01586#define WAFL1_BASE__INST6_SEG2 01587#define WAFL1_BASE__INST6_SEG3 01588#define WAFL1_BASE__INST6_SEG4 01589#define WAFL1_BASE__INST6_SEG5 01590 1591#define XGMI0_BASE__INST0_SEG0 0x02438C001592#define XGMI0_BASE__INST0_SEG1 0x046800001593#define XGMI0_BASE__INST0_SEG2 0x049400001594#define XGMI0_BASE__INST0_SEG3 01595#define XGMI0_BASE__INST0_SEG4 01596#define XGMI0_BASE__INST0_SEG5 01597 1598#define XGMI0_BASE__INST1_SEG0 01599#define XGMI0_BASE__INST1_SEG1 01600#define XGMI0_BASE__INST1_SEG2 01601#define XGMI0_BASE__INST1_SEG3 01602#define XGMI0_BASE__INST1_SEG4 01603#define XGMI0_BASE__INST1_SEG5 01604 1605#define XGMI0_BASE__INST2_SEG0 01606#define XGMI0_BASE__INST2_SEG1 01607#define XGMI0_BASE__INST2_SEG2 01608#define XGMI0_BASE__INST2_SEG3 01609#define XGMI0_BASE__INST2_SEG4 01610#define XGMI0_BASE__INST2_SEG5 01611 1612#define XGMI0_BASE__INST3_SEG0 01613#define XGMI0_BASE__INST3_SEG1 01614#define XGMI0_BASE__INST3_SEG2 01615#define XGMI0_BASE__INST3_SEG3 01616#define XGMI0_BASE__INST3_SEG4 01617#define XGMI0_BASE__INST3_SEG5 01618 1619#define XGMI0_BASE__INST4_SEG0 01620#define XGMI0_BASE__INST4_SEG1 01621#define XGMI0_BASE__INST4_SEG2 01622#define XGMI0_BASE__INST4_SEG3 01623#define XGMI0_BASE__INST4_SEG4 01624#define XGMI0_BASE__INST4_SEG5 01625 1626#define XGMI0_BASE__INST5_SEG0 01627#define XGMI0_BASE__INST5_SEG1 01628#define XGMI0_BASE__INST5_SEG2 01629#define XGMI0_BASE__INST5_SEG3 01630#define XGMI0_BASE__INST5_SEG4 01631#define XGMI0_BASE__INST5_SEG5 01632 1633#define XGMI0_BASE__INST6_SEG0 01634#define XGMI0_BASE__INST6_SEG1 01635#define XGMI0_BASE__INST6_SEG2 01636#define XGMI0_BASE__INST6_SEG3 01637#define XGMI0_BASE__INST6_SEG4 01638#define XGMI0_BASE__INST6_SEG5 01639 1640#define XGMI1_BASE__INST0_SEG0 0x024390001641#define XGMI1_BASE__INST0_SEG1 0x046C00001642#define XGMI1_BASE__INST0_SEG2 0x049800001643#define XGMI1_BASE__INST0_SEG3 01644#define XGMI1_BASE__INST0_SEG4 01645#define XGMI1_BASE__INST0_SEG5 01646 1647#define XGMI1_BASE__INST1_SEG0 01648#define XGMI1_BASE__INST1_SEG1 01649#define XGMI1_BASE__INST1_SEG2 01650#define XGMI1_BASE__INST1_SEG3 01651#define XGMI1_BASE__INST1_SEG4 01652#define XGMI1_BASE__INST1_SEG5 01653 1654#define XGMI1_BASE__INST2_SEG0 01655#define XGMI1_BASE__INST2_SEG1 01656#define XGMI1_BASE__INST2_SEG2 01657#define XGMI1_BASE__INST2_SEG3 01658#define XGMI1_BASE__INST2_SEG4 01659#define XGMI1_BASE__INST2_SEG5 01660 1661#define XGMI1_BASE__INST3_SEG0 01662#define XGMI1_BASE__INST3_SEG1 01663#define XGMI1_BASE__INST3_SEG2 01664#define XGMI1_BASE__INST3_SEG3 01665#define XGMI1_BASE__INST3_SEG4 01666#define XGMI1_BASE__INST3_SEG5 01667 1668#define XGMI1_BASE__INST4_SEG0 01669#define XGMI1_BASE__INST4_SEG1 01670#define XGMI1_BASE__INST4_SEG2 01671#define XGMI1_BASE__INST4_SEG3 01672#define XGMI1_BASE__INST4_SEG4 01673#define XGMI1_BASE__INST4_SEG5 01674 1675#define XGMI1_BASE__INST5_SEG0 01676#define XGMI1_BASE__INST5_SEG1 01677#define XGMI1_BASE__INST5_SEG2 01678#define XGMI1_BASE__INST5_SEG3 01679#define XGMI1_BASE__INST5_SEG4 01680#define XGMI1_BASE__INST5_SEG5 01681 1682#define XGMI1_BASE__INST6_SEG0 01683#define XGMI1_BASE__INST6_SEG1 01684#define XGMI1_BASE__INST6_SEG2 01685#define XGMI1_BASE__INST6_SEG3 01686#define XGMI1_BASE__INST6_SEG4 01687#define XGMI1_BASE__INST6_SEG5 01688 1689#define XGMI2_BASE__INST0_SEG0 0x047000001690#define XGMI2_BASE__INST0_SEG1 0x049C00001691#define XGMI2_BASE__INST0_SEG2 01692#define XGMI2_BASE__INST0_SEG3 01693#define XGMI2_BASE__INST0_SEG4 01694#define XGMI2_BASE__INST0_SEG5 01695 1696#define XGMI2_BASE__INST1_SEG0 0x047400001697#define XGMI2_BASE__INST1_SEG1 0x04A000001698#define XGMI2_BASE__INST1_SEG2 01699#define XGMI2_BASE__INST1_SEG3 01700#define XGMI2_BASE__INST1_SEG4 01701#define XGMI2_BASE__INST1_SEG5 01702 1703#define XGMI2_BASE__INST2_SEG0 0x047800001704#define XGMI2_BASE__INST2_SEG1 0x04A400001705#define XGMI2_BASE__INST2_SEG2 01706#define XGMI2_BASE__INST2_SEG3 01707#define XGMI2_BASE__INST2_SEG4 01708#define XGMI2_BASE__INST2_SEG5 01709 1710#define XGMI2_BASE__INST3_SEG0 0x047C00001711#define XGMI2_BASE__INST3_SEG1 0x04A800001712#define XGMI2_BASE__INST3_SEG2 01713#define XGMI2_BASE__INST3_SEG3 01714#define XGMI2_BASE__INST3_SEG4 01715#define XGMI2_BASE__INST3_SEG5 01716 1717#define XGMI2_BASE__INST4_SEG0 0x048000001718#define XGMI2_BASE__INST4_SEG1 0x04AC00001719#define XGMI2_BASE__INST4_SEG2 01720#define XGMI2_BASE__INST4_SEG3 01721#define XGMI2_BASE__INST4_SEG4 01722#define XGMI2_BASE__INST4_SEG5 01723 1724#define XGMI2_BASE__INST5_SEG0 0x048400001725#define XGMI2_BASE__INST5_SEG1 0x04B000001726#define XGMI2_BASE__INST5_SEG2 01727#define XGMI2_BASE__INST5_SEG3 01728#define XGMI2_BASE__INST5_SEG4 01729#define XGMI2_BASE__INST5_SEG5 01730 1731#define XGMI2_BASE__INST6_SEG0 01732#define XGMI2_BASE__INST6_SEG1 01733#define XGMI2_BASE__INST6_SEG2 01734#define XGMI2_BASE__INST6_SEG3 01735#define XGMI2_BASE__INST6_SEG4 01736#define XGMI2_BASE__INST6_SEG5 01737 1738#endif1739