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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#ifndef __AMD_PCIE_H__24#define __AMD_PCIE_H__25 26/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */27#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x0001000028#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x0002000029#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x0004000030#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x0008000031#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x0010000032#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF000033#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 1634 35/* Following flags shows PCIe link speed supported by ASIC H/W.*/36#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x0000000137#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x0000000238#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x0000000439#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x0000000840#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x0000001041#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF42#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 043 44/* gen: chipset 1/2, asic 1/2/3 */45#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \46 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \47 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \48 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \49 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)50 51/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */52#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x0001000053#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x0002000054#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x0004000055#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x0008000056#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x0010000057#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x0020000058#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x0040000059#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 1660 61/* 1/2/4/8/16 lanes */62#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \63 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \64 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \65 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \66 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)67 68#endif69