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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#ifndef __AMD_SHARED_H__24#define __AMD_SHARED_H__25 26#include <drm/amd_asic_type.h>27#include <drm/drm_print.h>28 29 30#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */31 32/*33 * Chip flags34 */35enum amd_chip_flags {36 AMD_ASIC_MASK = 0x0000ffffUL,37 AMD_FLAGS_MASK = 0xffff0000UL,38 AMD_IS_MOBILITY = 0x00010000UL,39 AMD_IS_APU = 0x00020000UL,40 AMD_IS_PX = 0x00040000UL,41 AMD_EXP_HW_SUPPORT = 0x00080000UL,42};43 44enum amd_apu_flags {45 AMD_APU_IS_RAVEN = 0x00000001UL,46 AMD_APU_IS_RAVEN2 = 0x00000002UL,47 AMD_APU_IS_PICASSO = 0x00000004UL,48 AMD_APU_IS_RENOIR = 0x00000008UL,49 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,50 AMD_APU_IS_VANGOGH = 0x00000020UL,51 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,52};53 54/**55* DOC: IP Blocks56*57* GPUs are composed of IP (intellectual property) blocks. These58* IP blocks provide various functionalities: display, graphics,59* video decode, etc. The IP blocks that comprise a particular GPU60* are listed in the GPU's respective SoC file. amdgpu_device.c61* acquires the list of IP blocks for the GPU in use on initialization.62* It can then operate on this list to perform standard driver operations63* such as: init, fini, suspend, resume, etc.64*65*66* IP block implementations are named using the following convention:67* <functionality>_v<version> (E.g.: gfx_v6_0).68*/69 70/**71* enum amd_ip_block_type - Used to classify IP blocks by functionality.72*73* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family74* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller75* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler76* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller77* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor78* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine79* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine80* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine81* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder82* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine83* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor84* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next85* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler86* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine87* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine88* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia89* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor90* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types91*/92enum amd_ip_block_type {93 AMD_IP_BLOCK_TYPE_COMMON,94 AMD_IP_BLOCK_TYPE_GMC,95 AMD_IP_BLOCK_TYPE_IH,96 AMD_IP_BLOCK_TYPE_SMC,97 AMD_IP_BLOCK_TYPE_PSP,98 AMD_IP_BLOCK_TYPE_DCE,99 AMD_IP_BLOCK_TYPE_GFX,100 AMD_IP_BLOCK_TYPE_SDMA,101 AMD_IP_BLOCK_TYPE_UVD,102 AMD_IP_BLOCK_TYPE_VCE,103 AMD_IP_BLOCK_TYPE_ACP,104 AMD_IP_BLOCK_TYPE_VCN,105 AMD_IP_BLOCK_TYPE_MES,106 AMD_IP_BLOCK_TYPE_JPEG,107 AMD_IP_BLOCK_TYPE_VPE,108 AMD_IP_BLOCK_TYPE_UMSCH_MM,109 AMD_IP_BLOCK_TYPE_ISP,110 AMD_IP_BLOCK_TYPE_NUM,111};112 113enum amd_clockgating_state {114 AMD_CG_STATE_GATE = 0,115 AMD_CG_STATE_UNGATE,116};117 118 119enum amd_powergating_state {120 AMD_PG_STATE_GATE = 0,121 AMD_PG_STATE_UNGATE,122};123 124 125/* CG flags */126#define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0)127#define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1)128#define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2)129#define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3)130#define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4)131#define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5)132#define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6)133#define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7)134#define AMD_CG_SUPPORT_MC_LS (1ULL << 8)135#define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9)136#define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10)137#define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11)138#define AMD_CG_SUPPORT_BIF_LS (1ULL << 12)139#define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13)140#define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14)141#define AMD_CG_SUPPORT_HDP_LS (1ULL << 15)142#define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16)143#define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17)144#define AMD_CG_SUPPORT_DRM_LS (1ULL << 18)145#define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19)146#define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20)147#define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21)148#define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22)149#define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23)150#define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24)151#define AMD_CG_SUPPORT_HDP_DS (1ULL << 25)152#define AMD_CG_SUPPORT_HDP_SD (1ULL << 26)153#define AMD_CG_SUPPORT_IH_CG (1ULL << 27)154#define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28)155#define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29)156#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)157#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)158#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)159#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)160/* PG flags */161#define AMD_PG_SUPPORT_GFX_PG (1 << 0)162#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)163#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)164#define AMD_PG_SUPPORT_UVD (1 << 3)165#define AMD_PG_SUPPORT_VCE (1 << 4)166#define AMD_PG_SUPPORT_CP (1 << 5)167#define AMD_PG_SUPPORT_GDS (1 << 6)168#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)169#define AMD_PG_SUPPORT_SDMA (1 << 8)170#define AMD_PG_SUPPORT_ACP (1 << 9)171#define AMD_PG_SUPPORT_SAMU (1 << 10)172#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)173#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)174#define AMD_PG_SUPPORT_MMHUB (1 << 13)175#define AMD_PG_SUPPORT_VCN (1 << 14)176#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)177#define AMD_PG_SUPPORT_ATHUB (1 << 16)178#define AMD_PG_SUPPORT_JPEG (1 << 17)179#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)180#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)181 182/**183 * enum PP_FEATURE_MASK - Used to mask power play features.184 *185 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.186 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.187 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.188 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.189 * @PP_POWER_CONTAINMENT_MASK: Power containment.190 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.191 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.192 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.193 * @PP_ULV_MASK: Ultra low voltage.194 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.195 * @PP_CLOCK_STRETCH_MASK: Clock stretching.196 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.197 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.198 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.199 * @PP_OVERDRIVE_MASK: Over- and under-clocking support.200 * @PP_GFXOFF_MASK: Dynamic graphics engine power control.201 * @PP_ACG_MASK: Adaptive clock generator.202 * @PP_STUTTER_MODE: Stutter mode.203 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.204 * @PP_GFX_DCS_MASK: GFX Async DCS.205 *206 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to207 * the kernel's command line parameters. This is usually done through a system's208 * boot loader (E.g. GRUB). If manually loading the driver, pass209 * ppfeaturemask=<mask> as a modprobe parameter.210 */211enum PP_FEATURE_MASK {212 PP_SCLK_DPM_MASK = 0x1,213 PP_MCLK_DPM_MASK = 0x2,214 PP_PCIE_DPM_MASK = 0x4,215 PP_SCLK_DEEP_SLEEP_MASK = 0x8,216 PP_POWER_CONTAINMENT_MASK = 0x10,217 PP_UVD_HANDSHAKE_MASK = 0x20,218 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,219 PP_VBI_TIME_SUPPORT_MASK = 0x80,220 PP_ULV_MASK = 0x100,221 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,222 PP_CLOCK_STRETCH_MASK = 0x400,223 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,224 PP_SOCCLK_DPM_MASK = 0x1000,225 PP_DCEFCLK_DPM_MASK = 0x2000,226 PP_OVERDRIVE_MASK = 0x4000,227 PP_GFXOFF_MASK = 0x8000,228 PP_ACG_MASK = 0x10000,229 PP_STUTTER_MODE = 0x20000,230 PP_AVFS_MASK = 0x40000,231 PP_GFX_DCS_MASK = 0x80000,232};233 234enum amd_harvest_ip_mask {235 AMD_HARVEST_IP_VCN_MASK = 0x1,236 AMD_HARVEST_IP_JPEG_MASK = 0x2,237 AMD_HARVEST_IP_DMU_MASK = 0x4,238};239 240enum DC_FEATURE_MASK {241 //Default value can be found at "uint amdgpu_dc_feature_mask"242 DC_FBC_MASK = (1 << 0), //0x1, disabled by default243 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default244 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default245 DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1246 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default247 DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default248 DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default249 DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default250 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default251 DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4252};253 254/**255 * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP256 */257enum DC_DEBUG_MASK {258 /**259 * @DC_DISABLE_PIPE_SPLIT: If set, disable pipe-splitting260 */261 DC_DISABLE_PIPE_SPLIT = 0x1,262 263 /**264 * @DC_DISABLE_STUTTER: If set, disable memory stutter mode265 */266 DC_DISABLE_STUTTER = 0x2,267 268 /**269 * @DC_DISABLE_DSC: If set, disable display stream compression270 */271 DC_DISABLE_DSC = 0x4,272 273 /**274 * @DC_DISABLE_CLOCK_GATING: If set, disable clock gating optimizations275 */276 DC_DISABLE_CLOCK_GATING = 0x8,277 278 /**279 * @DC_DISABLE_PSR: If set, disable Panel self refresh v1 and PSR-SU280 */281 DC_DISABLE_PSR = 0x10,282 283 /**284 * @DC_FORCE_SUBVP_MCLK_SWITCH: If set, force mclk switch in subvp, even285 * if mclk switch in vblank is possible286 */287 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,288 289 /**290 * @DC_DISABLE_MPO: If set, disable multi-plane offloading291 */292 DC_DISABLE_MPO = 0x40,293 294 /**295 * @DC_ENABLE_DPIA_TRACE: If set, enable trace logging for DPIA296 */297 DC_ENABLE_DPIA_TRACE = 0x80,298 299 /**300 * @DC_ENABLE_DML2: If set, force usage of DML2, even if the DCN version301 * does not default to it.302 */303 DC_ENABLE_DML2 = 0x100,304 305 /**306 * @DC_DISABLE_PSR_SU: If set, disable PSR SU307 */308 DC_DISABLE_PSR_SU = 0x200,309 310 /**311 * @DC_DISABLE_REPLAY: If set, disable Panel Replay312 */313 DC_DISABLE_REPLAY = 0x400,314 315 /**316 * @DC_DISABLE_IPS: If set, disable all Idle Power States, all the time.317 * If more than one IPS debug bit is set, the lowest bit takes318 * precedence. For example, if DC_FORCE_IPS_ENABLE and319 * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes320 * precedence.321 */322 DC_DISABLE_IPS = 0x800,323 324 /**325 * @DC_DISABLE_IPS_DYNAMIC: If set, disable all IPS, all the time,326 * *except* when driver goes into suspend.327 */328 DC_DISABLE_IPS_DYNAMIC = 0x1000,329 330 /**331 * @DC_DISABLE_IPS2_DYNAMIC: If set, disable IPS2 (IPS1 allowed) if332 * there is an enabled display. Otherwise, enable all IPS.333 */334 DC_DISABLE_IPS2_DYNAMIC = 0x2000,335 336 /**337 * @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the time.338 */339 DC_FORCE_IPS_ENABLE = 0x4000,340};341 342enum amd_dpm_forced_level;343 344/**345 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks346 * @name: Name of IP block347 * @early_init: sets up early driver state (pre sw_init),348 * does not configure hw - Optional349 * @late_init: sets up late driver/hw state (post hw_init) - Optional350 * @sw_init: sets up driver state, does not configure hw351 * @sw_fini: tears down driver state, does not configure hw352 * @early_fini: tears down stuff before dev detached from driver353 * @hw_init: sets up the hw state354 * @hw_fini: tears down the hw state355 * @late_fini: final cleanup356 * @prepare_suspend: handle IP specific changes to prepare for suspend357 * (such as allocating any required memory)358 * @suspend: handles IP specific hw/sw changes for suspend359 * @resume: handles IP specific hw/sw changes for resume360 * @is_idle: returns current IP block idle status361 * @wait_for_idle: poll for idle362 * @check_soft_reset: check soft reset the IP block363 * @pre_soft_reset: pre soft reset the IP block364 * @soft_reset: soft reset the IP block365 * @post_soft_reset: post soft reset the IP block366 * @set_clockgating_state: enable/disable cg for the IP block367 * @set_powergating_state: enable/disable pg for the IP block368 * @get_clockgating_state: get current clockgating status369 * @dump_ip_state: dump the IP state of the ASIC during a gpu hang370 * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC371 *372 * These hooks provide an interface for controlling the operational state373 * of IP blocks. After acquiring a list of IP blocks for the GPU in use,374 * the driver can make chip-wide state changes by walking this list and375 * making calls to hooks from each IP block. This list is ordered to ensure376 * that the driver initializes the IP blocks in a safe sequence.377 */378struct amd_ip_funcs {379 char *name;380 int (*early_init)(void *handle);381 int (*late_init)(void *handle);382 int (*sw_init)(void *handle);383 int (*sw_fini)(void *handle);384 int (*early_fini)(void *handle);385 int (*hw_init)(void *handle);386 int (*hw_fini)(void *handle);387 void (*late_fini)(void *handle);388 int (*prepare_suspend)(void *handle);389 int (*suspend)(void *handle);390 int (*resume)(void *handle);391 bool (*is_idle)(void *handle);392 int (*wait_for_idle)(void *handle);393 bool (*check_soft_reset)(void *handle);394 int (*pre_soft_reset)(void *handle);395 int (*soft_reset)(void *handle);396 int (*post_soft_reset)(void *handle);397 int (*set_clockgating_state)(void *handle,398 enum amd_clockgating_state state);399 int (*set_powergating_state)(void *handle,400 enum amd_powergating_state state);401 void (*get_clockgating_state)(void *handle, u64 *flags);402 void (*dump_ip_state)(void *handle);403 void (*print_ip_state)(void *handle, struct drm_printer *p);404};405 406 407#endif /* __AMD_SHARED_H__ */408