1649 lines · c
1/*2 * Copyright (C) 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included12 * in all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.20 */21#ifndef _arct_ip_offset_HEADER22#define _arct_ip_offset_HEADER23 24#define MAX_INSTANCE 825#define MAX_SEGMENT 626 27 28struct IP_BASE_INSTANCE {29 unsigned int segment[MAX_SEGMENT];30} __maybe_unused;31 32struct IP_BASE {33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];34} __maybe_unused;35 36 37static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },38 { { 0, 0, 0, 0, 0, 0 } },39 { { 0, 0, 0, 0, 0, 0 } },40 { { 0, 0, 0, 0, 0, 0 } },41 { { 0, 0, 0, 0, 0, 0 } },42 { { 0, 0, 0, 0, 0, 0 } },43 { { 0, 0, 0, 0, 0, 0 } },44 { { 0, 0, 0, 0, 0, 0 } } } };45static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },46 { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },47 { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },48 { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },49 { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },50 { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },51 { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },52 { { 0, 0, 0, 0, 0, 0 } } } };53static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },54 { { 0, 0, 0, 0, 0, 0 } },55 { { 0, 0, 0, 0, 0, 0 } },56 { { 0, 0, 0, 0, 0, 0 } },57 { { 0, 0, 0, 0, 0, 0 } },58 { { 0, 0, 0, 0, 0, 0 } },59 { { 0, 0, 0, 0, 0, 0 } },60 { { 0, 0, 0, 0, 0, 0 } } } };61static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },62 { { 0, 0, 0, 0, 0, 0 } },63 { { 0, 0, 0, 0, 0, 0 } },64 { { 0, 0, 0, 0, 0, 0 } },65 { { 0, 0, 0, 0, 0, 0 } },66 { { 0, 0, 0, 0, 0, 0 } },67 { { 0, 0, 0, 0, 0, 0 } },68 { { 0, 0, 0, 0, 0, 0 } } } };69static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },70 { { 0, 0, 0, 0, 0, 0 } },71 { { 0, 0, 0, 0, 0, 0 } },72 { { 0, 0, 0, 0, 0, 0 } },73 { { 0, 0, 0, 0, 0, 0 } },74 { { 0, 0, 0, 0, 0, 0 } },75 { { 0, 0, 0, 0, 0, 0 } },76 { { 0, 0, 0, 0, 0, 0 } } } };77static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },78 { { 0, 0, 0, 0, 0, 0 } },79 { { 0, 0, 0, 0, 0, 0 } },80 { { 0, 0, 0, 0, 0, 0 } },81 { { 0, 0, 0, 0, 0, 0 } },82 { { 0, 0, 0, 0, 0, 0 } },83 { { 0, 0, 0, 0, 0, 0 } },84 { { 0, 0, 0, 0, 0, 0 } } } };85static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },86 { { 0, 0, 0, 0, 0, 0 } },87 { { 0, 0, 0, 0, 0, 0 } },88 { { 0, 0, 0, 0, 0, 0 } },89 { { 0, 0, 0, 0, 0, 0 } },90 { { 0, 0, 0, 0, 0, 0 } },91 { { 0, 0, 0, 0, 0, 0 } },92 { { 0, 0, 0, 0, 0, 0 } } } };93static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },94 { { 0, 0, 0, 0, 0, 0 } },95 { { 0, 0, 0, 0, 0, 0 } },96 { { 0, 0, 0, 0, 0, 0 } },97 { { 0, 0, 0, 0, 0, 0 } },98 { { 0, 0, 0, 0, 0, 0 } },99 { { 0, 0, 0, 0, 0, 0 } },100 { { 0, 0, 0, 0, 0, 0 } } } };101static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },102 { { 0, 0, 0, 0, 0, 0 } },103 { { 0, 0, 0, 0, 0, 0 } },104 { { 0, 0, 0, 0, 0, 0 } },105 { { 0, 0, 0, 0, 0, 0 } },106 { { 0, 0, 0, 0, 0, 0 } },107 { { 0, 0, 0, 0, 0, 0 } },108 { { 0, 0, 0, 0, 0, 0 } } } };109static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },110 { { 0, 0, 0, 0, 0, 0 } },111 { { 0, 0, 0, 0, 0, 0 } },112 { { 0, 0, 0, 0, 0, 0 } },113 { { 0, 0, 0, 0, 0, 0 } },114 { { 0, 0, 0, 0, 0, 0 } },115 { { 0, 0, 0, 0, 0, 0 } },116 { { 0, 0, 0, 0, 0, 0 } } } };117static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },118 { { 0, 0, 0, 0, 0, 0 } },119 { { 0, 0, 0, 0, 0, 0 } },120 { { 0, 0, 0, 0, 0, 0 } },121 { { 0, 0, 0, 0, 0, 0 } },122 { { 0, 0, 0, 0, 0, 0 } },123 { { 0, 0, 0, 0, 0, 0 } },124 { { 0, 0, 0, 0, 0, 0 } } } };125static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },126 { { 0, 0, 0, 0, 0, 0 } },127 { { 0, 0, 0, 0, 0, 0 } },128 { { 0, 0, 0, 0, 0, 0 } },129 { { 0, 0, 0, 0, 0, 0 } },130 { { 0, 0, 0, 0, 0, 0 } },131 { { 0, 0, 0, 0, 0, 0 } },132 { { 0, 0, 0, 0, 0, 0 } } } };133static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },134 { { 0, 0, 0, 0, 0, 0 } },135 { { 0, 0, 0, 0, 0, 0 } },136 { { 0, 0, 0, 0, 0, 0 } },137 { { 0, 0, 0, 0, 0, 0 } },138 { { 0, 0, 0, 0, 0, 0 } },139 { { 0, 0, 0, 0, 0, 0 } },140 { { 0, 0, 0, 0, 0, 0 } } } };141static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },142 { { 0, 0, 0, 0, 0, 0 } },143 { { 0, 0, 0, 0, 0, 0 } },144 { { 0, 0, 0, 0, 0, 0 } },145 { { 0, 0, 0, 0, 0, 0 } },146 { { 0, 0, 0, 0, 0, 0 } },147 { { 0, 0, 0, 0, 0, 0 } },148 { { 0, 0, 0, 0, 0, 0 } } } };149static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },150 { { 0, 0, 0, 0, 0, 0 } },151 { { 0, 0, 0, 0, 0, 0 } },152 { { 0, 0, 0, 0, 0, 0 } },153 { { 0, 0, 0, 0, 0, 0 } },154 { { 0, 0, 0, 0, 0, 0 } },155 { { 0, 0, 0, 0, 0, 0 } },156 { { 0, 0, 0, 0, 0, 0 } } } };157static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },158 { { 0, 0, 0, 0, 0, 0 } },159 { { 0, 0, 0, 0, 0, 0 } },160 { { 0, 0, 0, 0, 0, 0 } },161 { { 0, 0, 0, 0, 0, 0 } },162 { { 0, 0, 0, 0, 0, 0 } },163 { { 0, 0, 0, 0, 0, 0 } },164 { { 0, 0, 0, 0, 0, 0 } } } };165static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },166 { { 0, 0, 0, 0, 0, 0 } },167 { { 0, 0, 0, 0, 0, 0 } },168 { { 0, 0, 0, 0, 0, 0 } },169 { { 0, 0, 0, 0, 0, 0 } },170 { { 0, 0, 0, 0, 0, 0 } },171 { { 0, 0, 0, 0, 0, 0 } },172 { { 0, 0, 0, 0, 0, 0 } } } };173static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },174 { { 0, 0, 0, 0, 0, 0 } },175 { { 0, 0, 0, 0, 0, 0 } },176 { { 0, 0, 0, 0, 0, 0 } },177 { { 0, 0, 0, 0, 0, 0 } },178 { { 0, 0, 0, 0, 0, 0 } },179 { { 0, 0, 0, 0, 0, 0 } },180 { { 0, 0, 0, 0, 0, 0 } } } };181static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },182 { { 0, 0, 0, 0, 0, 0 } },183 { { 0, 0, 0, 0, 0, 0 } },184 { { 0, 0, 0, 0, 0, 0 } },185 { { 0, 0, 0, 0, 0, 0 } },186 { { 0, 0, 0, 0, 0, 0 } },187 { { 0, 0, 0, 0, 0, 0 } },188 { { 0, 0, 0, 0, 0, 0 } } } };189static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },190 { { 0, 0, 0, 0, 0, 0 } },191 { { 0, 0, 0, 0, 0, 0 } },192 { { 0, 0, 0, 0, 0, 0 } },193 { { 0, 0, 0, 0, 0, 0 } },194 { { 0, 0, 0, 0, 0, 0 } },195 { { 0, 0, 0, 0, 0, 0 } },196 { { 0, 0, 0, 0, 0, 0 } } } };197static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },198 { { 0, 0, 0, 0, 0, 0 } },199 { { 0, 0, 0, 0, 0, 0 } },200 { { 0, 0, 0, 0, 0, 0 } },201 { { 0, 0, 0, 0, 0, 0 } },202 { { 0, 0, 0, 0, 0, 0 } } } };203static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },204 { { 0, 0, 0, 0, 0, 0 } },205 { { 0, 0, 0, 0, 0, 0 } },206 { { 0, 0, 0, 0, 0, 0 } },207 { { 0, 0, 0, 0, 0, 0 } },208 { { 0, 0, 0, 0, 0, 0 } } } };209static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },210 { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },211 { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },212 { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },213 { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },214 { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },215 { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },216 { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };217static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },218 { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },219 { { 0, 0, 0, 0, 0, 0 } },220 { { 0, 0, 0, 0, 0, 0 } },221 { { 0, 0, 0, 0, 0, 0 } },222 { { 0, 0, 0, 0, 0, 0 } },223 { { 0, 0, 0, 0, 0, 0 } },224 { { 0, 0, 0, 0, 0, 0 } } } };225static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },226 { { 0, 0, 0, 0, 0, 0 } },227 { { 0, 0, 0, 0, 0, 0 } },228 { { 0, 0, 0, 0, 0, 0 } },229 { { 0, 0, 0, 0, 0, 0 } },230 { { 0, 0, 0, 0, 0, 0 } },231 { { 0, 0, 0, 0, 0, 0 } },232 { { 0, 0, 0, 0, 0, 0 } } } };233static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },234 { { 0, 0, 0, 0, 0, 0 } },235 { { 0, 0, 0, 0, 0, 0 } },236 { { 0, 0, 0, 0, 0, 0 } },237 { { 0, 0, 0, 0, 0, 0 } },238 { { 0, 0, 0, 0, 0, 0 } },239 { { 0, 0, 0, 0, 0, 0 } },240 { { 0, 0, 0, 0, 0, 0 } } } };241 242 243 244#define ATHUB_BASE__INST0_SEG0 0x00000C20245#define ATHUB_BASE__INST0_SEG1 0x00012460246#define ATHUB_BASE__INST0_SEG2 0x00408C00247#define ATHUB_BASE__INST0_SEG3 0248#define ATHUB_BASE__INST0_SEG4 0249#define ATHUB_BASE__INST0_SEG5 0250 251#define ATHUB_BASE__INST1_SEG0 0252#define ATHUB_BASE__INST1_SEG1 0253#define ATHUB_BASE__INST1_SEG2 0254#define ATHUB_BASE__INST1_SEG3 0255#define ATHUB_BASE__INST1_SEG4 0256#define ATHUB_BASE__INST1_SEG5 0257 258#define ATHUB_BASE__INST2_SEG0 0259#define ATHUB_BASE__INST2_SEG1 0260#define ATHUB_BASE__INST2_SEG2 0261#define ATHUB_BASE__INST2_SEG3 0262#define ATHUB_BASE__INST2_SEG4 0263#define ATHUB_BASE__INST2_SEG5 0264 265#define ATHUB_BASE__INST3_SEG0 0266#define ATHUB_BASE__INST3_SEG1 0267#define ATHUB_BASE__INST3_SEG2 0268#define ATHUB_BASE__INST3_SEG3 0269#define ATHUB_BASE__INST3_SEG4 0270#define ATHUB_BASE__INST3_SEG5 0271 272#define ATHUB_BASE__INST4_SEG0 0273#define ATHUB_BASE__INST4_SEG1 0274#define ATHUB_BASE__INST4_SEG2 0275#define ATHUB_BASE__INST4_SEG3 0276#define ATHUB_BASE__INST4_SEG4 0277#define ATHUB_BASE__INST4_SEG5 0278 279#define ATHUB_BASE__INST5_SEG0 0280#define ATHUB_BASE__INST5_SEG1 0281#define ATHUB_BASE__INST5_SEG2 0282#define ATHUB_BASE__INST5_SEG3 0283#define ATHUB_BASE__INST5_SEG4 0284#define ATHUB_BASE__INST5_SEG5 0285 286#define ATHUB_BASE__INST6_SEG0 0287#define ATHUB_BASE__INST6_SEG1 0288#define ATHUB_BASE__INST6_SEG2 0289#define ATHUB_BASE__INST6_SEG3 0290#define ATHUB_BASE__INST6_SEG4 0291#define ATHUB_BASE__INST6_SEG5 0292 293#define ATHUB_BASE__INST7_SEG0 0294#define ATHUB_BASE__INST7_SEG1 0295#define ATHUB_BASE__INST7_SEG2 0296#define ATHUB_BASE__INST7_SEG3 0297#define ATHUB_BASE__INST7_SEG4 0298#define ATHUB_BASE__INST7_SEG5 0299 300#define CLK_BASE__INST0_SEG0 0x000120C0301#define CLK_BASE__INST0_SEG1 0x00016C00302#define CLK_BASE__INST0_SEG2 0x00401800303#define CLK_BASE__INST0_SEG3 0304#define CLK_BASE__INST0_SEG4 0305#define CLK_BASE__INST0_SEG5 0306 307#define CLK_BASE__INST1_SEG0 0x000120E0308#define CLK_BASE__INST1_SEG1 0x00016E00309#define CLK_BASE__INST1_SEG2 0x00401C00310#define CLK_BASE__INST1_SEG3 0311#define CLK_BASE__INST1_SEG4 0312#define CLK_BASE__INST1_SEG5 0313 314#define CLK_BASE__INST2_SEG0 0x00012100315#define CLK_BASE__INST2_SEG1 0x00017000316#define CLK_BASE__INST2_SEG2 0x00402000317#define CLK_BASE__INST2_SEG3 0318#define CLK_BASE__INST2_SEG4 0319#define CLK_BASE__INST2_SEG5 0320 321#define CLK_BASE__INST3_SEG0 0x00012120322#define CLK_BASE__INST3_SEG1 0x00017200323#define CLK_BASE__INST3_SEG2 0x00402400324#define CLK_BASE__INST3_SEG3 0325#define CLK_BASE__INST3_SEG4 0326#define CLK_BASE__INST3_SEG5 0327 328#define CLK_BASE__INST4_SEG0 0x000136C0329#define CLK_BASE__INST4_SEG1 0x0001B000330#define CLK_BASE__INST4_SEG2 0x0042D800331#define CLK_BASE__INST4_SEG3 0332#define CLK_BASE__INST4_SEG4 0333#define CLK_BASE__INST4_SEG5 0334 335#define CLK_BASE__INST5_SEG0 0x00013720336#define CLK_BASE__INST5_SEG1 0x0001B200337#define CLK_BASE__INST5_SEG2 0x0042E400338#define CLK_BASE__INST5_SEG3 0339#define CLK_BASE__INST5_SEG4 0340#define CLK_BASE__INST5_SEG5 0341 342#define CLK_BASE__INST6_SEG0 0x000125E0343#define CLK_BASE__INST6_SEG1 0x00017E00344#define CLK_BASE__INST6_SEG2 0x0040BC00345#define CLK_BASE__INST6_SEG3 0346#define CLK_BASE__INST6_SEG4 0347#define CLK_BASE__INST6_SEG5 0348 349#define CLK_BASE__INST7_SEG0 0350#define CLK_BASE__INST7_SEG1 0351#define CLK_BASE__INST7_SEG2 0352#define CLK_BASE__INST7_SEG3 0353#define CLK_BASE__INST7_SEG4 0354#define CLK_BASE__INST7_SEG5 0355 356#define DF_BASE__INST0_SEG0 0x00007000357#define DF_BASE__INST0_SEG1 0x000125C0358#define DF_BASE__INST0_SEG2 0x0040B800359#define DF_BASE__INST0_SEG3 0360#define DF_BASE__INST0_SEG4 0361#define DF_BASE__INST0_SEG5 0362 363#define DF_BASE__INST1_SEG0 0364#define DF_BASE__INST1_SEG1 0365#define DF_BASE__INST1_SEG2 0366#define DF_BASE__INST1_SEG3 0367#define DF_BASE__INST1_SEG4 0368#define DF_BASE__INST1_SEG5 0369 370#define DF_BASE__INST2_SEG0 0371#define DF_BASE__INST2_SEG1 0372#define DF_BASE__INST2_SEG2 0373#define DF_BASE__INST2_SEG3 0374#define DF_BASE__INST2_SEG4 0375#define DF_BASE__INST2_SEG5 0376 377#define DF_BASE__INST3_SEG0 0378#define DF_BASE__INST3_SEG1 0379#define DF_BASE__INST3_SEG2 0380#define DF_BASE__INST3_SEG3 0381#define DF_BASE__INST3_SEG4 0382#define DF_BASE__INST3_SEG5 0383 384#define DF_BASE__INST4_SEG0 0385#define DF_BASE__INST4_SEG1 0386#define DF_BASE__INST4_SEG2 0387#define DF_BASE__INST4_SEG3 0388#define DF_BASE__INST4_SEG4 0389#define DF_BASE__INST4_SEG5 0390 391#define DF_BASE__INST5_SEG0 0392#define DF_BASE__INST5_SEG1 0393#define DF_BASE__INST5_SEG2 0394#define DF_BASE__INST5_SEG3 0395#define DF_BASE__INST5_SEG4 0396#define DF_BASE__INST5_SEG5 0397 398#define DF_BASE__INST6_SEG0 0399#define DF_BASE__INST6_SEG1 0400#define DF_BASE__INST6_SEG2 0401#define DF_BASE__INST6_SEG3 0402#define DF_BASE__INST6_SEG4 0403#define DF_BASE__INST6_SEG5 0404 405#define DF_BASE__INST7_SEG0 0406#define DF_BASE__INST7_SEG1 0407#define DF_BASE__INST7_SEG2 0408#define DF_BASE__INST7_SEG3 0409#define DF_BASE__INST7_SEG4 0410#define DF_BASE__INST7_SEG5 0411 412#define FUSE_BASE__INST0_SEG0 0x000120A0413#define FUSE_BASE__INST0_SEG1 0x00017400414#define FUSE_BASE__INST0_SEG2 0x00401400415#define FUSE_BASE__INST0_SEG3 0416#define FUSE_BASE__INST0_SEG4 0417#define FUSE_BASE__INST0_SEG5 0418 419#define FUSE_BASE__INST1_SEG0 0420#define FUSE_BASE__INST1_SEG1 0421#define FUSE_BASE__INST1_SEG2 0422#define FUSE_BASE__INST1_SEG3 0423#define FUSE_BASE__INST1_SEG4 0424#define FUSE_BASE__INST1_SEG5 0425 426#define FUSE_BASE__INST2_SEG0 0427#define FUSE_BASE__INST2_SEG1 0428#define FUSE_BASE__INST2_SEG2 0429#define FUSE_BASE__INST2_SEG3 0430#define FUSE_BASE__INST2_SEG4 0431#define FUSE_BASE__INST2_SEG5 0432 433#define FUSE_BASE__INST3_SEG0 0434#define FUSE_BASE__INST3_SEG1 0435#define FUSE_BASE__INST3_SEG2 0436#define FUSE_BASE__INST3_SEG3 0437#define FUSE_BASE__INST3_SEG4 0438#define FUSE_BASE__INST3_SEG5 0439 440#define FUSE_BASE__INST4_SEG0 0441#define FUSE_BASE__INST4_SEG1 0442#define FUSE_BASE__INST4_SEG2 0443#define FUSE_BASE__INST4_SEG3 0444#define FUSE_BASE__INST4_SEG4 0445#define FUSE_BASE__INST4_SEG5 0446 447#define FUSE_BASE__INST5_SEG0 0448#define FUSE_BASE__INST5_SEG1 0449#define FUSE_BASE__INST5_SEG2 0450#define FUSE_BASE__INST5_SEG3 0451#define FUSE_BASE__INST5_SEG4 0452#define FUSE_BASE__INST5_SEG5 0453 454#define FUSE_BASE__INST6_SEG0 0455#define FUSE_BASE__INST6_SEG1 0456#define FUSE_BASE__INST6_SEG2 0457#define FUSE_BASE__INST6_SEG3 0458#define FUSE_BASE__INST6_SEG4 0459#define FUSE_BASE__INST6_SEG5 0460 461#define FUSE_BASE__INST7_SEG0 0462#define FUSE_BASE__INST7_SEG1 0463#define FUSE_BASE__INST7_SEG2 0464#define FUSE_BASE__INST7_SEG3 0465#define FUSE_BASE__INST7_SEG4 0466#define FUSE_BASE__INST7_SEG5 0467 468#define GC_BASE__INST0_SEG0 0x00002000469#define GC_BASE__INST0_SEG1 0x0000A000470#define GC_BASE__INST0_SEG2 0x00012160471#define GC_BASE__INST0_SEG3 0x00402C00472#define GC_BASE__INST0_SEG4 0473#define GC_BASE__INST0_SEG5 0474 475#define GC_BASE__INST1_SEG0 0476#define GC_BASE__INST1_SEG1 0477#define GC_BASE__INST1_SEG2 0478#define GC_BASE__INST1_SEG3 0479#define GC_BASE__INST1_SEG4 0480#define GC_BASE__INST1_SEG5 0481 482#define GC_BASE__INST2_SEG0 0483#define GC_BASE__INST2_SEG1 0484#define GC_BASE__INST2_SEG2 0485#define GC_BASE__INST2_SEG3 0486#define GC_BASE__INST2_SEG4 0487#define GC_BASE__INST2_SEG5 0488 489#define GC_BASE__INST3_SEG0 0490#define GC_BASE__INST3_SEG1 0491#define GC_BASE__INST3_SEG2 0492#define GC_BASE__INST3_SEG3 0493#define GC_BASE__INST3_SEG4 0494#define GC_BASE__INST3_SEG5 0495 496#define GC_BASE__INST4_SEG0 0497#define GC_BASE__INST4_SEG1 0498#define GC_BASE__INST4_SEG2 0499#define GC_BASE__INST4_SEG3 0500#define GC_BASE__INST4_SEG4 0501#define GC_BASE__INST4_SEG5 0502 503#define GC_BASE__INST5_SEG0 0504#define GC_BASE__INST5_SEG1 0505#define GC_BASE__INST5_SEG2 0506#define GC_BASE__INST5_SEG3 0507#define GC_BASE__INST5_SEG4 0508#define GC_BASE__INST5_SEG5 0509 510#define GC_BASE__INST6_SEG0 0511#define GC_BASE__INST6_SEG1 0512#define GC_BASE__INST6_SEG2 0513#define GC_BASE__INST6_SEG3 0514#define GC_BASE__INST6_SEG4 0515#define GC_BASE__INST6_SEG5 0516 517#define GC_BASE__INST7_SEG0 0518#define GC_BASE__INST7_SEG1 0519#define GC_BASE__INST7_SEG2 0520#define GC_BASE__INST7_SEG3 0521#define GC_BASE__INST7_SEG4 0522#define GC_BASE__INST7_SEG5 0523 524#define HDP_BASE__INST0_SEG0 0x00000F20525#define HDP_BASE__INST0_SEG1 0x00012520526#define HDP_BASE__INST0_SEG2 0x0040A400527#define HDP_BASE__INST0_SEG3 0528#define HDP_BASE__INST0_SEG4 0529#define HDP_BASE__INST0_SEG5 0530 531#define HDP_BASE__INST1_SEG0 0532#define HDP_BASE__INST1_SEG1 0533#define HDP_BASE__INST1_SEG2 0534#define HDP_BASE__INST1_SEG3 0535#define HDP_BASE__INST1_SEG4 0536#define HDP_BASE__INST1_SEG5 0537 538#define HDP_BASE__INST2_SEG0 0539#define HDP_BASE__INST2_SEG1 0540#define HDP_BASE__INST2_SEG2 0541#define HDP_BASE__INST2_SEG3 0542#define HDP_BASE__INST2_SEG4 0543#define HDP_BASE__INST2_SEG5 0544 545#define HDP_BASE__INST3_SEG0 0546#define HDP_BASE__INST3_SEG1 0547#define HDP_BASE__INST3_SEG2 0548#define HDP_BASE__INST3_SEG3 0549#define HDP_BASE__INST3_SEG4 0550#define HDP_BASE__INST3_SEG5 0551 552#define HDP_BASE__INST4_SEG0 0553#define HDP_BASE__INST4_SEG1 0554#define HDP_BASE__INST4_SEG2 0555#define HDP_BASE__INST4_SEG3 0556#define HDP_BASE__INST4_SEG4 0557#define HDP_BASE__INST4_SEG5 0558 559#define HDP_BASE__INST5_SEG0 0560#define HDP_BASE__INST5_SEG1 0561#define HDP_BASE__INST5_SEG2 0562#define HDP_BASE__INST5_SEG3 0563#define HDP_BASE__INST5_SEG4 0564#define HDP_BASE__INST5_SEG5 0565 566#define HDP_BASE__INST6_SEG0 0567#define HDP_BASE__INST6_SEG1 0568#define HDP_BASE__INST6_SEG2 0569#define HDP_BASE__INST6_SEG3 0570#define HDP_BASE__INST6_SEG4 0571#define HDP_BASE__INST6_SEG5 0572 573#define HDP_BASE__INST7_SEG0 0574#define HDP_BASE__INST7_SEG1 0575#define HDP_BASE__INST7_SEG2 0576#define HDP_BASE__INST7_SEG3 0577#define HDP_BASE__INST7_SEG4 0578#define HDP_BASE__INST7_SEG5 0579 580#define MMHUB_BASE__INST0_SEG0 0x00012440581#define MMHUB_BASE__INST0_SEG1 0x0001A000582#define MMHUB_BASE__INST0_SEG2 0x00408800583#define MMHUB_BASE__INST0_SEG3 0584#define MMHUB_BASE__INST0_SEG4 0585#define MMHUB_BASE__INST0_SEG5 0586 587#define MMHUB_BASE__INST1_SEG0 0588#define MMHUB_BASE__INST1_SEG1 0589#define MMHUB_BASE__INST1_SEG2 0590#define MMHUB_BASE__INST1_SEG3 0591#define MMHUB_BASE__INST1_SEG4 0592#define MMHUB_BASE__INST1_SEG5 0593 594#define MMHUB_BASE__INST2_SEG0 0595#define MMHUB_BASE__INST2_SEG1 0596#define MMHUB_BASE__INST2_SEG2 0597#define MMHUB_BASE__INST2_SEG3 0598#define MMHUB_BASE__INST2_SEG4 0599#define MMHUB_BASE__INST2_SEG5 0600 601#define MMHUB_BASE__INST3_SEG0 0602#define MMHUB_BASE__INST3_SEG1 0603#define MMHUB_BASE__INST3_SEG2 0604#define MMHUB_BASE__INST3_SEG3 0605#define MMHUB_BASE__INST3_SEG4 0606#define MMHUB_BASE__INST3_SEG5 0607 608#define MMHUB_BASE__INST4_SEG0 0609#define MMHUB_BASE__INST4_SEG1 0610#define MMHUB_BASE__INST4_SEG2 0611#define MMHUB_BASE__INST4_SEG3 0612#define MMHUB_BASE__INST4_SEG4 0613#define MMHUB_BASE__INST4_SEG5 0614 615#define MMHUB_BASE__INST5_SEG0 0616#define MMHUB_BASE__INST5_SEG1 0617#define MMHUB_BASE__INST5_SEG2 0618#define MMHUB_BASE__INST5_SEG3 0619#define MMHUB_BASE__INST5_SEG4 0620#define MMHUB_BASE__INST5_SEG5 0621 622#define MMHUB_BASE__INST6_SEG0 0623#define MMHUB_BASE__INST6_SEG1 0624#define MMHUB_BASE__INST6_SEG2 0625#define MMHUB_BASE__INST6_SEG3 0626#define MMHUB_BASE__INST6_SEG4 0627#define MMHUB_BASE__INST6_SEG5 0628 629#define MMHUB_BASE__INST7_SEG0 0630#define MMHUB_BASE__INST7_SEG1 0631#define MMHUB_BASE__INST7_SEG2 0632#define MMHUB_BASE__INST7_SEG3 0633#define MMHUB_BASE__INST7_SEG4 0634#define MMHUB_BASE__INST7_SEG5 0635 636#define MP0_BASE__INST0_SEG0 0x00013FE0637#define MP0_BASE__INST0_SEG1 0x00016000638#define MP0_BASE__INST0_SEG2 0x0043FC00639#define MP0_BASE__INST0_SEG3 0x00DC0000640#define MP0_BASE__INST0_SEG4 0x00E00000641#define MP0_BASE__INST0_SEG5 0x00E40000642 643#define MP0_BASE__INST1_SEG0 0644#define MP0_BASE__INST1_SEG1 0645#define MP0_BASE__INST1_SEG2 0646#define MP0_BASE__INST1_SEG3 0647#define MP0_BASE__INST1_SEG4 0648#define MP0_BASE__INST1_SEG5 0649 650#define MP0_BASE__INST2_SEG0 0651#define MP0_BASE__INST2_SEG1 0652#define MP0_BASE__INST2_SEG2 0653#define MP0_BASE__INST2_SEG3 0654#define MP0_BASE__INST2_SEG4 0655#define MP0_BASE__INST2_SEG5 0656 657#define MP0_BASE__INST3_SEG0 0658#define MP0_BASE__INST3_SEG1 0659#define MP0_BASE__INST3_SEG2 0660#define MP0_BASE__INST3_SEG3 0661#define MP0_BASE__INST3_SEG4 0662#define MP0_BASE__INST3_SEG5 0663 664#define MP0_BASE__INST4_SEG0 0665#define MP0_BASE__INST4_SEG1 0666#define MP0_BASE__INST4_SEG2 0667#define MP0_BASE__INST4_SEG3 0668#define MP0_BASE__INST4_SEG4 0669#define MP0_BASE__INST4_SEG5 0670 671#define MP0_BASE__INST5_SEG0 0672#define MP0_BASE__INST5_SEG1 0673#define MP0_BASE__INST5_SEG2 0674#define MP0_BASE__INST5_SEG3 0675#define MP0_BASE__INST5_SEG4 0676#define MP0_BASE__INST5_SEG5 0677 678#define MP0_BASE__INST6_SEG0 0679#define MP0_BASE__INST6_SEG1 0680#define MP0_BASE__INST6_SEG2 0681#define MP0_BASE__INST6_SEG3 0682#define MP0_BASE__INST6_SEG4 0683#define MP0_BASE__INST6_SEG5 0684 685#define MP0_BASE__INST7_SEG0 0686#define MP0_BASE__INST7_SEG1 0687#define MP0_BASE__INST7_SEG2 0688#define MP0_BASE__INST7_SEG3 0689#define MP0_BASE__INST7_SEG4 0690#define MP0_BASE__INST7_SEG5 0691 692#define MP1_BASE__INST0_SEG0 0x00012020693#define MP1_BASE__INST0_SEG1 0x00016200694#define MP1_BASE__INST0_SEG2 0x00400400695#define MP1_BASE__INST0_SEG3 0x00E80000696#define MP1_BASE__INST0_SEG4 0x00EC0000697#define MP1_BASE__INST0_SEG5 0x00F00000698 699#define MP1_BASE__INST1_SEG0 0700#define MP1_BASE__INST1_SEG1 0701#define MP1_BASE__INST1_SEG2 0702#define MP1_BASE__INST1_SEG3 0703#define MP1_BASE__INST1_SEG4 0704#define MP1_BASE__INST1_SEG5 0705 706#define MP1_BASE__INST2_SEG0 0707#define MP1_BASE__INST2_SEG1 0708#define MP1_BASE__INST2_SEG2 0709#define MP1_BASE__INST2_SEG3 0710#define MP1_BASE__INST2_SEG4 0711#define MP1_BASE__INST2_SEG5 0712 713#define MP1_BASE__INST3_SEG0 0714#define MP1_BASE__INST3_SEG1 0715#define MP1_BASE__INST3_SEG2 0716#define MP1_BASE__INST3_SEG3 0717#define MP1_BASE__INST3_SEG4 0718#define MP1_BASE__INST3_SEG5 0719 720#define MP1_BASE__INST4_SEG0 0721#define MP1_BASE__INST4_SEG1 0722#define MP1_BASE__INST4_SEG2 0723#define MP1_BASE__INST4_SEG3 0724#define MP1_BASE__INST4_SEG4 0725#define MP1_BASE__INST4_SEG5 0726 727#define MP1_BASE__INST5_SEG0 0728#define MP1_BASE__INST5_SEG1 0729#define MP1_BASE__INST5_SEG2 0730#define MP1_BASE__INST5_SEG3 0731#define MP1_BASE__INST5_SEG4 0732#define MP1_BASE__INST5_SEG5 0733 734#define MP1_BASE__INST6_SEG0 0735#define MP1_BASE__INST6_SEG1 0736#define MP1_BASE__INST6_SEG2 0737#define MP1_BASE__INST6_SEG3 0738#define MP1_BASE__INST6_SEG4 0739#define MP1_BASE__INST6_SEG5 0740 741#define MP1_BASE__INST7_SEG0 0742#define MP1_BASE__INST7_SEG1 0743#define MP1_BASE__INST7_SEG2 0744#define MP1_BASE__INST7_SEG3 0745#define MP1_BASE__INST7_SEG4 0746#define MP1_BASE__INST7_SEG5 0747 748#define NBIF0_BASE__INST0_SEG0 0x00000000749#define NBIF0_BASE__INST0_SEG1 0x00000014750#define NBIF0_BASE__INST0_SEG2 0x00000D20751#define NBIF0_BASE__INST0_SEG3 0x00010400752#define NBIF0_BASE__INST0_SEG4 0x00012D80753#define NBIF0_BASE__INST0_SEG5 0x0041B000754 755#define NBIF0_BASE__INST1_SEG0 0756#define NBIF0_BASE__INST1_SEG1 0757#define NBIF0_BASE__INST1_SEG2 0758#define NBIF0_BASE__INST1_SEG3 0759#define NBIF0_BASE__INST1_SEG4 0760#define NBIF0_BASE__INST1_SEG5 0761 762#define NBIF0_BASE__INST2_SEG0 0763#define NBIF0_BASE__INST2_SEG1 0764#define NBIF0_BASE__INST2_SEG2 0765#define NBIF0_BASE__INST2_SEG3 0766#define NBIF0_BASE__INST2_SEG4 0767#define NBIF0_BASE__INST2_SEG5 0768 769#define NBIF0_BASE__INST3_SEG0 0770#define NBIF0_BASE__INST3_SEG1 0771#define NBIF0_BASE__INST3_SEG2 0772#define NBIF0_BASE__INST3_SEG3 0773#define NBIF0_BASE__INST3_SEG4 0774#define NBIF0_BASE__INST3_SEG5 0775 776#define NBIF0_BASE__INST4_SEG0 0777#define NBIF0_BASE__INST4_SEG1 0778#define NBIF0_BASE__INST4_SEG2 0779#define NBIF0_BASE__INST4_SEG3 0780#define NBIF0_BASE__INST4_SEG4 0781#define NBIF0_BASE__INST4_SEG5 0782 783#define NBIF0_BASE__INST5_SEG0 0784#define NBIF0_BASE__INST5_SEG1 0785#define NBIF0_BASE__INST5_SEG2 0786#define NBIF0_BASE__INST5_SEG3 0787#define NBIF0_BASE__INST5_SEG4 0788#define NBIF0_BASE__INST5_SEG5 0789 790#define NBIF0_BASE__INST6_SEG0 0791#define NBIF0_BASE__INST6_SEG1 0792#define NBIF0_BASE__INST6_SEG2 0793#define NBIF0_BASE__INST6_SEG3 0794#define NBIF0_BASE__INST6_SEG4 0795#define NBIF0_BASE__INST6_SEG5 0796 797#define NBIF0_BASE__INST7_SEG0 0798#define NBIF0_BASE__INST7_SEG1 0799#define NBIF0_BASE__INST7_SEG2 0800#define NBIF0_BASE__INST7_SEG3 0801#define NBIF0_BASE__INST7_SEG4 0802#define NBIF0_BASE__INST7_SEG5 0803 804#define OSSSYS_BASE__INST0_SEG0 0x000010A0805#define OSSSYS_BASE__INST0_SEG1 0x00012500806#define OSSSYS_BASE__INST0_SEG2 0x0040A000807#define OSSSYS_BASE__INST0_SEG3 0808#define OSSSYS_BASE__INST0_SEG4 0809#define OSSSYS_BASE__INST0_SEG5 0810 811#define OSSSYS_BASE__INST1_SEG0 0812#define OSSSYS_BASE__INST1_SEG1 0813#define OSSSYS_BASE__INST1_SEG2 0814#define OSSSYS_BASE__INST1_SEG3 0815#define OSSSYS_BASE__INST1_SEG4 0816#define OSSSYS_BASE__INST1_SEG5 0817 818#define OSSSYS_BASE__INST2_SEG0 0819#define OSSSYS_BASE__INST2_SEG1 0820#define OSSSYS_BASE__INST2_SEG2 0821#define OSSSYS_BASE__INST2_SEG3 0822#define OSSSYS_BASE__INST2_SEG4 0823#define OSSSYS_BASE__INST2_SEG5 0824 825#define OSSSYS_BASE__INST3_SEG0 0826#define OSSSYS_BASE__INST3_SEG1 0827#define OSSSYS_BASE__INST3_SEG2 0828#define OSSSYS_BASE__INST3_SEG3 0829#define OSSSYS_BASE__INST3_SEG4 0830#define OSSSYS_BASE__INST3_SEG5 0831 832#define OSSSYS_BASE__INST4_SEG0 0833#define OSSSYS_BASE__INST4_SEG1 0834#define OSSSYS_BASE__INST4_SEG2 0835#define OSSSYS_BASE__INST4_SEG3 0836#define OSSSYS_BASE__INST4_SEG4 0837#define OSSSYS_BASE__INST4_SEG5 0838 839#define OSSSYS_BASE__INST5_SEG0 0840#define OSSSYS_BASE__INST5_SEG1 0841#define OSSSYS_BASE__INST5_SEG2 0842#define OSSSYS_BASE__INST5_SEG3 0843#define OSSSYS_BASE__INST5_SEG4 0844#define OSSSYS_BASE__INST5_SEG5 0845 846#define OSSSYS_BASE__INST6_SEG0 0847#define OSSSYS_BASE__INST6_SEG1 0848#define OSSSYS_BASE__INST6_SEG2 0849#define OSSSYS_BASE__INST6_SEG3 0850#define OSSSYS_BASE__INST6_SEG4 0851#define OSSSYS_BASE__INST6_SEG5 0852 853#define OSSSYS_BASE__INST7_SEG0 0854#define OSSSYS_BASE__INST7_SEG1 0855#define OSSSYS_BASE__INST7_SEG2 0856#define OSSSYS_BASE__INST7_SEG3 0857#define OSSSYS_BASE__INST7_SEG4 0858#define OSSSYS_BASE__INST7_SEG5 0859 860#define PCIE0_BASE__INST0_SEG0 0x000128C0861#define PCIE0_BASE__INST0_SEG1 0x00411800862#define PCIE0_BASE__INST0_SEG2 0x04440000863#define PCIE0_BASE__INST0_SEG3 0864#define PCIE0_BASE__INST0_SEG4 0865#define PCIE0_BASE__INST0_SEG5 0866 867#define PCIE0_BASE__INST1_SEG0 0868#define PCIE0_BASE__INST1_SEG1 0869#define PCIE0_BASE__INST1_SEG2 0870#define PCIE0_BASE__INST1_SEG3 0871#define PCIE0_BASE__INST1_SEG4 0872#define PCIE0_BASE__INST1_SEG5 0873 874#define PCIE0_BASE__INST2_SEG0 0875#define PCIE0_BASE__INST2_SEG1 0876#define PCIE0_BASE__INST2_SEG2 0877#define PCIE0_BASE__INST2_SEG3 0878#define PCIE0_BASE__INST2_SEG4 0879#define PCIE0_BASE__INST2_SEG5 0880 881#define PCIE0_BASE__INST3_SEG0 0882#define PCIE0_BASE__INST3_SEG1 0883#define PCIE0_BASE__INST3_SEG2 0884#define PCIE0_BASE__INST3_SEG3 0885#define PCIE0_BASE__INST3_SEG4 0886#define PCIE0_BASE__INST3_SEG5 0887 888#define PCIE0_BASE__INST4_SEG0 0889#define PCIE0_BASE__INST4_SEG1 0890#define PCIE0_BASE__INST4_SEG2 0891#define PCIE0_BASE__INST4_SEG3 0892#define PCIE0_BASE__INST4_SEG4 0893#define PCIE0_BASE__INST4_SEG5 0894 895#define PCIE0_BASE__INST5_SEG0 0896#define PCIE0_BASE__INST5_SEG1 0897#define PCIE0_BASE__INST5_SEG2 0898#define PCIE0_BASE__INST5_SEG3 0899#define PCIE0_BASE__INST5_SEG4 0900#define PCIE0_BASE__INST5_SEG5 0901 902#define PCIE0_BASE__INST6_SEG0 0903#define PCIE0_BASE__INST6_SEG1 0904#define PCIE0_BASE__INST6_SEG2 0905#define PCIE0_BASE__INST6_SEG3 0906#define PCIE0_BASE__INST6_SEG4 0907#define PCIE0_BASE__INST6_SEG5 0908 909#define PCIE0_BASE__INST7_SEG0 0910#define PCIE0_BASE__INST7_SEG1 0911#define PCIE0_BASE__INST7_SEG2 0912#define PCIE0_BASE__INST7_SEG3 0913#define PCIE0_BASE__INST7_SEG4 0914#define PCIE0_BASE__INST7_SEG5 0915 916#define SDMA0_BASE__INST0_SEG0 0x00001260917#define SDMA0_BASE__INST0_SEG1 0x00012540918#define SDMA0_BASE__INST0_SEG2 0x0040A800919#define SDMA0_BASE__INST0_SEG3 0920#define SDMA0_BASE__INST0_SEG4 0921#define SDMA0_BASE__INST0_SEG5 0922 923#define SDMA0_BASE__INST1_SEG0 0924#define SDMA0_BASE__INST1_SEG1 0925#define SDMA0_BASE__INST1_SEG2 0926#define SDMA0_BASE__INST1_SEG3 0927#define SDMA0_BASE__INST1_SEG4 0928#define SDMA0_BASE__INST1_SEG5 0929 930#define SDMA0_BASE__INST2_SEG0 0931#define SDMA0_BASE__INST2_SEG1 0932#define SDMA0_BASE__INST2_SEG2 0933#define SDMA0_BASE__INST2_SEG3 0934#define SDMA0_BASE__INST2_SEG4 0935#define SDMA0_BASE__INST2_SEG5 0936 937#define SDMA0_BASE__INST3_SEG0 0938#define SDMA0_BASE__INST3_SEG1 0939#define SDMA0_BASE__INST3_SEG2 0940#define SDMA0_BASE__INST3_SEG3 0941#define SDMA0_BASE__INST3_SEG4 0942#define SDMA0_BASE__INST3_SEG5 0943 944#define SDMA0_BASE__INST4_SEG0 0945#define SDMA0_BASE__INST4_SEG1 0946#define SDMA0_BASE__INST4_SEG2 0947#define SDMA0_BASE__INST4_SEG3 0948#define SDMA0_BASE__INST4_SEG4 0949#define SDMA0_BASE__INST4_SEG5 0950 951#define SDMA0_BASE__INST5_SEG0 0952#define SDMA0_BASE__INST5_SEG1 0953#define SDMA0_BASE__INST5_SEG2 0954#define SDMA0_BASE__INST5_SEG3 0955#define SDMA0_BASE__INST5_SEG4 0956#define SDMA0_BASE__INST5_SEG5 0957 958#define SDMA0_BASE__INST6_SEG0 0959#define SDMA0_BASE__INST6_SEG1 0960#define SDMA0_BASE__INST6_SEG2 0961#define SDMA0_BASE__INST6_SEG3 0962#define SDMA0_BASE__INST6_SEG4 0963#define SDMA0_BASE__INST6_SEG5 0964 965#define SDMA1_BASE__INST0_SEG0 0x00001860966#define SDMA1_BASE__INST0_SEG1 0x00012560967#define SDMA1_BASE__INST0_SEG2 0x0040AC00968#define SDMA1_BASE__INST0_SEG3 0969#define SDMA1_BASE__INST0_SEG4 0970#define SDMA1_BASE__INST0_SEG5 0971 972#define SDMA1_BASE__INST1_SEG0 0973#define SDMA1_BASE__INST1_SEG1 0974#define SDMA1_BASE__INST1_SEG2 0975#define SDMA1_BASE__INST1_SEG3 0976#define SDMA1_BASE__INST1_SEG4 0977#define SDMA1_BASE__INST1_SEG5 0978 979#define SDMA1_BASE__INST2_SEG0 0980#define SDMA1_BASE__INST2_SEG1 0981#define SDMA1_BASE__INST2_SEG2 0982#define SDMA1_BASE__INST2_SEG3 0983#define SDMA1_BASE__INST2_SEG4 0984#define SDMA1_BASE__INST2_SEG5 0985 986#define SDMA1_BASE__INST3_SEG0 0987#define SDMA1_BASE__INST3_SEG1 0988#define SDMA1_BASE__INST3_SEG2 0989#define SDMA1_BASE__INST3_SEG3 0990#define SDMA1_BASE__INST3_SEG4 0991#define SDMA1_BASE__INST3_SEG5 0992 993#define SDMA1_BASE__INST4_SEG0 0994#define SDMA1_BASE__INST4_SEG1 0995#define SDMA1_BASE__INST4_SEG2 0996#define SDMA1_BASE__INST4_SEG3 0997#define SDMA1_BASE__INST4_SEG4 0998#define SDMA1_BASE__INST4_SEG5 0999 1000#define SDMA1_BASE__INST5_SEG0 01001#define SDMA1_BASE__INST5_SEG1 01002#define SDMA1_BASE__INST5_SEG2 01003#define SDMA1_BASE__INST5_SEG3 01004#define SDMA1_BASE__INST5_SEG4 01005#define SDMA1_BASE__INST5_SEG5 01006 1007 1008#define SDMA1_BASE__INST6_SEG0 01009#define SDMA1_BASE__INST6_SEG1 01010#define SDMA1_BASE__INST6_SEG2 01011#define SDMA1_BASE__INST6_SEG3 01012#define SDMA1_BASE__INST6_SEG4 01013#define SDMA1_BASE__INST6_SEG5 01014 1015 1016#define SDMA2_BASE__INST0_SEG0 0x000137601017#define SDMA2_BASE__INST0_SEG1 0x0001E0001018#define SDMA2_BASE__INST0_SEG2 0x0042EC001019#define SDMA2_BASE__INST0_SEG3 01020#define SDMA2_BASE__INST0_SEG4 01021#define SDMA2_BASE__INST0_SEG5 01022 1023 1024#define SDMA2_BASE__INST1_SEG0 01025#define SDMA2_BASE__INST1_SEG1 01026#define SDMA2_BASE__INST1_SEG2 01027#define SDMA2_BASE__INST1_SEG3 01028#define SDMA2_BASE__INST1_SEG4 01029#define SDMA2_BASE__INST1_SEG5 01030 1031#define SDMA2_BASE__INST2_SEG0 01032#define SDMA2_BASE__INST2_SEG1 01033#define SDMA2_BASE__INST2_SEG2 01034#define SDMA2_BASE__INST2_SEG3 01035#define SDMA2_BASE__INST2_SEG4 01036#define SDMA2_BASE__INST2_SEG5 01037 1038#define SDMA2_BASE__INST3_SEG0 01039#define SDMA2_BASE__INST3_SEG1 01040#define SDMA2_BASE__INST3_SEG2 01041#define SDMA2_BASE__INST3_SEG3 01042#define SDMA2_BASE__INST3_SEG4 01043#define SDMA2_BASE__INST3_SEG5 01044 1045#define SDMA2_BASE__INST4_SEG0 01046#define SDMA2_BASE__INST4_SEG1 01047#define SDMA2_BASE__INST4_SEG2 01048#define SDMA2_BASE__INST4_SEG3 01049#define SDMA2_BASE__INST4_SEG4 01050#define SDMA2_BASE__INST4_SEG5 01051 1052#define SDMA2_BASE__INST5_SEG0 01053#define SDMA2_BASE__INST5_SEG1 01054#define SDMA2_BASE__INST5_SEG2 01055#define SDMA2_BASE__INST5_SEG3 01056#define SDMA2_BASE__INST5_SEG4 01057#define SDMA2_BASE__INST5_SEG5 01058 1059#define SDMA2_BASE__INST6_SEG0 01060#define SDMA2_BASE__INST6_SEG1 01061#define SDMA2_BASE__INST6_SEG2 01062#define SDMA2_BASE__INST6_SEG3 01063#define SDMA2_BASE__INST6_SEG4 01064#define SDMA2_BASE__INST6_SEG5 01065 1066#define SDMA3_BASE__INST0_SEG0 0x000137801067#define SDMA3_BASE__INST0_SEG1 0x0001E4001068#define SDMA3_BASE__INST0_SEG2 0x0042F0001069#define SDMA3_BASE__INST0_SEG3 01070#define SDMA3_BASE__INST0_SEG4 01071#define SDMA3_BASE__INST0_SEG5 01072 1073#define SDMA3_BASE__INST1_SEG0 01074#define SDMA3_BASE__INST1_SEG1 01075#define SDMA3_BASE__INST1_SEG2 01076#define SDMA3_BASE__INST1_SEG3 01077#define SDMA3_BASE__INST1_SEG4 01078#define SDMA3_BASE__INST1_SEG5 01079 1080#define SDMA3_BASE__INST2_SEG0 01081#define SDMA3_BASE__INST2_SEG1 01082#define SDMA3_BASE__INST2_SEG2 01083#define SDMA3_BASE__INST2_SEG3 01084#define SDMA3_BASE__INST2_SEG4 01085#define SDMA3_BASE__INST2_SEG5 01086 1087#define SDMA3_BASE__INST3_SEG0 01088#define SDMA3_BASE__INST3_SEG1 01089#define SDMA3_BASE__INST3_SEG2 01090#define SDMA3_BASE__INST3_SEG3 01091#define SDMA3_BASE__INST3_SEG4 01092#define SDMA3_BASE__INST3_SEG5 01093 1094#define SDMA3_BASE__INST4_SEG0 01095#define SDMA3_BASE__INST4_SEG1 01096#define SDMA3_BASE__INST4_SEG2 01097#define SDMA3_BASE__INST4_SEG3 01098#define SDMA3_BASE__INST4_SEG4 01099#define SDMA3_BASE__INST4_SEG5 01100 1101#define SDMA3_BASE__INST5_SEG0 01102#define SDMA3_BASE__INST5_SEG1 01103#define SDMA3_BASE__INST5_SEG2 01104#define SDMA3_BASE__INST5_SEG3 01105#define SDMA3_BASE__INST5_SEG4 01106#define SDMA3_BASE__INST5_SEG5 01107 1108#define SDMA3_BASE__INST6_SEG0 01109#define SDMA3_BASE__INST6_SEG1 01110#define SDMA3_BASE__INST6_SEG2 01111#define SDMA3_BASE__INST6_SEG3 01112#define SDMA3_BASE__INST6_SEG4 01113#define SDMA3_BASE__INST6_SEG5 01114 1115#define SDMA4_BASE__INST0_SEG0 0x000137A01116#define SDMA4_BASE__INST0_SEG1 0x0001E8001117#define SDMA4_BASE__INST0_SEG2 0x0042F4001118#define SDMA4_BASE__INST0_SEG3 01119#define SDMA4_BASE__INST0_SEG4 01120#define SDMA4_BASE__INST0_SEG5 01121 1122#define SDMA4_BASE__INST1_SEG0 01123#define SDMA4_BASE__INST1_SEG1 01124#define SDMA4_BASE__INST1_SEG2 01125#define SDMA4_BASE__INST1_SEG3 01126#define SDMA4_BASE__INST1_SEG4 01127#define SDMA4_BASE__INST1_SEG5 01128 1129#define SDMA4_BASE__INST2_SEG0 01130#define SDMA4_BASE__INST2_SEG1 01131#define SDMA4_BASE__INST2_SEG2 01132#define SDMA4_BASE__INST2_SEG3 01133#define SDMA4_BASE__INST2_SEG4 01134#define SDMA4_BASE__INST2_SEG5 01135 1136#define SDMA4_BASE__INST3_SEG0 01137#define SDMA4_BASE__INST3_SEG1 01138#define SDMA4_BASE__INST3_SEG2 01139#define SDMA4_BASE__INST3_SEG3 01140#define SDMA4_BASE__INST3_SEG4 01141#define SDMA4_BASE__INST3_SEG5 01142 1143#define SDMA4_BASE__INST4_SEG0 01144#define SDMA4_BASE__INST4_SEG1 01145#define SDMA4_BASE__INST4_SEG2 01146#define SDMA4_BASE__INST4_SEG3 01147#define SDMA4_BASE__INST4_SEG4 01148#define SDMA4_BASE__INST4_SEG5 01149 1150#define SDMA4_BASE__INST5_SEG0 01151#define SDMA4_BASE__INST5_SEG1 01152#define SDMA4_BASE__INST5_SEG2 01153#define SDMA4_BASE__INST5_SEG3 01154#define SDMA4_BASE__INST5_SEG4 01155#define SDMA4_BASE__INST5_SEG5 01156 1157#define SDMA4_BASE__INST6_SEG0 01158#define SDMA4_BASE__INST6_SEG1 01159#define SDMA4_BASE__INST6_SEG2 01160#define SDMA4_BASE__INST6_SEG3 01161#define SDMA4_BASE__INST6_SEG4 01162#define SDMA4_BASE__INST6_SEG5 01163 1164#define SDMA5_BASE__INST0_SEG0 0x000137C01165#define SDMA5_BASE__INST0_SEG1 0x0001EC001166#define SDMA5_BASE__INST0_SEG2 0x0042F8001167#define SDMA5_BASE__INST0_SEG3 01168#define SDMA5_BASE__INST0_SEG4 01169#define SDMA5_BASE__INST0_SEG5 01170 1171#define SDMA5_BASE__INST1_SEG0 01172#define SDMA5_BASE__INST1_SEG1 01173#define SDMA5_BASE__INST1_SEG2 01174#define SDMA5_BASE__INST1_SEG3 01175#define SDMA5_BASE__INST1_SEG4 01176#define SDMA5_BASE__INST1_SEG5 01177 1178#define SDMA5_BASE__INST2_SEG0 01179#define SDMA5_BASE__INST2_SEG1 01180#define SDMA5_BASE__INST2_SEG2 01181#define SDMA5_BASE__INST2_SEG3 01182#define SDMA5_BASE__INST2_SEG4 01183#define SDMA5_BASE__INST2_SEG5 01184 1185#define SDMA5_BASE__INST3_SEG0 01186#define SDMA5_BASE__INST3_SEG1 01187#define SDMA5_BASE__INST3_SEG2 01188#define SDMA5_BASE__INST3_SEG3 01189#define SDMA5_BASE__INST3_SEG4 01190#define SDMA5_BASE__INST3_SEG5 01191 1192#define SDMA5_BASE__INST4_SEG0 01193#define SDMA5_BASE__INST4_SEG1 01194#define SDMA5_BASE__INST4_SEG2 01195#define SDMA5_BASE__INST4_SEG3 01196#define SDMA5_BASE__INST4_SEG4 01197#define SDMA5_BASE__INST4_SEG5 01198 1199#define SDMA5_BASE__INST5_SEG0 01200#define SDMA5_BASE__INST5_SEG1 01201#define SDMA5_BASE__INST5_SEG2 01202#define SDMA5_BASE__INST5_SEG3 01203#define SDMA5_BASE__INST5_SEG4 01204#define SDMA5_BASE__INST5_SEG5 01205 1206#define SDMA5_BASE__INST6_SEG0 01207#define SDMA5_BASE__INST6_SEG1 01208#define SDMA5_BASE__INST6_SEG2 01209#define SDMA5_BASE__INST6_SEG3 01210#define SDMA5_BASE__INST6_SEG4 01211#define SDMA5_BASE__INST6_SEG5 01212 1213#define SDMA6_BASE__INST0_SEG0 0x000137E01214#define SDMA6_BASE__INST0_SEG1 0x0001F0001215#define SDMA6_BASE__INST0_SEG2 0x0042FC001216#define SDMA6_BASE__INST0_SEG3 01217#define SDMA6_BASE__INST0_SEG4 01218#define SDMA6_BASE__INST0_SEG5 01219 1220#define SDMA6_BASE__INST1_SEG0 01221#define SDMA6_BASE__INST1_SEG1 01222#define SDMA6_BASE__INST1_SEG2 01223#define SDMA6_BASE__INST1_SEG3 01224#define SDMA6_BASE__INST1_SEG4 01225#define SDMA6_BASE__INST1_SEG5 01226 1227#define SDMA6_BASE__INST2_SEG0 01228#define SDMA6_BASE__INST2_SEG1 01229#define SDMA6_BASE__INST2_SEG2 01230#define SDMA6_BASE__INST2_SEG3 01231#define SDMA6_BASE__INST2_SEG4 01232#define SDMA6_BASE__INST2_SEG5 01233 1234#define SDMA6_BASE__INST3_SEG0 01235#define SDMA6_BASE__INST3_SEG1 01236#define SDMA6_BASE__INST3_SEG2 01237#define SDMA6_BASE__INST3_SEG3 01238#define SDMA6_BASE__INST3_SEG4 01239#define SDMA6_BASE__INST3_SEG5 01240 1241#define SDMA6_BASE__INST4_SEG0 01242#define SDMA6_BASE__INST4_SEG1 01243#define SDMA6_BASE__INST4_SEG2 01244#define SDMA6_BASE__INST4_SEG3 01245#define SDMA6_BASE__INST4_SEG4 01246#define SDMA6_BASE__INST4_SEG5 01247 1248#define SDMA6_BASE__INST5_SEG0 01249#define SDMA6_BASE__INST5_SEG1 01250#define SDMA6_BASE__INST5_SEG2 01251#define SDMA6_BASE__INST5_SEG3 01252#define SDMA6_BASE__INST5_SEG4 01253#define SDMA6_BASE__INST5_SEG5 01254 1255#define SDMA6_BASE__INST6_SEG0 01256#define SDMA6_BASE__INST6_SEG1 01257#define SDMA6_BASE__INST6_SEG2 01258#define SDMA6_BASE__INST6_SEG3 01259#define SDMA6_BASE__INST6_SEG4 01260#define SDMA6_BASE__INST6_SEG5 01261 1262#define SDMA7_BASE__INST0_SEG0 0x000138001263#define SDMA7_BASE__INST0_SEG1 0x0001F4001264#define SDMA7_BASE__INST0_SEG2 0x004300001265#define SDMA7_BASE__INST0_SEG3 01266#define SDMA7_BASE__INST0_SEG4 01267#define SDMA7_BASE__INST0_SEG5 01268 1269#define SDMA7_BASE__INST1_SEG0 01270#define SDMA7_BASE__INST1_SEG1 01271#define SDMA7_BASE__INST1_SEG2 01272#define SDMA7_BASE__INST1_SEG3 01273#define SDMA7_BASE__INST1_SEG4 01274#define SDMA7_BASE__INST1_SEG5 01275 1276#define SDMA7_BASE__INST2_SEG0 01277#define SDMA7_BASE__INST2_SEG1 01278#define SDMA7_BASE__INST2_SEG2 01279#define SDMA7_BASE__INST2_SEG3 01280#define SDMA7_BASE__INST2_SEG4 01281#define SDMA7_BASE__INST2_SEG5 01282 1283#define SDMA7_BASE__INST3_SEG0 01284#define SDMA7_BASE__INST3_SEG1 01285#define SDMA7_BASE__INST3_SEG2 01286#define SDMA7_BASE__INST3_SEG3 01287#define SDMA7_BASE__INST3_SEG4 01288#define SDMA7_BASE__INST3_SEG5 01289 1290#define SDMA7_BASE__INST4_SEG0 01291#define SDMA7_BASE__INST4_SEG1 01292#define SDMA7_BASE__INST4_SEG2 01293#define SDMA7_BASE__INST4_SEG3 01294#define SDMA7_BASE__INST4_SEG4 01295#define SDMA7_BASE__INST4_SEG5 01296 1297#define SDMA7_BASE__INST5_SEG0 01298#define SDMA7_BASE__INST5_SEG1 01299#define SDMA7_BASE__INST5_SEG2 01300#define SDMA7_BASE__INST5_SEG3 01301#define SDMA7_BASE__INST5_SEG4 01302#define SDMA7_BASE__INST5_SEG5 01303 1304#define SDMA7_BASE__INST6_SEG0 01305#define SDMA7_BASE__INST6_SEG1 01306#define SDMA7_BASE__INST6_SEG2 01307#define SDMA7_BASE__INST6_SEG3 01308#define SDMA7_BASE__INST6_SEG4 01309#define SDMA7_BASE__INST6_SEG5 01310 1311#define SMUIO_BASE__INST0_SEG0 0x000120801312#define SMUIO_BASE__INST0_SEG1 0x000168001313#define SMUIO_BASE__INST0_SEG2 0x00016A001314#define SMUIO_BASE__INST0_SEG3 0x004010001315#define SMUIO_BASE__INST0_SEG4 0x004400001316#define SMUIO_BASE__INST0_SEG5 01317 1318#define SMUIO_BASE__INST1_SEG0 01319#define SMUIO_BASE__INST1_SEG1 01320#define SMUIO_BASE__INST1_SEG2 01321#define SMUIO_BASE__INST1_SEG3 01322#define SMUIO_BASE__INST1_SEG4 01323#define SMUIO_BASE__INST1_SEG5 01324 1325#define SMUIO_BASE__INST2_SEG0 01326#define SMUIO_BASE__INST2_SEG1 01327#define SMUIO_BASE__INST2_SEG2 01328#define SMUIO_BASE__INST2_SEG3 01329#define SMUIO_BASE__INST2_SEG4 01330#define SMUIO_BASE__INST2_SEG5 01331 1332#define SMUIO_BASE__INST3_SEG0 01333#define SMUIO_BASE__INST3_SEG1 01334#define SMUIO_BASE__INST3_SEG2 01335#define SMUIO_BASE__INST3_SEG3 01336#define SMUIO_BASE__INST3_SEG4 01337#define SMUIO_BASE__INST3_SEG5 01338 1339#define SMUIO_BASE__INST4_SEG0 01340#define SMUIO_BASE__INST4_SEG1 01341#define SMUIO_BASE__INST4_SEG2 01342#define SMUIO_BASE__INST4_SEG3 01343#define SMUIO_BASE__INST4_SEG4 01344#define SMUIO_BASE__INST4_SEG5 01345 1346#define SMUIO_BASE__INST5_SEG0 01347#define SMUIO_BASE__INST5_SEG1 01348#define SMUIO_BASE__INST5_SEG2 01349#define SMUIO_BASE__INST5_SEG3 01350#define SMUIO_BASE__INST5_SEG4 01351#define SMUIO_BASE__INST5_SEG5 01352 1353#define SMUIO_BASE__INST6_SEG0 01354#define SMUIO_BASE__INST6_SEG1 01355#define SMUIO_BASE__INST6_SEG2 01356#define SMUIO_BASE__INST6_SEG3 01357#define SMUIO_BASE__INST6_SEG4 01358#define SMUIO_BASE__INST6_SEG5 01359 1360#define SMUIO_BASE__INST7_SEG0 01361#define SMUIO_BASE__INST7_SEG1 01362#define SMUIO_BASE__INST7_SEG2 01363#define SMUIO_BASE__INST7_SEG3 01364#define SMUIO_BASE__INST7_SEG4 01365#define SMUIO_BASE__INST7_SEG5 01366 1367#define THM_BASE__INST0_SEG0 0x000120601368#define THM_BASE__INST0_SEG1 0x000166001369#define THM_BASE__INST0_SEG2 0x00400C001370#define THM_BASE__INST0_SEG3 01371#define THM_BASE__INST0_SEG4 01372#define THM_BASE__INST0_SEG5 01373 1374#define THM_BASE__INST1_SEG0 01375#define THM_BASE__INST1_SEG1 01376#define THM_BASE__INST1_SEG2 01377#define THM_BASE__INST1_SEG3 01378#define THM_BASE__INST1_SEG4 01379#define THM_BASE__INST1_SEG5 01380 1381#define THM_BASE__INST2_SEG0 01382#define THM_BASE__INST2_SEG1 01383#define THM_BASE__INST2_SEG2 01384#define THM_BASE__INST2_SEG3 01385#define THM_BASE__INST2_SEG4 01386#define THM_BASE__INST2_SEG5 01387 1388#define THM_BASE__INST3_SEG0 01389#define THM_BASE__INST3_SEG1 01390#define THM_BASE__INST3_SEG2 01391#define THM_BASE__INST3_SEG3 01392#define THM_BASE__INST3_SEG4 01393#define THM_BASE__INST3_SEG5 01394 1395#define THM_BASE__INST4_SEG0 01396#define THM_BASE__INST4_SEG1 01397#define THM_BASE__INST4_SEG2 01398#define THM_BASE__INST4_SEG3 01399#define THM_BASE__INST4_SEG4 01400#define THM_BASE__INST4_SEG5 01401 1402#define THM_BASE__INST5_SEG0 01403#define THM_BASE__INST5_SEG1 01404#define THM_BASE__INST5_SEG2 01405#define THM_BASE__INST5_SEG3 01406#define THM_BASE__INST5_SEG4 01407#define THM_BASE__INST5_SEG5 01408 1409#define THM_BASE__INST6_SEG0 01410#define THM_BASE__INST6_SEG1 01411#define THM_BASE__INST6_SEG2 01412#define THM_BASE__INST6_SEG3 01413#define THM_BASE__INST6_SEG4 01414#define THM_BASE__INST6_SEG5 01415 1416#define THM_BASE__INST7_SEG0 01417#define THM_BASE__INST7_SEG1 01418#define THM_BASE__INST7_SEG2 01419#define THM_BASE__INST7_SEG3 01420#define THM_BASE__INST7_SEG4 01421#define THM_BASE__INST7_SEG5 01422 1423#define UMC_BASE__INST0_SEG0 0x000132C01424#define UMC_BASE__INST0_SEG1 0x000140001425#define UMC_BASE__INST0_SEG2 0x004258001426#define UMC_BASE__INST0_SEG3 01427#define UMC_BASE__INST0_SEG4 01428#define UMC_BASE__INST0_SEG5 01429 1430#define UMC_BASE__INST1_SEG0 0x000132E01431#define UMC_BASE__INST1_SEG1 0x000540001432#define UMC_BASE__INST1_SEG2 0x00425C001433#define UMC_BASE__INST1_SEG3 01434#define UMC_BASE__INST1_SEG4 01435#define UMC_BASE__INST1_SEG5 01436 1437#define UMC_BASE__INST2_SEG0 0x000133001438#define UMC_BASE__INST2_SEG1 0x000940001439#define UMC_BASE__INST2_SEG2 0x004260001440#define UMC_BASE__INST2_SEG3 01441#define UMC_BASE__INST2_SEG4 01442#define UMC_BASE__INST2_SEG5 01443 1444#define UMC_BASE__INST3_SEG0 0x000133201445#define UMC_BASE__INST3_SEG1 0x000D40001446#define UMC_BASE__INST3_SEG2 0x004264001447#define UMC_BASE__INST3_SEG3 01448#define UMC_BASE__INST3_SEG4 01449#define UMC_BASE__INST3_SEG5 01450 1451#define UMC_BASE__INST4_SEG0 0x000133401452#define UMC_BASE__INST4_SEG1 0x001140001453#define UMC_BASE__INST4_SEG2 0x004268001454#define UMC_BASE__INST4_SEG3 01455#define UMC_BASE__INST4_SEG4 01456#define UMC_BASE__INST4_SEG5 01457 1458#define UMC_BASE__INST5_SEG0 0x000133601459#define UMC_BASE__INST5_SEG1 0x001540001460#define UMC_BASE__INST5_SEG2 0x00426C001461#define UMC_BASE__INST5_SEG3 01462#define UMC_BASE__INST5_SEG4 01463#define UMC_BASE__INST5_SEG5 01464 1465#define UMC_BASE__INST6_SEG0 0x000133801466#define UMC_BASE__INST6_SEG1 0x001940001467#define UMC_BASE__INST6_SEG2 0x004270001468#define UMC_BASE__INST6_SEG3 01469#define UMC_BASE__INST6_SEG4 01470#define UMC_BASE__INST6_SEG5 01471 1472#define UMC_BASE__INST7_SEG0 0x000133A01473#define UMC_BASE__INST7_SEG1 0x001D40001474#define UMC_BASE__INST7_SEG2 0x004274001475#define UMC_BASE__INST7_SEG3 01476#define UMC_BASE__INST7_SEG4 01477#define UMC_BASE__INST7_SEG5 01478 1479#define UVD_BASE__INST0_SEG0 0x000078001480#define UVD_BASE__INST0_SEG1 0x00007E001481#define UVD_BASE__INST0_SEG2 0x000121801482#define UVD_BASE__INST0_SEG3 0x004030001483#define UVD_BASE__INST0_SEG4 01484#define UVD_BASE__INST0_SEG5 01485 1486#define UVD_BASE__INST1_SEG0 0x00007A001487#define UVD_BASE__INST1_SEG1 0x000090001488#define UVD_BASE__INST1_SEG2 0x000136E01489#define UVD_BASE__INST1_SEG3 0x0042DC001490#define UVD_BASE__INST1_SEG4 01491#define UVD_BASE__INST1_SEG5 01492 1493#define UVD_BASE__INST2_SEG0 01494#define UVD_BASE__INST2_SEG1 01495#define UVD_BASE__INST2_SEG2 01496#define UVD_BASE__INST2_SEG3 01497#define UVD_BASE__INST2_SEG4 01498#define UVD_BASE__INST2_SEG5 01499 1500#define UVD_BASE__INST3_SEG0 01501#define UVD_BASE__INST3_SEG1 01502#define UVD_BASE__INST3_SEG2 01503#define UVD_BASE__INST3_SEG3 01504#define UVD_BASE__INST3_SEG4 01505#define UVD_BASE__INST3_SEG5 01506 1507#define UVD_BASE__INST4_SEG0 01508#define UVD_BASE__INST4_SEG1 01509#define UVD_BASE__INST4_SEG2 01510#define UVD_BASE__INST4_SEG3 01511#define UVD_BASE__INST4_SEG4 01512#define UVD_BASE__INST4_SEG5 01513 1514#define UVD_BASE__INST5_SEG0 01515#define UVD_BASE__INST5_SEG1 01516#define UVD_BASE__INST5_SEG2 01517#define UVD_BASE__INST5_SEG3 01518#define UVD_BASE__INST5_SEG4 01519#define UVD_BASE__INST5_SEG5 01520 1521#define UVD_BASE__INST6_SEG0 01522#define UVD_BASE__INST6_SEG1 01523#define UVD_BASE__INST6_SEG2 01524#define UVD_BASE__INST6_SEG3 01525#define UVD_BASE__INST6_SEG4 01526#define UVD_BASE__INST6_SEG5 01527 1528#define UVD_BASE__INST7_SEG0 01529#define UVD_BASE__INST7_SEG1 01530#define UVD_BASE__INST7_SEG2 01531#define UVD_BASE__INST7_SEG3 01532#define UVD_BASE__INST7_SEG4 01533#define UVD_BASE__INST7_SEG5 01534 1535#define DBGU_IO_BASE__INST0_SEG0 0x000001E01536#define DBGU_IO_BASE__INST0_SEG1 0x000125A01537#define DBGU_IO_BASE__INST0_SEG2 0x0040B4001538#define DBGU_IO_BASE__INST0_SEG3 01539#define DBGU_IO_BASE__INST0_SEG4 01540#define DBGU_IO_BASE__INST0_SEG5 01541 1542#define DBGU_IO_BASE__INST1_SEG0 01543#define DBGU_IO_BASE__INST1_SEG1 01544#define DBGU_IO_BASE__INST1_SEG2 01545#define DBGU_IO_BASE__INST1_SEG3 01546#define DBGU_IO_BASE__INST1_SEG4 01547#define DBGU_IO_BASE__INST1_SEG5 01548 1549#define DBGU_IO_BASE__INST2_SEG0 01550#define DBGU_IO_BASE__INST2_SEG1 01551#define DBGU_IO_BASE__INST2_SEG2 01552#define DBGU_IO_BASE__INST2_SEG3 01553#define DBGU_IO_BASE__INST2_SEG4 01554#define DBGU_IO_BASE__INST2_SEG5 01555 1556#define DBGU_IO_BASE__INST3_SEG0 01557#define DBGU_IO_BASE__INST3_SEG1 01558#define DBGU_IO_BASE__INST3_SEG2 01559#define DBGU_IO_BASE__INST3_SEG3 01560#define DBGU_IO_BASE__INST3_SEG4 01561#define DBGU_IO_BASE__INST3_SEG5 01562 1563#define DBGU_IO_BASE__INST4_SEG0 01564#define DBGU_IO_BASE__INST4_SEG1 01565#define DBGU_IO_BASE__INST4_SEG2 01566#define DBGU_IO_BASE__INST4_SEG3 01567#define DBGU_IO_BASE__INST4_SEG4 01568#define DBGU_IO_BASE__INST4_SEG5 01569 1570#define DBGU_IO_BASE__INST5_SEG0 01571#define DBGU_IO_BASE__INST5_SEG1 01572#define DBGU_IO_BASE__INST5_SEG2 01573#define DBGU_IO_BASE__INST5_SEG3 01574#define DBGU_IO_BASE__INST5_SEG4 01575#define DBGU_IO_BASE__INST5_SEG5 01576 1577#define DBGU_IO_BASE__INST6_SEG0 01578#define DBGU_IO_BASE__INST6_SEG1 01579#define DBGU_IO_BASE__INST6_SEG2 01580#define DBGU_IO_BASE__INST6_SEG3 01581#define DBGU_IO_BASE__INST6_SEG4 01582#define DBGU_IO_BASE__INST6_SEG5 01583 1584#define DBGU_IO_BASE__INST7_SEG0 01585#define DBGU_IO_BASE__INST7_SEG1 01586#define DBGU_IO_BASE__INST7_SEG2 01587#define DBGU_IO_BASE__INST7_SEG3 01588#define DBGU_IO_BASE__INST7_SEG4 01589#define DBGU_IO_BASE__INST7_SEG5 01590 1591#define RSMU_BASE__INST0_SEG0 0x000120001592#define RSMU_BASE__INST0_SEG1 01593#define RSMU_BASE__INST0_SEG2 01594#define RSMU_BASE__INST0_SEG3 01595#define RSMU_BASE__INST0_SEG4 01596#define RSMU_BASE__INST0_SEG5 01597 1598#define RSMU_BASE__INST1_SEG0 01599#define RSMU_BASE__INST1_SEG1 01600#define RSMU_BASE__INST1_SEG2 01601#define RSMU_BASE__INST1_SEG3 01602#define RSMU_BASE__INST1_SEG4 01603#define RSMU_BASE__INST1_SEG5 01604 1605#define RSMU_BASE__INST2_SEG0 01606#define RSMU_BASE__INST2_SEG1 01607#define RSMU_BASE__INST2_SEG2 01608#define RSMU_BASE__INST2_SEG3 01609#define RSMU_BASE__INST2_SEG4 01610#define RSMU_BASE__INST2_SEG5 01611 1612#define RSMU_BASE__INST3_SEG0 01613#define RSMU_BASE__INST3_SEG1 01614#define RSMU_BASE__INST3_SEG2 01615#define RSMU_BASE__INST3_SEG3 01616#define RSMU_BASE__INST3_SEG4 01617#define RSMU_BASE__INST3_SEG5 01618 1619#define RSMU_BASE__INST4_SEG0 01620#define RSMU_BASE__INST4_SEG1 01621#define RSMU_BASE__INST4_SEG2 01622#define RSMU_BASE__INST4_SEG3 01623#define RSMU_BASE__INST4_SEG4 01624#define RSMU_BASE__INST4_SEG5 01625 1626#define RSMU_BASE__INST5_SEG0 01627#define RSMU_BASE__INST5_SEG1 01628#define RSMU_BASE__INST5_SEG2 01629#define RSMU_BASE__INST5_SEG3 01630#define RSMU_BASE__INST5_SEG4 01631#define RSMU_BASE__INST5_SEG5 01632 1633#define RSMU_BASE__INST6_SEG0 01634#define RSMU_BASE__INST6_SEG1 01635#define RSMU_BASE__INST6_SEG2 01636#define RSMU_BASE__INST6_SEG3 01637#define RSMU_BASE__INST6_SEG4 01638#define RSMU_BASE__INST6_SEG5 01639 1640#define RSMU_BASE__INST7_SEG0 01641#define RSMU_BASE__INST7_SEG1 01642#define RSMU_BASE__INST7_SEG2 01643#define RSMU_BASE__INST7_SEG3 01644#define RSMU_BASE__INST7_SEG4 01645#define RSMU_BASE__INST7_SEG5 01646 1647 1648#endif1649