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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.4 * Author: James.Qian.Wang <james.qian.wang@arm.com>5 *6 */7#ifndef _D71_REG_H_8#define _D71_REG_H_9 10/* Common block registers offset */11#define BLK_BLOCK_INFO 0x00012#define BLK_PIPELINE_INFO 0x00413#define BLK_MAX_LINE_SIZE 0x00814#define BLK_VALID_INPUT_ID0 0x02015#define BLK_OUTPUT_ID0 0x06016#define BLK_INPUT_ID0 0x08017#define BLK_IRQ_RAW_STATUS 0x0A018#define BLK_IRQ_CLEAR 0x0A419#define BLK_IRQ_MASK 0x0A820#define BLK_IRQ_STATUS 0x0AC21#define BLK_STATUS 0x0B022#define BLK_INFO 0x0C023#define BLK_CONTROL 0x0D024#define BLK_SIZE 0x0D425#define BLK_IN_SIZE 0x0E026 27#define BLK_P0_PTR_LOW 0x10028#define BLK_P0_PTR_HIGH 0x10429#define BLK_P0_STRIDE 0x10830#define BLK_P1_PTR_LOW 0x11031#define BLK_P1_PTR_HIGH 0x11432#define BLK_P1_STRIDE 0x11833#define BLK_P2_PTR_LOW 0x12034#define BLK_P2_PTR_HIGH 0x12435 36#define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)37#define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)38#define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)39#define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)40#define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)41 42#define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)43#define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)44 45/* Common block control register bits */46#define BLK_CTRL_EN BIT(0)47/* Common size macro */48#define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))49#define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))50#define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))51 52/* AD_CONTROL register */53#define AD_CONTROL 0x16054 55/* AD_CONTROL register bits */56#define AD_AEN BIT(0)57#define AD_YT BIT(1)58#define AD_BS BIT(2)59#define AD_WB BIT(3)60#define AD_TH BIT(4)61 62/* Global Control Unit */63#define GLB_ARCH_ID 0x00064#define GLB_CORE_ID 0x00465#define GLB_CORE_INFO 0x00866#define GLB_IRQ_STATUS 0x01067 68#define GCU_CONFIG_VALID0 0x0D469#define GCU_CONFIG_VALID1 0x0D870 71/* GCU_CONTROL_BITS */72#define GCU_CONTROL_MODE(x) ((x) & 0x7)73#define GCU_CONTROL_SRST BIT(16)74 75/* GCU_CONFIGURATION registers */76#define GCU_CONFIGURATION_ID0 0x10077#define GCU_CONFIGURATION_ID1 0x10478 79/* GCU configuration */80#define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF)81#define GCU_MAX_NUM_LINES(x) ((x) >> 16)82#define GCU_NUM_RICH_LAYERS(x) ((x) & 0x7)83#define GCU_NUM_PIPELINES(x) (((x) >> 3) & 0x7)84#define GCU_NUM_SCALERS(x) (((x) >> 6) & 0x7)85#define GCU_DISPLAY_SPLIT_EN(x) (((x) >> 16) & 0x1)86#define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)87 88/* GCU opmode */89#define INACTIVE_MODE 090#define TBU_CONNECT_MODE 191#define TBU_DISCONNECT_MODE 292#define DO0_ACTIVE_MODE 393#define DO1_ACTIVE_MODE 494#define DO01_ACTIVE_MODE 595 96/* GLB_IRQ_STATUS bits */97#define GLB_IRQ_STATUS_GCU BIT(0)98#define GLB_IRQ_STATUS_LPU0 BIT(8)99#define GLB_IRQ_STATUS_LPU1 BIT(9)100#define GLB_IRQ_STATUS_ATU0 BIT(10)101#define GLB_IRQ_STATUS_ATU1 BIT(11)102#define GLB_IRQ_STATUS_ATU2 BIT(12)103#define GLB_IRQ_STATUS_ATU3 BIT(13)104#define GLB_IRQ_STATUS_CU0 BIT(16)105#define GLB_IRQ_STATUS_CU1 BIT(17)106#define GLB_IRQ_STATUS_DOU0 BIT(24)107#define GLB_IRQ_STATUS_DOU1 BIT(25)108 109#define GLB_IRQ_STATUS_PIPE0 (GLB_IRQ_STATUS_LPU0 |\110 GLB_IRQ_STATUS_ATU0 |\111 GLB_IRQ_STATUS_ATU1 |\112 GLB_IRQ_STATUS_CU0 |\113 GLB_IRQ_STATUS_DOU0)114 115#define GLB_IRQ_STATUS_PIPE1 (GLB_IRQ_STATUS_LPU1 |\116 GLB_IRQ_STATUS_ATU2 |\117 GLB_IRQ_STATUS_ATU3 |\118 GLB_IRQ_STATUS_CU1 |\119 GLB_IRQ_STATUS_DOU1)120 121#define GLB_IRQ_STATUS_ATU (GLB_IRQ_STATUS_ATU0 |\122 GLB_IRQ_STATUS_ATU1 |\123 GLB_IRQ_STATUS_ATU2 |\124 GLB_IRQ_STATUS_ATU3)125 126/* GCU_IRQ_BITS */127#define GCU_IRQ_CVAL0 BIT(0)128#define GCU_IRQ_CVAL1 BIT(1)129#define GCU_IRQ_MODE BIT(4)130#define GCU_IRQ_ERR BIT(11)131 132/* GCU_STATUS_BITS */133#define GCU_STATUS_MODE(x) ((x) & 0x7)134#define GCU_STATUS_MERR BIT(4)135#define GCU_STATUS_TCS0 BIT(8)136#define GCU_STATUS_TCS1 BIT(9)137#define GCU_STATUS_ACTIVE BIT(31)138 139/* GCU_CONFIG_VALIDx BITS */140#define GCU_CONFIG_CVAL BIT(0)141 142/* PERIPHERAL registers */143#define PERIPH_MAX_LINE_SIZE BIT(0)144#define PERIPH_NUM_RICH_LAYERS BIT(4)145#define PERIPH_SPLIT_EN BIT(8)146#define PERIPH_TBU_EN BIT(12)147#define PERIPH_AFBC_DMA_EN BIT(16)148#define PERIPH_CONFIGURATION_ID 0x1D4149 150/* LPU register */151#define LPU_TBU_STATUS 0x0B4152#define LPU_RAXI_CONTROL 0x0D0153#define LPU_WAXI_CONTROL 0x0D4154#define LPU_TBU_CONTROL 0x0D8155 156/* LPU_xAXI_CONTROL_BITS */157#define TO_RAXI_AOUTSTDCAPB(x) (x)158#define TO_RAXI_BOUTSTDCAPB(x) ((x) << 8)159#define TO_RAXI_BEN(x) ((x) << 15)160#define TO_xAXI_BURSTLEN(x) ((x) << 16)161#define TO_xAXI_AxQOS(x) ((x) << 24)162#define TO_xAXI_ORD(x) ((x) << 31)163#define TO_WAXI_OUTSTDCAPB(x) (x)164 165#define RAXI_AOUTSTDCAPB_MASK 0x7F166#define RAXI_BOUTSTDCAPB_MASK 0x7F00167#define RAXI_BEN_MASK BIT(15)168#define xAXI_BURSTLEN_MASK 0x3F0000169#define xAXI_AxQOS_MASK 0xF000000170#define xAXI_ORD_MASK BIT(31)171#define WAXI_OUTSTDCAPB_MASK 0x3F172 173/* LPU_TBU_CONTROL BITS */174#define TO_TBU_DOUTSTDCAPB(x) (x)175#define TBU_DOUTSTDCAPB_MASK 0x3F176 177/* LPU_IRQ_BITS */178#define LPU_IRQ_OVR BIT(9)179#define LPU_IRQ_IBSY BIT(10)180#define LPU_IRQ_ERR BIT(11)181#define LPU_IRQ_EOW BIT(12)182#define LPU_IRQ_PL0 BIT(13)183 184/* LPU_STATUS_BITS */185#define LPU_STATUS_AXIED(x) ((x) & 0xF)186#define LPU_STATUS_AXIE BIT(4)187#define LPU_STATUS_AXIRP BIT(5)188#define LPU_STATUS_AXIWP BIT(6)189#define LPU_STATUS_FEMPTY BIT(11)190#define LPU_STATUS_FFULL BIT(14)191#define LPU_STATUS_ACE0 BIT(16)192#define LPU_STATUS_ACE1 BIT(17)193#define LPU_STATUS_ACE2 BIT(18)194#define LPU_STATUS_ACE3 BIT(19)195#define LPU_STATUS_ACTIVE BIT(31)196 197#define AXIEID_MASK 0xF198#define AXIE_MASK LPU_STATUS_AXIE199#define AXIRP_MASK LPU_STATUS_AXIRP200#define AXIWP_MASK LPU_STATUS_AXIWP201 202#define FROM_AXIEID(reg) ((reg) & AXIEID_MASK)203#define TO_AXIE(x) ((x) << 4)204#define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5)205#define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6)206 207/* LPU_TBU_STATUS_BITS */208#define LPU_TBU_STATUS_TCF BIT(1)209#define LPU_TBU_STATUS_TTNG BIT(2)210#define LPU_TBU_STATUS_TITR BIT(8)211#define LPU_TBU_STATUS_TEMR BIT(16)212#define LPU_TBU_STATUS_TTF BIT(31)213 214/* LPU_TBU_CONTROL BITS */215#define LPU_TBU_CTRL_TLBPEN BIT(16)216 217/* CROSSBAR CONTROL BITS */218#define CBU_INPUT_CTRL_EN BIT(0)219#define CBU_NUM_INPUT_IDS 5220#define CBU_NUM_OUTPUT_IDS 5221 222/* CU register */223#define CU_BG_COLOR 0x0DC224#define CU_INPUT0_SIZE 0x0E0225#define CU_INPUT0_OFFSET 0x0E4226#define CU_INPUT0_CONTROL 0x0E8227#define CU_INPUT1_SIZE 0x0F0228#define CU_INPUT1_OFFSET 0x0F4229#define CU_INPUT1_CONTROL 0x0F8230#define CU_INPUT2_SIZE 0x100231#define CU_INPUT2_OFFSET 0x104232#define CU_INPUT2_CONTROL 0x108233#define CU_INPUT3_SIZE 0x110234#define CU_INPUT3_OFFSET 0x114235#define CU_INPUT3_CONTROL 0x118236#define CU_INPUT4_SIZE 0x120237#define CU_INPUT4_OFFSET 0x124238#define CU_INPUT4_CONTROL 0x128239 240#define CU_PER_INPUT_REGS 4241 242#define CU_NUM_INPUT_IDS 5243#define CU_NUM_OUTPUT_IDS 1244 245/* CU control register bits */246#define CU_CTRL_COPROC BIT(0)247 248/* CU_IRQ_BITS */249#define CU_IRQ_OVR BIT(9)250#define CU_IRQ_ERR BIT(11)251 252/* CU_STATUS_BITS */253#define CU_STATUS_CPE BIT(0)254#define CU_STATUS_ZME BIT(1)255#define CU_STATUS_CFGE BIT(2)256#define CU_STATUS_ACTIVE BIT(31)257 258/* CU input control register bits */259#define CU_INPUT_CTRL_EN BIT(0)260#define CU_INPUT_CTRL_PAD BIT(1)261#define CU_INPUT_CTRL_PMUL BIT(2)262#define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)263 264/* DOU register */265 266/* DOU_IRQ_BITS */267#define DOU_IRQ_UND BIT(8)268#define DOU_IRQ_ERR BIT(11)269#define DOU_IRQ_PL0 BIT(13)270#define DOU_IRQ_PL1 BIT(14)271 272/* DOU_STATUS_BITS */273#define DOU_STATUS_DRIFTTO BIT(0)274#define DOU_STATUS_FRAMETO BIT(1)275#define DOU_STATUS_TETO BIT(2)276#define DOU_STATUS_CSCE BIT(8)277#define DOU_STATUS_ACTIVE BIT(31)278 279/* Layer registers */280#define LAYER_INFO 0x0C0281#define LAYER_R_CONTROL 0x0D4282#define LAYER_FMT 0x0D8283#define LAYER_LT_COEFFTAB 0x0DC284#define LAYER_PALPHA 0x0E4285 286#define LAYER_YUV_RGB_COEFF0 0x130287 288#define LAYER_AD_H_CROP 0x164289#define LAYER_AD_V_CROP 0x168290 291#define LAYER_RGB_RGB_COEFF0 0x170292 293/* L_CONTROL_BITS */294#define L_EN BIT(0)295#define L_IT BIT(4)296#define L_R2R BIT(5)297#define L_FT BIT(6)298#define L_ROT(x) (((x) & 3) << 8)299#define L_HFLIP BIT(10)300#define L_VFLIP BIT(11)301#define L_TBU_EN BIT(16)302#define L_A_RCACHE(x) (((x) & 0xF) << 28)303#define L_ROT_R0 0304#define L_ROT_R90 1305#define L_ROT_R180 2306#define L_ROT_R270 3307 308/* LAYER_R_CONTROL BITS */309#define LR_CHI422_BILINEAR 0310#define LR_CHI422_REPLICATION 1311#define LR_CHI420_JPEG (0 << 2)312#define LR_CHI420_MPEG (1 << 2)313 314#define L_ITSEL(x) ((x) & 0xFFF)315#define L_FTSEL(x) (((x) & 0xFFF) << 16)316 317#define LAYER_PER_PLANE_REGS 4318 319/* Layer_WR registers */320#define LAYER_WR_PROG_LINE 0x0D4321#define LAYER_WR_FORMAT 0x0D8322 323/* Layer_WR control bits */324#define LW_OFM BIT(4)325#define LW_LALPHA(x) (((x) & 0xFF) << 8)326#define LW_A_WCACHE(x) (((x) & 0xF) << 28)327#define LW_TBU_EN BIT(16)328 329#define AxCACHE_MASK 0xF0000000330 331/* Layer AXI R/W cache setting */332#define AxCACHE_B BIT(0) /* Bufferable */333#define AxCACHE_M BIT(1) /* Modifiable */334#define AxCACHE_RA BIT(2) /* Read-Allocate */335#define AxCACHE_WA BIT(3) /* Write-Allocate */336 337/* Layer info bits */338#define L_INFO_RF BIT(0)339#define L_INFO_CM BIT(1)340#define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)341#define L_INFO_YUV_MAX_LINESZ(x) (((x) >> 16) & 0xFFFF)342 343/* Scaler registers */344#define SC_COEFFTAB 0x0DC345#define SC_OUT_SIZE 0x0E4346#define SC_H_CROP 0x0E8347#define SC_V_CROP 0x0EC348#define SC_H_INIT_PH 0x0F0349#define SC_H_DELTA_PH 0x0F4350#define SC_V_INIT_PH 0x0F8351#define SC_V_DELTA_PH 0x0FC352#define SC_ENH_LIMITS 0x130353#define SC_ENH_COEFF0 0x134354 355#define SC_MAX_ENH_COEFF 9356 357/* SC_CTRL_BITS */358#define SC_CTRL_SCL BIT(0)359#define SC_CTRL_LS BIT(1)360#define SC_CTRL_AP BIT(4)361#define SC_CTRL_IENH BIT(8)362#define SC_CTRL_RGBSM BIT(16)363#define SC_CTRL_ASM BIT(17)364 365#define SC_VTSEL(vtal) ((vtal) << 16)366 367#define SC_NUM_INPUTS_IDS 1368#define SC_NUM_OUTPUTS_IDS 1369 370#define MG_NUM_INPUTS_IDS 2371#define MG_NUM_OUTPUTS_IDS 1372 373/* Merger registers */374#define MG_INPUT_ID0 BLK_INPUT_ID0375#define MG_INPUT_ID1 (MG_INPUT_ID0 + 4)376#define MG_SIZE BLK_SIZE377 378/* Splitter registers */379#define SP_OVERLAP_SIZE 0xD8380 381/* Backend registers */382#define BS_INFO 0x0C0383#define BS_PROG_LINE 0x0D4384#define BS_PREFETCH_LINE 0x0D8385#define BS_BG_COLOR 0x0DC386#define BS_ACTIVESIZE 0x0E0387#define BS_HINTERVALS 0x0E4388#define BS_VINTERVALS 0x0E8389#define BS_SYNC 0x0EC390#define BS_DRIFT_TO 0x100391#define BS_FRAME_TO 0x104392#define BS_TE_TO 0x108393#define BS_T0_INTERVAL 0x110394#define BS_T1_INTERVAL 0x114395#define BS_T2_INTERVAL 0x118396#define BS_CRC0_LOW 0x120397#define BS_CRC0_HIGH 0x124398#define BS_CRC1_LOW 0x128399#define BS_CRC1_HIGH 0x12C400#define BS_USER 0x130401 402/* BS control register bits */403#define BS_CTRL_EN BIT(0)404#define BS_CTRL_VM BIT(1)405#define BS_CTRL_BM BIT(2)406#define BS_CTRL_HMASK BIT(4)407#define BS_CTRL_VD BIT(5)408#define BS_CTRL_TE BIT(8)409#define BS_CTRL_TS BIT(9)410#define BS_CTRL_TM BIT(12)411#define BS_CTRL_DL BIT(16)412#define BS_CTRL_SBS BIT(17)413#define BS_CTRL_CRC BIT(18)414#define BS_CTRL_PM BIT(20)415 416/* BS active size/intervals */417#define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))418#define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))419 420/* BS_SYNC bits */421#define BS_SYNC_HSW(x) ((x) & 0x3FF)422#define BS_SYNC_HSP BIT(12)423#define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)424#define BS_SYNC_VSP BIT(28)425 426#define BS_NUM_INPUT_IDS 0427#define BS_NUM_OUTPUT_IDS 0428 429/* Image process registers */430#define IPS_DEPTH 0x0D8431#define IPS_RGB_RGB_COEFF0 0x130432#define IPS_RGB_YUV_COEFF0 0x170433 434#define IPS_DEPTH_MARK 0xF435 436/* IPS control register bits */437#define IPS_CTRL_RGB BIT(0)438#define IPS_CTRL_FT BIT(4)439#define IPS_CTRL_YUV BIT(8)440#define IPS_CTRL_CHD422 BIT(9)441#define IPS_CTRL_CHD420 BIT(10)442#define IPS_CTRL_LPF BIT(11)443#define IPS_CTRL_DITH BIT(12)444#define IPS_CTRL_CLAMP BIT(16)445#define IPS_CTRL_SBS BIT(17)446 447/* IPS info register bits */448#define IPS_INFO_CHD420 BIT(10)449 450#define IPS_NUM_INPUT_IDS 2451#define IPS_NUM_OUTPUT_IDS 1452 453/* FT_COEFF block registers */454#define FT_COEFF0 0x80455#define GLB_IT_COEFF 0x80456 457/* GLB_SC_COEFF registers */458#define GLB_SC_COEFF_ADDR 0x0080459#define GLB_SC_COEFF_DATA 0x0084460#define GLB_LT_COEFF_DATA 0x0080461 462#define GLB_SC_COEFF_MAX_NUM 1024463#define GLB_LT_COEFF_NUM 65464/* GLB_SC_ADDR */465#define SC_COEFF_R_ADDR BIT(18)466#define SC_COEFF_G_ADDR BIT(17)467#define SC_COEFF_B_ADDR BIT(16)468 469#define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))470 471enum d71_blk_type {472 D71_BLK_TYPE_GCU = 0x00,473 D71_BLK_TYPE_LPU = 0x01,474 D71_BLK_TYPE_CU = 0x02,475 D71_BLK_TYPE_DOU = 0x03,476 D71_BLK_TYPE_AEU = 0x04,477 D71_BLK_TYPE_GLB_LT_COEFF = 0x05,478 D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */479 D71_BLK_TYPE_GLB_SC_COEFF = 0x07,480 D71_BLK_TYPE_PERIPH = 0x08,481 D71_BLK_TYPE_LPU_TRUSTED = 0x09,482 D71_BLK_TYPE_AEU_TRUSTED = 0x0A,483 D71_BLK_TYPE_LPU_LAYER = 0x10,484 D71_BLK_TYPE_LPU_WB_LAYER = 0x11,485 D71_BLK_TYPE_CU_SPLITTER = 0x20,486 D71_BLK_TYPE_CU_SCALER = 0x21,487 D71_BLK_TYPE_CU_MERGER = 0x22,488 D71_BLK_TYPE_DOU_IPS = 0x30,489 D71_BLK_TYPE_DOU_BS = 0x31,490 D71_BLK_TYPE_DOU_FT_COEFF = 0x32,491 D71_BLK_TYPE_AEU_DS = 0x40,492 D71_BLK_TYPE_AEU_AES = 0x41,493 D71_BLK_TYPE_RESERVED = 0xFF494};495 496/* Constant of components */497#define D71_MAX_PIPELINE 2498#define D71_PIPELINE_MAX_SCALERS 2499#define D71_PIPELINE_MAX_LAYERS 4500 501#define D71_MAX_GLB_IT_COEFF 3502#define D71_MAX_GLB_SCL_COEFF 4503 504#define D71_MAX_LAYERS_PER_LPU 4505#define D71_BLOCK_MAX_INPUT 9506#define D71_BLOCK_MAX_OUTPUT 5507#define D71_MAX_SC_PER_CU 2508 509#define D71_BLOCK_OFFSET_PERIPH 0xFE00510#define D71_BLOCK_SIZE 0x0200511 512#define D71_DEFAULT_PREPRETCH_LINE 5513#define D71_BUS_WIDTH_16_BYTES 16514 515#define D71_SC_MAX_UPSCALING 64516#define D71_SC_MAX_DOWNSCALING 6517#define D71_SC_SPLIT_OVERLAP 8518#define D71_SC_ENH_SPLIT_OVERLAP 1519 520#define D71_MG_MIN_MERGED_SIZE 4521#define D71_MG_MAX_MERGED_HSIZE 4032522#define D71_MG_MAX_MERGED_VSIZE 4096523 524#define D71_PALPHA_DEF_MAP 0xFFAA5500525#define D71_LAYER_CONTROL_DEFAULT 0x30000000526#define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00527#define D71_BS_CONTROL_DEFAULT 0x00000002528 529struct block_header {530 u32 block_info;531 u32 pipeline_info;532 u32 input_ids[D71_BLOCK_MAX_INPUT];533 u32 output_ids[D71_BLOCK_MAX_OUTPUT];534};535 536static inline u32 get_block_type(struct block_header *blk)537{538 return BLOCK_INFO_BLK_TYPE(blk->block_info);539}540 541#endif /* !_D71_REG_H_ */542