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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.4 * Author: James.Qian.Wang <james.qian.wang@arm.com>5 *6 */7#ifndef _KOMEDA_DEV_H_8#define _KOMEDA_DEV_H_9 10#include <linux/device.h>11#include <linux/clk.h>12#include "komeda_pipeline.h"13#include "malidp_product.h"14#include "komeda_format_caps.h"15 16#define KOMEDA_EVENT_VSYNC BIT_ULL(0)17#define KOMEDA_EVENT_FLIP BIT_ULL(1)18#define KOMEDA_EVENT_URUN BIT_ULL(2)19#define KOMEDA_EVENT_IBSY BIT_ULL(3)20#define KOMEDA_EVENT_OVR BIT_ULL(4)21#define KOMEDA_EVENT_EOW BIT_ULL(5)22#define KOMEDA_EVENT_MODE BIT_ULL(6)23#define KOMEDA_EVENT_FULL BIT_ULL(7)24#define KOMEDA_EVENT_EMPTY BIT_ULL(8)25 26#define KOMEDA_ERR_TETO BIT_ULL(14)27#define KOMEDA_ERR_TEMR BIT_ULL(15)28#define KOMEDA_ERR_TITR BIT_ULL(16)29#define KOMEDA_ERR_CPE BIT_ULL(17)30#define KOMEDA_ERR_CFGE BIT_ULL(18)31#define KOMEDA_ERR_AXIE BIT_ULL(19)32#define KOMEDA_ERR_ACE0 BIT_ULL(20)33#define KOMEDA_ERR_ACE1 BIT_ULL(21)34#define KOMEDA_ERR_ACE2 BIT_ULL(22)35#define KOMEDA_ERR_ACE3 BIT_ULL(23)36#define KOMEDA_ERR_DRIFTTO BIT_ULL(24)37#define KOMEDA_ERR_FRAMETO BIT_ULL(25)38#define KOMEDA_ERR_CSCE BIT_ULL(26)39#define KOMEDA_ERR_ZME BIT_ULL(27)40#define KOMEDA_ERR_MERR BIT_ULL(28)41#define KOMEDA_ERR_TCF BIT_ULL(29)42#define KOMEDA_ERR_TTNG BIT_ULL(30)43#define KOMEDA_ERR_TTF BIT_ULL(31)44 45#define KOMEDA_ERR_EVENTS \46 (KOMEDA_EVENT_URUN | KOMEDA_EVENT_IBSY | KOMEDA_EVENT_OVR |\47 KOMEDA_ERR_TETO | KOMEDA_ERR_TEMR | KOMEDA_ERR_TITR |\48 KOMEDA_ERR_CPE | KOMEDA_ERR_CFGE | KOMEDA_ERR_AXIE |\49 KOMEDA_ERR_ACE0 | KOMEDA_ERR_ACE1 | KOMEDA_ERR_ACE2 |\50 KOMEDA_ERR_ACE3 | KOMEDA_ERR_DRIFTTO | KOMEDA_ERR_FRAMETO |\51 KOMEDA_ERR_ZME | KOMEDA_ERR_MERR | KOMEDA_ERR_TCF |\52 KOMEDA_ERR_TTNG | KOMEDA_ERR_TTF)53 54#define KOMEDA_WARN_EVENTS \55 (KOMEDA_ERR_CSCE | KOMEDA_EVENT_FULL | KOMEDA_EVENT_EMPTY)56 57#define KOMEDA_INFO_EVENTS (0 \58 | KOMEDA_EVENT_VSYNC \59 | KOMEDA_EVENT_FLIP \60 | KOMEDA_EVENT_EOW \61 | KOMEDA_EVENT_MODE \62 )63 64/* pipeline DT ports */65enum {66 KOMEDA_OF_PORT_OUTPUT = 0,67 KOMEDA_OF_PORT_COPROC = 1,68};69 70struct komeda_chip_info {71 u32 arch_id;72 u32 core_id;73 u32 core_info;74 u32 bus_width;75};76 77struct komeda_dev;78 79struct komeda_events {80 u64 global;81 u64 pipes[KOMEDA_MAX_PIPELINES];82};83 84/**85 * struct komeda_dev_funcs86 *87 * Supplied by chip level and returned by the chip entry function xxx_identify,88 */89struct komeda_dev_funcs {90 /**91 * @init_format_table:92 *93 * initialize &komeda_dev->format_table, this function should be called94 * before the &enum_resource95 */96 void (*init_format_table)(struct komeda_dev *mdev);97 /**98 * @enum_resources:99 *100 * for CHIP to report or add pipeline and component resources to CORE101 */102 int (*enum_resources)(struct komeda_dev *mdev);103 /** @cleanup: call to chip to cleanup komeda_dev->chip data */104 void (*cleanup)(struct komeda_dev *mdev);105 /** @connect_iommu: Optional, connect to external iommu */106 int (*connect_iommu)(struct komeda_dev *mdev);107 /** @disconnect_iommu: Optional, disconnect to external iommu */108 int (*disconnect_iommu)(struct komeda_dev *mdev);109 /**110 * @irq_handler:111 *112 * for CORE to get the HW event from the CHIP when interrupt happened.113 */114 irqreturn_t (*irq_handler)(struct komeda_dev *mdev,115 struct komeda_events *events);116 /** @enable_irq: enable irq */117 int (*enable_irq)(struct komeda_dev *mdev);118 /** @disable_irq: disable irq */119 int (*disable_irq)(struct komeda_dev *mdev);120 /** @on_off_vblank: notify HW to on/off vblank */121 void (*on_off_vblank)(struct komeda_dev *mdev,122 int master_pipe, bool on);123 124 /** @dump_register: Optional, dump registers to seq_file */125 void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);126 /**127 * @change_opmode:128 *129 * Notify HW to switch to a new display operation mode.130 */131 int (*change_opmode)(struct komeda_dev *mdev, int new_mode);132 /** @flush: Notify the HW to flush or kickoff the update */133 void (*flush)(struct komeda_dev *mdev,134 int master_pipe, u32 active_pipes);135};136 137/*138 * DISPLAY_MODE describes how many display been enabled, and which will be139 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the140 * pipeline resources assignment according to this usage hint.141 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.142 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.143 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.144 * And D71 supports assign two pipelines to one single display on mode145 * KOMEDA_MODE_DISP0/DISP1146 */147enum {148 KOMEDA_MODE_INACTIVE = 0,149 KOMEDA_MODE_DISP0 = BIT(0),150 KOMEDA_MODE_DISP1 = BIT(1),151 KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,152};153 154/**155 * struct komeda_dev156 *157 * Pipeline and component are used to describe how to handle the pixel data.158 * komeda_device is for describing the whole view of the device, and the159 * control-abilites of device.160 */161struct komeda_dev {162 /** @dev: the base device structure */163 struct device *dev;164 /** @reg_base: the base address of komeda io space */165 u32 __iomem *reg_base;166 167 /** @chip: the basic chip information */168 struct komeda_chip_info chip;169 /** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */170 struct komeda_format_caps_table fmt_tbl;171 /** @aclk: HW main engine clk */172 struct clk *aclk;173 174 /** @irq: irq number */175 int irq;176 177 /** @lock: used to protect dpmode */178 struct mutex lock;179 /** @dpmode: current display mode */180 u32 dpmode;181 182 /** @n_pipelines: the number of pipe in @pipelines */183 int n_pipelines;184 /** @pipelines: the komeda pipelines */185 struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];186 187 /** @funcs: chip funcs to access to HW */188 const struct komeda_dev_funcs *funcs;189 /**190 * @chip_data:191 *192 * chip data will be added by &komeda_dev_funcs.enum_resources() and193 * destroyed by &komeda_dev_funcs.cleanup()194 */195 void *chip_data;196 197 /** @iommu: iommu domain */198 struct iommu_domain *iommu;199 200 /** @debugfs_root: root directory of komeda debugfs */201 struct dentry *debugfs_root;202 /**203 * @err_verbosity: bitmask for how much extra info to print on error204 *205 * See KOMEDA_DEV_* macros for details. Low byte contains the debug206 * level categories, the high byte contains extra debug options.207 */208 u16 err_verbosity;209 /* Print a single line per error per frame with error events. */210#define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0)211 /* Print a single line per warning per frame with error events. */212#define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1)213 /* Print a single line per info event per frame with error events. */214#define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2)215 /* Dump DRM state on an error or warning event. */216#define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8)217 /* Disable rate limiting of event prints (normally one per commit) */218#define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12)219};220 221static inline bool222komeda_product_match(struct komeda_dev *mdev, u32 target)223{224 return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;225}226 227typedef const struct komeda_dev_funcs *228(*komeda_identify_func)(u32 __iomem *reg, struct komeda_chip_info *chip);229 230const struct komeda_dev_funcs *231d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);232 233struct komeda_dev *komeda_dev_create(struct device *dev);234void komeda_dev_destroy(struct komeda_dev *mdev);235 236struct komeda_dev *dev_to_mdev(struct device *dev);237 238void komeda_print_events(struct komeda_events *evts, struct drm_device *dev);239 240int komeda_dev_resume(struct komeda_dev *mdev);241int komeda_dev_suspend(struct komeda_dev *mdev);242 243#endif /*_KOMEDA_DEV_H_*/244