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1/*2 * Copyright (C) 2013-2015 ARM Limited3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>4 *5 * This file is subject to the terms and conditions of the GNU General Public6 * License. See the file COPYING in the main directory of this archive7 * for more details.8 *9 * Implementation of a CRTC class for the HDLCD driver.10 */11 12#include <linux/clk.h>13#include <linux/of_graph.h>14#include <linux/platform_data/simplefb.h>15 16#include <video/videomode.h>17 18#include <drm/drm_atomic.h>19#include <drm/drm_atomic_helper.h>20#include <drm/drm_crtc.h>21#include <drm/drm_fb_dma_helper.h>22#include <drm/drm_framebuffer.h>23#include <drm/drm_gem_dma_helper.h>24#include <drm/drm_of.h>25#include <drm/drm_probe_helper.h>26#include <drm/drm_vblank.h>27 28#include "hdlcd_drv.h"29#include "hdlcd_regs.h"30 31/*32 * The HDLCD controller is a dumb RGB streamer that gets connected to33 * a single HDMI transmitter or in the case of the ARM Models it gets34 * emulated by the software that does the actual rendering.35 *36 */37 38static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)39{40 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);41 42 /* stop the controller on cleanup */43 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);44 drm_crtc_cleanup(crtc);45}46 47static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)48{49 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);50 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);51 52 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);53 54 return 0;55}56 57static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)58{59 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);60 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);61 62 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);63}64 65static const struct drm_crtc_funcs hdlcd_crtc_funcs = {66 .destroy = hdlcd_crtc_cleanup,67 .set_config = drm_atomic_helper_set_config,68 .page_flip = drm_atomic_helper_page_flip,69 .reset = drm_atomic_helper_crtc_reset,70 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,71 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,72 .enable_vblank = hdlcd_crtc_enable_vblank,73 .disable_vblank = hdlcd_crtc_disable_vblank,74};75 76static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;77 78/*79 * Setup the HDLCD registers for decoding the pixels out of the framebuffer80 */81static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)82{83 unsigned int btpp;84 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);85 const struct drm_framebuffer *fb = crtc->primary->state->fb;86 uint32_t pixel_format;87 struct simplefb_format *format = NULL;88 int i;89 90 pixel_format = fb->format->format;91 92 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {93 if (supported_formats[i].fourcc == pixel_format)94 format = &supported_formats[i];95 }96 97 if (WARN_ON(!format))98 return 0;99 100 /* HDLCD uses 'bytes per pixel', zero means 1 byte */101 btpp = (format->bits_per_pixel + 7) / 8;102 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);103 104 /*105 * The format of the HDLCD_REG_<color>_SELECT register is:106 * - bits[23:16] - default value for that color component107 * - bits[11:8] - number of bits to extract for each color component108 * - bits[4:0] - index of the lowest bit to extract109 *110 * The default color value is used when bits[11:8] are zero, when the111 * pixel is outside the visible frame area or when there is a112 * buffer underrun.113 */114 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |115#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN116 0x00ff0000 | /* show underruns in red */117#endif118 ((format->red.length & 0xf) << 8));119 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |120 ((format->green.length & 0xf) << 8));121 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |122 ((format->blue.length & 0xf) << 8));123 124 return 0;125}126 127static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)128{129 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);130 struct drm_display_mode *m = &crtc->state->adjusted_mode;131 struct videomode vm;132 unsigned int polarities, err;133 134 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;135 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;136 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;137 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;138 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;139 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;140 141 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;142 143 if (m->flags & DRM_MODE_FLAG_PHSYNC)144 polarities |= HDLCD_POLARITY_HSYNC;145 if (m->flags & DRM_MODE_FLAG_PVSYNC)146 polarities |= HDLCD_POLARITY_VSYNC;147 148 /* Allow max number of outstanding requests and largest burst size */149 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,150 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);151 152 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);153 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);154 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);155 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);156 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);157 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);158 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);159 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);160 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);161 162 err = hdlcd_set_pxl_fmt(crtc);163 if (err)164 return;165 166 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);167}168 169static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,170 struct drm_atomic_state *state)171{172 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);173 174 clk_prepare_enable(hdlcd->clk);175 hdlcd_crtc_mode_set_nofb(crtc);176 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);177 drm_crtc_vblank_on(crtc);178}179 180static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,181 struct drm_atomic_state *state)182{183 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);184 185 drm_crtc_vblank_off(crtc);186 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);187 clk_disable_unprepare(hdlcd->clk);188}189 190static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,191 const struct drm_display_mode *mode)192{193 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);194 long rate, clk_rate = mode->clock * 1000;195 196 rate = clk_round_rate(hdlcd->clk, clk_rate);197 /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */198 if (abs(rate - clk_rate) * 1000 > clk_rate) {199 /* clock required by mode not supported by hardware */200 return MODE_NOCLOCK;201 }202 203 return MODE_OK;204}205 206static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,207 struct drm_atomic_state *state)208{209 struct drm_pending_vblank_event *event = crtc->state->event;210 211 if (event) {212 crtc->state->event = NULL;213 214 spin_lock_irq(&crtc->dev->event_lock);215 if (drm_crtc_vblank_get(crtc) == 0)216 drm_crtc_arm_vblank_event(crtc, event);217 else218 drm_crtc_send_vblank_event(crtc, event);219 spin_unlock_irq(&crtc->dev->event_lock);220 }221}222 223static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {224 .mode_valid = hdlcd_crtc_mode_valid,225 .atomic_begin = hdlcd_crtc_atomic_begin,226 .atomic_enable = hdlcd_crtc_atomic_enable,227 .atomic_disable = hdlcd_crtc_atomic_disable,228};229 230static int hdlcd_plane_atomic_check(struct drm_plane *plane,231 struct drm_atomic_state *state)232{233 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,234 plane);235 int i;236 struct drm_crtc *crtc;237 struct drm_crtc_state *crtc_state;238 u32 src_h = new_plane_state->src_h >> 16;239 240 /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */241 if (src_h >= HDLCD_MAX_YRES) {242 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);243 return -EINVAL;244 }245 246 for_each_new_crtc_in_state(state, crtc, crtc_state,247 i) {248 /* we cannot disable the plane while the CRTC is active */249 if (!new_plane_state->fb && crtc_state->active)250 return -EINVAL;251 return drm_atomic_helper_check_plane_state(new_plane_state,252 crtc_state,253 DRM_PLANE_NO_SCALING,254 DRM_PLANE_NO_SCALING,255 false, true);256 }257 258 return 0;259}260 261static void hdlcd_plane_atomic_update(struct drm_plane *plane,262 struct drm_atomic_state *state)263{264 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,265 plane);266 struct drm_framebuffer *fb = new_plane_state->fb;267 struct hdlcd_drm_private *hdlcd;268 u32 dest_h;269 dma_addr_t scanout_start;270 271 if (!fb)272 return;273 274 dest_h = drm_rect_height(&new_plane_state->dst);275 scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0);276 277 hdlcd = drm_to_hdlcd_priv(plane->dev);278 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);279 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);280 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);281 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);282}283 284static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {285 .atomic_check = hdlcd_plane_atomic_check,286 .atomic_update = hdlcd_plane_atomic_update,287};288 289static const struct drm_plane_funcs hdlcd_plane_funcs = {290 .update_plane = drm_atomic_helper_update_plane,291 .disable_plane = drm_atomic_helper_disable_plane,292 .reset = drm_atomic_helper_plane_reset,293 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,294 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,295};296 297static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)298{299 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);300 struct drm_plane *plane = NULL;301 u32 formats[ARRAY_SIZE(supported_formats)], i;302 303 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)304 formats[i] = supported_formats[i].fourcc;305 306 plane = drmm_universal_plane_alloc(drm, struct drm_plane, dev, 0xff,307 &hdlcd_plane_funcs,308 formats, ARRAY_SIZE(formats),309 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);310 if (IS_ERR(plane))311 return plane;312 313 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);314 hdlcd->plane = plane;315 316 return plane;317}318 319int hdlcd_setup_crtc(struct drm_device *drm)320{321 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);322 struct drm_plane *primary;323 int ret;324 325 primary = hdlcd_plane_init(drm);326 if (IS_ERR(primary))327 return PTR_ERR(primary);328 329 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,330 &hdlcd_crtc_funcs, NULL);331 if (ret)332 return ret;333 334 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);335 return 0;336}337