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1/* SPDX-License-Identifier: GPL-2.0+ */2/* Copyright 2018 IBM Corporation */3 4#include <drm/drm_device.h>5#include <drm/drm_simple_kms_helper.h>6 7struct aspeed_gfx {8 struct drm_device drm;9 void __iomem *base;10 struct clk *clk;11 struct reset_control *rst;12 struct regmap *scu;13 14 u32 dac_reg;15 u32 int_clr_reg;16 u32 vga_scratch_reg;17 u32 throd_val;18 u32 scan_line_max;19 20 struct drm_simple_display_pipe pipe;21 struct drm_connector connector;22};23#define to_aspeed_gfx(x) container_of(x, struct aspeed_gfx, drm)24 25int aspeed_gfx_create_pipe(struct drm_device *drm);26int aspeed_gfx_create_output(struct drm_device *drm);27 28#define CRT_CTRL1 0x60 /* CRT Control I */29#define CRT_CTRL2 0x64 /* CRT Control II */30#define CRT_STATUS 0x68 /* CRT Status */31#define CRT_MISC 0x6c /* CRT Misc Setting */32#define CRT_HORIZ0 0x70 /* CRT Horizontal Total & Display Enable End */33#define CRT_HORIZ1 0x74 /* CRT Horizontal Retrace Start & End */34#define CRT_VERT0 0x78 /* CRT Vertical Total & Display Enable End */35#define CRT_VERT1 0x7C /* CRT Vertical Retrace Start & End */36#define CRT_ADDR 0x80 /* CRT Display Starting Address */37#define CRT_OFFSET 0x84 /* CRT Display Offset & Terminal Count */38#define CRT_THROD 0x88 /* CRT Threshold */39#define CRT_XSCALE 0x8C /* CRT Scaling-Up Factor */40#define CRT_CURSOR0 0x90 /* CRT Hardware Cursor X & Y Offset */41#define CRT_CURSOR1 0x94 /* CRT Hardware Cursor X & Y Position */42#define CRT_CURSOR2 0x98 /* CRT Hardware Cursor Pattern Address */43#define CRT_9C 0x9C44#define CRT_OSD_H 0xA0 /* CRT OSD Horizontal Start/End */45#define CRT_OSD_V 0xA4 /* CRT OSD Vertical Start/End */46#define CRT_OSD_ADDR 0xA8 /* CRT OSD Pattern Address */47#define CRT_OSD_DISP 0xAC /* CRT OSD Offset */48#define CRT_OSD_THRESH 0xB0 /* CRT OSD Threshold & Alpha */49#define CRT_B4 0xB450#define CRT_STS_V 0xB8 /* CRT Status V */51#define CRT_SCRATCH 0xBC /* Scratchpad */52#define CRT_BB0_ADDR 0xD0 /* CRT Display BB0 Starting Address */53#define CRT_BB1_ADDR 0xD4 /* CRT Display BB1 Starting Address */54#define CRT_BB_COUNT 0xD8 /* CRT Display BB Terminal Count */55#define OSD_COLOR1 0xE0 /* OSD Color Palette Index 1 & 0 */56#define OSD_COLOR2 0xE4 /* OSD Color Palette Index 3 & 2 */57#define OSD_COLOR3 0xE8 /* OSD Color Palette Index 5 & 4 */58#define OSD_COLOR4 0xEC /* OSD Color Palette Index 7 & 6 */59#define OSD_COLOR5 0xF0 /* OSD Color Palette Index 9 & 8 */60#define OSD_COLOR6 0xF4 /* OSD Color Palette Index 11 & 10 */61#define OSD_COLOR7 0xF8 /* OSD Color Palette Index 13 & 12 */62#define OSD_COLOR8 0xFC /* OSD Color Palette Index 15 & 14 */63 64/* CTRL1 */65#define CRT_CTRL_EN BIT(0)66#define CRT_CTRL_HW_CURSOR_EN BIT(1)67#define CRT_CTRL_OSD_EN BIT(2)68#define CRT_CTRL_INTERLACED BIT(3)69#define CRT_CTRL_COLOR_RGB565 (0 << 7)70#define CRT_CTRL_COLOR_YUV444 (1 << 7)71#define CRT_CTRL_COLOR_XRGB8888 (2 << 7)72#define CRT_CTRL_COLOR_RGB888 (3 << 7)73#define CRT_CTRL_COLOR_YUV444_2RGB (5 << 7)74#define CRT_CTRL_COLOR_YUV422 (7 << 7)75#define CRT_CTRL_COLOR_MASK GENMASK(9, 7)76#define CRT_CTRL_HSYNC_NEGATIVE BIT(16)77#define CRT_CTRL_VSYNC_NEGATIVE BIT(17)78#define CRT_CTRL_VERTICAL_INTR_EN BIT(30)79#define CRT_CTRL_VERTICAL_INTR_STS BIT(31)80 81/* CTRL2 */82#define CRT_CTRL_DAC_EN BIT(0)83#define CRT_CTRL_VBLANK_LINE(x) (((x) << 20) & CRT_CTRL_VBLANK_LINE_MASK)84#define CRT_CTRL_VBLANK_LINE_MASK GENMASK(31, 20)85 86/* CRT_HORIZ0 */87#define CRT_H_TOTAL(x) (x)88#define CRT_H_DE(x) ((x) << 16)89 90/* CRT_HORIZ1 */91#define CRT_H_RS_START(x) (x)92#define CRT_H_RS_END(x) ((x) << 16)93 94/* CRT_VIRT0 */95#define CRT_V_TOTAL(x) (x)96#define CRT_V_DE(x) ((x) << 16)97 98/* CRT_VIRT1 */99#define CRT_V_RS_START(x) (x)100#define CRT_V_RS_END(x) ((x) << 16)101 102/* CRT_OFFSET */103#define CRT_DISP_OFFSET(x) (x)104#define CRT_TERM_COUNT(x) ((x) << 16)105 106/* CRT_THROD */107#define CRT_THROD_LOW(x) (x)108#define CRT_THROD_HIGH(x) ((x) << 8)109