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1/*2 * Copyright 2012 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the6 * "Software"), to deal in the Software without restriction, including7 * without limitation the rights to use, copy, modify, merge, publish,8 * distribute, sub license, and/or sell copies of the Software, and to9 * permit persons to whom the Software is furnished to do so, subject to10 * the following conditions:11 *12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE18 * USE OR OTHER DEALINGS IN THE SOFTWARE.19 *20 * The above copyright notice and this permission notice (including the21 * next paragraph) shall be included in all copies or substantial portions22 * of the Software.23 *24 */25/*26 * Authors: Dave Airlie <airlied@redhat.com>27 */28 29#include <linux/module.h>30#include <linux/of.h>31#include <linux/pci.h>32 33#include <drm/drm_aperture.h>34#include <drm/drm_atomic_helper.h>35#include <drm/drm_drv.h>36#include <drm/drm_fbdev_shmem.h>37#include <drm/drm_gem_shmem_helper.h>38#include <drm/drm_module.h>39#include <drm/drm_probe_helper.h>40 41#include "ast_drv.h"42 43static int ast_modeset = -1;44 45MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");46module_param_named(modeset, ast_modeset, int, 0400);47 48/*49 * DRM driver50 */51 52DEFINE_DRM_GEM_FOPS(ast_fops);53 54static const struct drm_driver ast_driver = {55 .driver_features = DRIVER_ATOMIC |56 DRIVER_GEM |57 DRIVER_MODESET,58 59 .fops = &ast_fops,60 .name = DRIVER_NAME,61 .desc = DRIVER_DESC,62 .date = DRIVER_DATE,63 .major = DRIVER_MAJOR,64 .minor = DRIVER_MINOR,65 .patchlevel = DRIVER_PATCHLEVEL,66 67 DRM_GEM_SHMEM_DRIVER_OPS68};69 70/*71 * PCI driver72 */73 74#define PCI_VENDOR_ASPEED 0x1a0375 76#define AST_VGA_DEVICE(id, info) { \77 .class = PCI_BASE_CLASS_DISPLAY << 16, \78 .class_mask = 0xff0000, \79 .vendor = PCI_VENDOR_ASPEED, \80 .device = id, \81 .subvendor = PCI_ANY_ID, \82 .subdevice = PCI_ANY_ID, \83 .driver_data = (unsigned long) info }84 85static const struct pci_device_id ast_pciidlist[] = {86 AST_VGA_DEVICE(PCI_CHIP_AST2000, NULL),87 AST_VGA_DEVICE(PCI_CHIP_AST2100, NULL),88 {0, 0, 0},89};90 91MODULE_DEVICE_TABLE(pci, ast_pciidlist);92 93static bool ast_is_vga_enabled(void __iomem *ioregs)94{95 u8 vgaer = __ast_read8(ioregs, AST_IO_VGAER);96 97 return vgaer & AST_IO_VGAER_VGA_ENABLE;98}99 100static void ast_enable_vga(void __iomem *ioregs)101{102 __ast_write8(ioregs, AST_IO_VGAER, AST_IO_VGAER_VGA_ENABLE);103 __ast_write8(ioregs, AST_IO_VGAMR_W, AST_IO_VGAMR_IOSEL);104}105 106/*107 * Run this function as part of the HW device cleanup; not108 * when the DRM device gets released.109 */110static void ast_enable_mmio_release(void *data)111{112 void __iomem *ioregs = (void __force __iomem *)data;113 114 /* enable standard VGA decode */115 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED);116}117 118static int ast_enable_mmio(struct device *dev, void __iomem *ioregs)119{120 void *data = (void __force *)ioregs;121 122 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1,123 AST_IO_VGACRA1_MMIO_ENABLED |124 AST_IO_VGACRA1_VGAIO_DISABLED);125 126 return devm_add_action_or_reset(dev, ast_enable_mmio_release, data);127}128 129static void ast_open_key(void __iomem *ioregs)130{131 __ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD);132}133 134static int ast_detect_chip(struct pci_dev *pdev,135 void __iomem *regs, void __iomem *ioregs,136 enum ast_chip *chip_out,137 enum ast_config_mode *config_mode_out)138{139 struct device *dev = &pdev->dev;140 struct device_node *np = dev->of_node;141 enum ast_config_mode config_mode = ast_use_defaults;142 uint32_t scu_rev = 0xffffffff;143 enum ast_chip chip;144 u32 data;145 u8 vgacrd0, vgacrd1;146 147 /*148 * Find configuration mode and read SCU revision149 */150 151 /* Check if we have device-tree properties */152 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) {153 /* We do, disable P2A access */154 config_mode = ast_use_dt;155 scu_rev = data;156 } else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge157 /*158 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge159 * is disabled. We force using P2A if VGA only mode bit160 * is set D[7]161 */162 vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0);163 vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1);164 if (!(vgacrd0 & 0x80) || !(vgacrd1 & 0x10)) {165 166 /*167 * We have a P2A bridge and it is enabled.168 */169 170 /* Patch AST2500/AST2510 */171 if ((pdev->revision & 0xf0) == 0x40) {172 if (!(vgacrd0 & AST_VRAM_INIT_STATUS_MASK))173 ast_patch_ahb_2500(regs);174 }175 176 /* Double check that it's actually working */177 data = __ast_read32(regs, 0xf004);178 if ((data != 0xffffffff) && (data != 0x00)) {179 config_mode = ast_use_p2a;180 181 /* Read SCU7c (silicon revision register) */182 __ast_write32(regs, 0xf004, 0x1e6e0000);183 __ast_write32(regs, 0xf000, 0x1);184 scu_rev = __ast_read32(regs, 0x1207c);185 }186 }187 }188 189 switch (config_mode) {190 case ast_use_defaults:191 dev_info(dev, "Using default configuration\n");192 break;193 case ast_use_dt:194 dev_info(dev, "Using device-tree for configuration\n");195 break;196 case ast_use_p2a:197 dev_info(dev, "Using P2A bridge for configuration\n");198 break;199 }200 201 /*202 * Identify chipset203 */204 205 if (pdev->revision >= 0x50) {206 chip = AST2600;207 dev_info(dev, "AST 2600 detected\n");208 } else if (pdev->revision >= 0x40) {209 switch (scu_rev & 0x300) {210 case 0x0100:211 chip = AST2510;212 dev_info(dev, "AST 2510 detected\n");213 break;214 default:215 chip = AST2500;216 dev_info(dev, "AST 2500 detected\n");217 break;218 }219 } else if (pdev->revision >= 0x30) {220 switch (scu_rev & 0x300) {221 case 0x0100:222 chip = AST1400;223 dev_info(dev, "AST 1400 detected\n");224 break;225 default:226 chip = AST2400;227 dev_info(dev, "AST 2400 detected\n");228 break;229 }230 } else if (pdev->revision >= 0x20) {231 switch (scu_rev & 0x300) {232 case 0x0000:233 chip = AST1300;234 dev_info(dev, "AST 1300 detected\n");235 break;236 default:237 chip = AST2300;238 dev_info(dev, "AST 2300 detected\n");239 break;240 }241 } else if (pdev->revision >= 0x10) {242 switch (scu_rev & 0x0300) {243 case 0x0200:244 chip = AST1100;245 dev_info(dev, "AST 1100 detected\n");246 break;247 case 0x0100:248 chip = AST2200;249 dev_info(dev, "AST 2200 detected\n");250 break;251 case 0x0000:252 chip = AST2150;253 dev_info(dev, "AST 2150 detected\n");254 break;255 default:256 chip = AST2100;257 dev_info(dev, "AST 2100 detected\n");258 break;259 }260 } else {261 chip = AST2000;262 dev_info(dev, "AST 2000 detected\n");263 }264 265 *chip_out = chip;266 *config_mode_out = config_mode;267 268 return 0;269}270 271static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)272{273 struct device *dev = &pdev->dev;274 int ret;275 void __iomem *regs;276 void __iomem *ioregs;277 enum ast_config_mode config_mode;278 enum ast_chip chip;279 struct drm_device *drm;280 bool need_post = false;281 282 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &ast_driver);283 if (ret)284 return ret;285 286 ret = pcim_enable_device(pdev);287 if (ret)288 return ret;289 290 regs = pcim_iomap_region(pdev, 1, "ast");291 if (IS_ERR(regs))292 return PTR_ERR(regs);293 294 if (pdev->revision >= 0x40) {295 /*296 * On AST2500 and later models, MMIO is enabled by297 * default. Adopt it to be compatible with ARM.298 */299 resource_size_t len = pci_resource_len(pdev, 1);300 301 if (len < AST_IO_MM_OFFSET)302 return -EIO;303 if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)304 return -EIO;305 ioregs = regs + AST_IO_MM_OFFSET;306 } else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {307 /*308 * Map I/O registers if we have a PCI BAR for I/O.309 */310 resource_size_t len = pci_resource_len(pdev, 2);311 312 if (len < AST_IO_MM_LENGTH)313 return -EIO;314 ioregs = pcim_iomap_region(pdev, 2, "ast");315 if (IS_ERR(ioregs))316 return PTR_ERR(ioregs);317 } else {318 /*319 * Anything else is best effort.320 */321 resource_size_t len = pci_resource_len(pdev, 1);322 323 if (len < AST_IO_MM_OFFSET)324 return -EIO;325 if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)326 return -EIO;327 ioregs = regs + AST_IO_MM_OFFSET;328 329 dev_info(dev, "Platform has no I/O space, using MMIO\n");330 }331 332 if (!ast_is_vga_enabled(ioregs)) {333 dev_info(dev, "VGA not enabled on entry, requesting chip POST\n");334 need_post = true;335 }336 337 /*338 * If VGA isn't enabled, we need to enable now or subsequent339 * access to the scratch registers will fail.340 */341 if (need_post)342 ast_enable_vga(ioregs);343 /* Enable extended register access */344 ast_open_key(ioregs);345 346 ret = ast_enable_mmio(dev, ioregs);347 if (ret)348 return ret;349 350 ret = ast_detect_chip(pdev, regs, ioregs, &chip, &config_mode);351 if (ret)352 return ret;353 354 drm = ast_device_create(pdev, &ast_driver, chip, config_mode, regs, ioregs, need_post);355 if (IS_ERR(drm))356 return PTR_ERR(drm);357 pci_set_drvdata(pdev, drm);358 359 ret = drm_dev_register(drm, ent->driver_data);360 if (ret)361 return ret;362 363 drm_fbdev_shmem_setup(drm, 32);364 365 return 0;366}367 368static void ast_pci_remove(struct pci_dev *pdev)369{370 struct drm_device *dev = pci_get_drvdata(pdev);371 372 drm_dev_unregister(dev);373 drm_atomic_helper_shutdown(dev);374}375 376static void ast_pci_shutdown(struct pci_dev *pdev)377{378 drm_atomic_helper_shutdown(pci_get_drvdata(pdev));379}380 381static int ast_drm_freeze(struct drm_device *dev)382{383 int error;384 385 error = drm_mode_config_helper_suspend(dev);386 if (error)387 return error;388 pci_save_state(to_pci_dev(dev->dev));389 return 0;390}391 392static int ast_drm_thaw(struct drm_device *dev)393{394 struct ast_device *ast = to_ast_device(dev);395 396 ast_enable_vga(ast->ioregs);397 ast_open_key(ast->ioregs);398 ast_enable_mmio(dev->dev, ast->ioregs);399 ast_post_gpu(dev);400 401 return drm_mode_config_helper_resume(dev);402}403 404static int ast_drm_resume(struct drm_device *dev)405{406 if (pci_enable_device(to_pci_dev(dev->dev)))407 return -EIO;408 409 return ast_drm_thaw(dev);410}411 412static int ast_pm_suspend(struct device *dev)413{414 struct pci_dev *pdev = to_pci_dev(dev);415 struct drm_device *ddev = pci_get_drvdata(pdev);416 int error;417 418 error = ast_drm_freeze(ddev);419 if (error)420 return error;421 422 pci_disable_device(pdev);423 pci_set_power_state(pdev, PCI_D3hot);424 return 0;425}426 427static int ast_pm_resume(struct device *dev)428{429 struct pci_dev *pdev = to_pci_dev(dev);430 struct drm_device *ddev = pci_get_drvdata(pdev);431 return ast_drm_resume(ddev);432}433 434static int ast_pm_freeze(struct device *dev)435{436 struct pci_dev *pdev = to_pci_dev(dev);437 struct drm_device *ddev = pci_get_drvdata(pdev);438 return ast_drm_freeze(ddev);439}440 441static int ast_pm_thaw(struct device *dev)442{443 struct pci_dev *pdev = to_pci_dev(dev);444 struct drm_device *ddev = pci_get_drvdata(pdev);445 return ast_drm_thaw(ddev);446}447 448static int ast_pm_poweroff(struct device *dev)449{450 struct pci_dev *pdev = to_pci_dev(dev);451 struct drm_device *ddev = pci_get_drvdata(pdev);452 453 return ast_drm_freeze(ddev);454}455 456static const struct dev_pm_ops ast_pm_ops = {457 .suspend = ast_pm_suspend,458 .resume = ast_pm_resume,459 .freeze = ast_pm_freeze,460 .thaw = ast_pm_thaw,461 .poweroff = ast_pm_poweroff,462 .restore = ast_pm_resume,463};464 465static struct pci_driver ast_pci_driver = {466 .name = DRIVER_NAME,467 .id_table = ast_pciidlist,468 .probe = ast_pci_probe,469 .remove = ast_pci_remove,470 .shutdown = ast_pci_shutdown,471 .driver.pm = &ast_pm_ops,472};473 474drm_module_pci_driver_if_modeset(ast_pci_driver, ast_modeset);475 476MODULE_AUTHOR(DRIVER_AUTHOR);477MODULE_DESCRIPTION(DRIVER_DESC);478MODULE_LICENSE("GPL and additional rights");479